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* octopus: lock gpio config for reset signalJett Rink2019-10-191-1/+6
| | | | | | | | | | | | | BRANCH=octopus BUG=b:142953493 TEST=verify that later modification of gpio flag will no allow driving signal high. Change-Id: I0b8c1503ba8c03afa3eb6fa4f921b3480106f05b Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1869407 Commit-Queue: Edward Hill <ecgh@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org>
* tablet_mode: Renaming for GMR sensorPhilip Chen2019-09-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | GMR sensors can be used to (1) detect clamshell/tablet mode (2) detect lid open/closed But hall sensors can only do (2). Therefore the naming related to "hall sensor" for tablet mode application is incorrect. This patch performs the following renaming to better reflect the reality: config: CONFIG_HALL_SENSOR -> CONFIG_GMR_TABLET_MODE CONFIG_HALL_SENSOR_CUSTOM -> CONFIG_GMR_TABLET_MODE_CUSTOM CONFIG_DPTF_MOTION_LID_NO_HALL_SENSOR -> CONFIG_DPTF_MOTION_LID_NO_GMR_SENSOR GPIO: HALL_SENSOR_GPIO_L -> GMR_TABLET_MODE_GPIO_L functions: hall_sensor_disable() -> gmr_tablet_switch_disable() hall_sensor_isr() -> gmr_tablet_switch_isr() hall_sensor_int() -> gmr_tablet_switch_init() variable: hall_sensor_at_360 -> gmr_sensor_at_360 BUG=b:139378190 BRANCH=none TEST=make buildall Change-Id: I28393d056ddd128d8ffafc16a1f9fefee5455ccc Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1757275 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org>
* octopus: convert boards to use hardware intJett Rink2019-01-101-0/+3
| | | | | | | | | | | | | | | | | | Recent kernel changes expect the EC to use a dedicated interrupt pin from the EC to the AP to notify the AP of pending sensor data (instead of using an eSPI "interrupt"). The octopus boards have this hardware support, we just need to enable the EC use it. BRANCH=octopus BUG=b:122552125,b:120679547 TEST=perform sensor tests on various octopus boards Change-Id: I2bd3ffe14947d5f1ec71acbb53fcac962b007cf9 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1403103 Reviewed-by: Enrico Granata <egranata@chromium.org>
* gpio: Add configuration for EC_PCH_RTCRST GPIO in octopus boardsKarthikeyan Ramasubramanian2018-12-051-0/+1
| | | | | | | | | | | | | | | | | | | This will help with using the hardware support to reset the RTC on the SoC. BUG=b:119678692 BRANCH=octopus TEST=make -j buildall && Boot to ChromeOS. Create a forced scenario to trigger an RTC reset and ensure that EC does not get reset while the SoC boots to ChromeOS. Execute warm reboot from AP, cold reboot from EC and wake from ec hibernate (10 iterations each) and suspend_stress_test for 50 iterations successfully. Change-Id: Ib79012b43e397d4c27ca829b135115bebf77dedb Signed-off-by: Karthikeyan Ramasubramanian <kramasub@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1354493 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* tablet_mode: Introduce hall sensor specific handlingFurquan Shaikh2018-11-291-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change performs the following renaming: 1. CONFIG_TABLET_SWITCH -> CONFIG_HALL_SENSOR Indicates if a device has hall sensor 2. TABLET_MODE_GPIO_L -> HALL_SENSOR_GPIO_L Provides the interrupt line from hall sensor to EC. 3. tablet_mode_isr -> hall_sensor_isr Interrupt routine that gets control on hall sensor interrupt. 4. tablet_mode_init -> hall_sensor_init Init routine for initializing hall sensor interrupt. 5. tablet_switch_disable -> hall_sensor_disable Disable hall sensor interrupt and tablet mode sub-system. This is done to separate hall sensor interrupt from tablet mode handling. It is another step towards aligning tablet mode detection on EC with Chrome. Hall sensor interrupt occurs when the lid is in 360-degree flipped mode. If tablet mode is not already triggered by lid motion driver, then hall_sensor_isr will set tablet mode and take necessary actions to disable input peripherals. CQ-DEPEND=CL:1351518 BUG=b:120050761 BRANCH=octopus TEST=make -j buildall Change-Id: I5841f6875d538a624cb888bc048f252397ab457c Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1350469 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* Octopus: add reset logic for C0 TCPCDiana Z2018-10-091-0/+3
| | | | | | | | | | | | | | | | | This change adds a call to the C0 TCPC reset for standalone TCPC boards which have that pin hooked up in hardware, and adds the GPIO as unimplemented for boards which do not have this yet. BRANCH=None BUG=b:112756630 TEST=Added a log print and rebooted EC on bobba to verify TCPC C0 reset, then verified that charging on C0 worked. Also imaged yorp proto 2 and rebooted, verifying C0 reset was not attempted. Change-Id: I615861f0d9ce9b5a89692e3982ed2e19c7e0b237 Signed-off-by: Diana Z <dzigterman@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1257647 Reviewed-by: Jett Rink <jettrink@chromium.org>
* Octopus: Add CCD_MODE_ODL to GPIO listDiana Z2018-10-011-0/+3
| | | | | | | | | | | | | | | This change adds CCD_MODE_ODL as an input for all octopus boards so it will be present in the "gpioget" output for debugging. BRANCH=None BUG=b:116849648 TEST=builds, confirmed net showed up on bip and yorp proto 2 Change-Id: I0da194e433444f160f10573c27e5e463694adf38 Signed-off-by: Diana Z <dzigterman@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1254923 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
* yorp: Add PSL supportScott Collyer2018-07-201-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | This CL enables PSL mode for the following wake sources: 1. LID_OPEN 2. AC_PRESENT 3. POWER_BUTTON 4. EC_RST_ODL BUG=b:79220888 BRANCH=None TEST=Tested the wake sources and ensured that the EC woke up for each case after putting the EC into hibernate mode. Also observed the pp3300_ec_mw and pp3300_pd_a_mw INA measurements. Verified that when PSL mode is entered, these both drop to 0 mW as expected. Change-Id: Ib565a40228e5abcdbf8b0ba6174f69bf216282f4 Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/1144260 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* yorp: Deprecate yorp v0 supportFurquan Shaikh2018-07-181-31/+15
| | | | | | | | | | | | | | | This change gets rid of yorp v0 support from EC codebase. BUG=b:111545725 BRANCH=None TEST=Boots to OS. Change-Id: I1db238ce673a576b913e92874d0f1de730c04b05 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1140742 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* yorp: add internal PUs for unused pins to prevent leakage current.Mulin Chao2018-06-281-0/+7
| | | | | | | | | | | | | | | | | | | This CL adds internal PUs for unused pins on yorp in gpio.inc to prevent leakage current. Please notice the test platform is yorp proto 1. Beside PUs for strap-pins, the configuration of other pins might need to change on yorp proto 2. BRANCH=none BUG=b:110170824 TEST=No build errors for npcx7 series. Adding PUs on strap-pins saves ~0.4mA at S0ix. Adding PUs on the other unused pin saves ~0.2mA at S0ix. Change-Id: If2406f9fca12f7b3456301435f8ec25cb264ed3a Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/1092391 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* yorp: Program PWM3 alternate function based on board versionFurquan Shaikh2018-06-191-1/+7
| | | | | | | | | | | | | | | | | | | | GPIO80 is used for ENTERING_RW signal on V0 whereas it is used as an alternate function for KB_BL_PWM on V1+. Configuring the alternate function in gpio.inc breaks V0 boards w.r.t. ENTERING_RW signal. This change moves the configuration of alternate function for PWM3 to update_drivers_from_board_id. BUG=b:110084012 BRANCH=None TEST=Verified that firmware_DevMode passes. Change-Id: I82bf5df685d40981b70767008dafbe76ccb20ddf Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1106289 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* yorp: Fix GPIO PIN for ENTERING_RW_V0Furquan Shaikh2018-06-191-1/+1
| | | | | | | | | | | | | | | | | | ENTERING_RW_V0 is GPIO80 on yorp V0. This change fixes the pin configuration in gpio.inc BUG=b:110084012 BRANCH=None TEST=Verified that firmware_DevMode test passes along with the other set of CLs. Change-Id: I77c80c5b6926003cc678e4a0d2a1f11bef140f92 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1106288 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
* gpio: fixed GPIO_SEL_1P8V is cleared unexpectedly during i2c unwedging.Mulin Chao2018-06-121-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | For npcx ec, board driver needs to add GPIO_SEL_1P8V flag for SDA/SCL pins in gpio.inc when i2c port is configured to support low-voltage mode (1.8V). Npcx gpio driver will set the corresponding bits in LV_GPIO_CTL register later. But if there is an i2c unwedging mechanism occurred on those 1.8V i2c port, the bits of LV_GPIO_CTL will be cleared unexpectedly after unweding is completed. And it also will make ec consumes more 0.5mA current on each pin since IO is selected to 3.3V. The root cause is the GPIO flags of SCL/SDA have been changed to zero only after i2c unweding is done. This CL which solved this issue includes: 1. Add GPIO_INPUT and GPIO_SEL_1P8V flag in ALTERNATE macro array which pins belong to 1.8V i2c port. 2. Change type of flags in structure gpio_alt_func from uint16_t to uint32_t since bit overflow. BRANCH=none BUG=b:109884927 TEST=No build errors for npcx7 series. Saving 3.3mW power consumption on yorp if this patch is applied. Change-Id: I06eadd5df36c7f69e6741f1dee13c801bac18360 Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/1089604 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* yorp: update gpio and functionality based on latest schematicJett Rink2018-06-071-25/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Change GPIO signals at runtime based on board version - SYS_RESTET_L, ENTERING_RW, USB2_OTG_ID - Add 2nd signal for 2nd USB-A port BC1.2 outbound charging - (GPIO96) USB_A1_CHARGE_EN_L (V1) maps to EN_BRD_ID (V0) so we can just enable the USBA port 1 signal on V0 with only a small power drain. It is not worth the EC codebase churn to add support for changing the number of USB-A ports at runtime (since it is a compile time constant now) - Yorp V0 is the only board that set USB_PORT_COUNT to 1 so we can make common octopus code only have the 2 port case. - Add placeholders for LED_3_L, WFCAM_VSYNC - Updated signal name comments to match schematics - Formatting cleanup for consistency BRANCH=none BUG=b:109747036,b:74388692 TEST=verified `sysjump rw` does not brown out board when only powering with USB C1 without battery. Since GPIO_C1_EN_SNK_V0 moved, the board would lock power out if GPIOs state was not maintained properly through sysjump transition. Change-Id: Ie4c72699ab23ee6f7d2fa77a78709e5b4343e46f Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1087815 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* octopus: remove ADCs for VBUSJett Rink2018-06-071-2/+0
| | | | | | | | | | | | | | | Hardware does not support ADCs for Vbus anymore for all boards except bip. Make bip the same as other octopus boards (i.e. not using ADCs for Vbus measurements). BRANCH=none BUG=b:109747036 TEST=CL stack works with current yorp Change-Id: I96b82b70799e8b70bf5d479a1714524fc1652140 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1089199 Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* octopus: rename USB-C signal namesJett Rink2018-06-071-4/+4
| | | | | | | | | | | | | | | Simple rename of gpio based on newest schematics for yorp and phaser BRANCH=none BUG=b:109747036,b:109747361 TEST=build Change-Id: I08d9010f16e623ca41bb66363d568c4b5bd687e8 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1089040 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* yorp: enable interrupt for base accel sensorJagadish Krishnamoorthy2018-05-301-2/+1
| | | | | | | | | | | | | | | | | Configure the accel sensor gpio to interrupt. Enable CONFIG_ACCEL_INTERRUPTS and CONFIG_ACCEL_FIFO to activate FIFO mode. BUG=b:74932344 BRANCH=NONE TEST=On Yorp board, "accelinfo on 1000" should output BASE ACCEL values. Change-Id: Icecbbe604b32b6bd691558d2898896f6d1443f19 Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1073645 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* yorp: drive PPC EN_SNK from TCPC gpioJett Rink2018-05-291-2/+4
| | | | | | | | | | | | | Since the PS8751 is now driving the EN_SNK GPIO on the PPC, we cannot reset without a battery otherwise we will brown out the board. BRANCH=none BUG=b:78896495,b:78021059 TEST=verified with reworked board. Change-Id: Ibadf46de922c49f5fdd08c43991e71f852ff7600 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1067711
* yorp: add keyboard backlight controlJett Rink2018-05-231-1/+4
| | | | | | | | | | | | | | Enable PWM control of backlight in EC for yorp and phaser. Proto build of bip will not have backlight control in EC. BRANCH=none BUG=b:79422226 TEST=none (no hardware to test with) Change-Id: Ib6ed4af4de3145b112ed43b4ca1ec9f931f3875f Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1050785 Reviewed-by: Justin TerAvest <teravest@chromium.org>
* octopus: implement device modeJagadish Krishnamoorthy2018-05-221-0/+2
| | | | | | | | | | | | | | | | | | To enable device mode, set the gpio USB2_OTG_ID in the respective boards to high. Pull the gpio low to disable device mode. BUG=b:79343083 BRANCH=NONE TEST=On Yorp board, for UFP mode gpio USB2_OTG_ID should be high, for DFP mode gpio USB2_OTG_ID should be low. In OS console, lspci should list xdci. (with chromiumos/third_party/coreboot/+/1064592) Change-Id: I70f13a9705626d9bcbe989239f6826d35d8fa536 Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1058832 Reviewed-by: Jett Rink <jettrink@chromium.org>
* octopus: enable trackpad (S3+) and backlight (S0)Jett Rink2018-05-181-2/+5
| | | | | | | | | | | | | | | | Enable trackpad when entering S3, and display backlight when entering S0 and disable them on the opposite transition. Moving common code to baseboard. BRANCH=none BUG=b:79900266 TEST=bip trackpad works in S3 as wake source. backlight turns off in S0ix and S3. Change-Id: I0937771093d87c020b3c0d94a482d108c5a5c180 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1064693 Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* yorp: Enable tablet modeDivya Sasidharan2018-05-171-0/+6
| | | | | | | | | | | | | | | | Enables tablet mode to change screen rotation with respect to portrait / landscape mode. BUG=b:78898771 BRANCH=None TEST=make buildall -j Change-Id: Ib959daee5b2dfa24b0a31e6bbf91f238d251abd0 Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1038605 Commit-Ready: Divya S Sasidharan <divya.s.sasidharan@intel.com> Tested-by: Divya S Sasidharan <divya.s.sasidharan@intel.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* yorp: Configure GPIO_HIB_WAKE_HIGH for AC_PRESENTFurquan Shaikh2018-05-071-2/+4
| | | | | | | | | | | | | | | | AC_PRESENT is active high and hence GPIO_HIB_WAKE_HIGH needs to be set in order to wake the EC up from hibernate. BUG=b:79220888 BRANCH=None TEST=make -j BOARD=yorp Change-Id: I91e1c2f0b615b8272d3d1916a284d34a56959f82 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1043343 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* octopus: remove pwm code for LEDsJett Rink2018-05-041-1/+0
| | | | | | | | | | | | | We are using LED as straight GPIO signals so remove pwm for now BRANCH=none BUG=none TEST=none Change-Id: I48b316b6df023217a7cc1bed7a741f72d1388026 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1042728 Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* yorp: Control backlight based on chipset transitionsFurquan Shaikh2018-05-021-0/+1
| | | | | | | | | | | | | | | | | | This change enables/disables backlight based on the chipset state transition. BUG=b:78897667 BRANCH=None TEST=None Change-Id: I4da331cb94f7a304a76fce93b73c38016f5b0f4d Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1036798 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
* board/yorp: fix PMIC_EN gpioAaron Durbin2018-04-251-1/+1
| | | | | | | | | | | | | | | | | | | | | | Apparently the symbol in the yorp schematic is incorrect for our part. The PMIC_EN signal on ball H6 is actually GPIO72 -- not GPIOD7. Adjust the gpio used for PMIC_EN. Note: GPIO72 needs to be put in gpio mode since it defaults to PWRGD functionality. However, gpio_pre_init() in chip/npcx/gpio.c enables gpio functionality by default. If that changes, the board options will need to change as well. BUG=b:78352179 TEST=Built. Booted. PMIC_EN goes up and down as expected. BRANCH=none Change-Id: I955f9a24e0fbecb0cda1380c237fa44c9a575e45 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1026375 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
* yorp: Enable temperature sensorsDivya Sasidharan2018-04-241-0/+1
| | | | | | | | | | | | | BUG=b:77944804 BRANCH=None TEST=On yorp; test adc values, verify they are valid. Change-Id: I64191f33c594d8869391bab813902f59a63d2ea1 Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1018118 Commit-Ready: Divya Sasidharan <divya.s.sasidharan@intel.corp-partner.google.com> Tested-by: Divya Sasidharan <divya.s.sasidharan@intel.corp-partner.google.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* yorp: use cbi for board versionJett Rink2018-04-131-3/+0
| | | | | | | | | | | | | | | | | | | | | Replace ADC-based board version with CBI/EEPROM board version. This will cause all of the existing boards to report -1 (or 65535) as their board version until you can update it from the kernel. To set your board version to 0 run the following command in the AP console when WP if off (e.g. battery removed) $ ectool cbi set 0 0 1 2 BRANCH=none BUG=b:77551185,b:77900842 TEST=wrote to cbi from ap console and verify flash state on ap and ec console Change-Id: I03987cc89ca4c14580dcf61de23780fe5304663b Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1008832 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* yorp: Enable DP alternate modeDivya Sasidharan2018-04-101-2/+2
| | | | | | | | | | | | | | | | | | | This code enables alternate mode path for DP for both TypeC ports. BUG=b:77496487 BRANCH=None TEST=On yorp; check if the mux is set correctly for DP use cases. When PD message for hot plug is received by EC, EC (write register) ---> TCPC (GPIO) ---> SoC, and display comes up with both ports. Change-Id: Idfd0f85dc02a04adb266f2755a6d68dcb20141f8 Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1003330 Commit-Ready: Divya S Sasidharan <divya.s.sasidharan@intel.com> Tested-by: Divya S Sasidharan <divya.s.sasidharan@intel.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* yorp: Enable keyboard supportDivya Sasidharan2018-04-041-0/+8
| | | | | | | | | | | | | BUG=b:77487719 BRANCH=None TEST=make buildall -j; on yorp test keyboard Change-Id: Ieb3da871cfa6e2274a3e54274497846787edb796 Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/984385 Commit-Ready: Divya S Sasidharan <divya.s.sasidharan@intel.com> Tested-by: Divya S Sasidharan <divya.s.sasidharan@intel.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* yorp: add board versionJett Rink2018-04-021-0/+3
| | | | | | | | | | | | | Hard code value to 0 for now. BRANCH=none BUG=b:76448181 TEST=none Change-Id: Iefe91fb02a958f40a1ff63c122792a390a545290 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/984517 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* yorp: Enable Trackpad powerShamile Khan2018-03-311-0/+1
| | | | | | | | | | | | | | Enable trackpad power when chipset is in S0 state. Keep it disabled in other states. BUG=b:73137125 BRANCH=master TEST=On Octopus, kernel logs show ELAN enumerated Change-Id: Ie1fd8ab777e82d900418127b4efee29fe65d1423 Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/984405 Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* yorp: update virtual wire note for PLT_RST_LJett Rink2018-03-261-1/+2
| | | | | | | | | | | | BRANCH=none BUG=b:74123961 TEST=none Change-Id: I8d1a810a171685f98c6fe476234ec2e29e7c5854 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/978369 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Scott Collyer <scollyer@chromium.org>
* yorp: Switch on blue LED on boot-upFurquan Shaikh2018-03-241-0/+5
| | | | | | | | | | | | | | | | | This is helpful during early debugging to identify if the EC is up and running. This will be later cleaned up as part of LED support for yorp. BUG=b:74952719 BRANCH=None TEST=Verified that blue led glows up on booting up EC. Change-Id: I4670c210045c649a926e7c3f23c5d6097df69e3d Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/979270 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
* Code cleanup: Rename GPIO PCH_RCIN_L to SYS_RESET_LVijay Hiremath2018-03-241-2/+2
| | | | | | | | | | | | | | | | | Renamed GPIO PCH_RCIN_L to SYS_RESET_L so that all the Intel chipset variants have same GPIO name for doing SOC internal reset. BUG=b:72426192 BRANCH=none TEST=make buildall -j Change-Id: I931ce136743fa928dd7cf6f005c912db3b2da893 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/974241 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* yorp: Enable lid, base accel and gyro sensorDivya Sasidharan2018-03-221-0/+4
| | | | | | | | | | | | | | | | This is initial configuration changes and enable motion sensor task. BUG=b:74129963,b:74132236 BRANCH=none TEST=Verified "make buildall -j and make BOARD=yorp" Change-Id: Ia45d6434a2c034c0ec650d7b46d6f664848f9153 Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/961459 Commit-Ready: Divya S Sasidharan <divya.s.sasidharan@intel.com> Tested-by: Divya S Sasidharan <divya.s.sasidharan@intel.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* yorp: update gpio alternate function parameterJett Rink2018-03-221-9/+9
| | | | | | | | | | | | | | | The NPCX driver doesn't use anything but >= 0; make everything consistent as to not imply something is different between UART and everything else. BRANCH=none BUG=none TEST=none Change-Id: Ib98f56f7004df2405df7d2cc1847f1ed4b3ec558 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/976524 Reviewed-by: Edward Hill <ecgh@chromium.org>
* yorp: add USB-C, Power, Charging skeleton codeJett Rink2018-03-091-0/+2
| | | | | | | | | | | BRANCH=none BUG=b:73811887,b:74127309 TEST=none Change-Id: Iac2d90e63db151d37db871dc33681dc35e9127a5 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/955941 Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* yorp: add usb gpio definitionsJett Rink2018-03-091-1/+55
| | | | | | | | | | | BRANCH=none BUG=b:74127309 TEST=none Change-Id: I598da6cd2f5e1cd262d0994c2e265a74cbc8fcc1 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/952960 Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* yorp: Implement initial power sequence for chipset.Jett Rink2018-03-081-4/+42
| | | | | | | | | | | | | Also adding eSPI define. BRANCH=none BUG=b:74020444,b:74018816 TEST=none Change-Id: Id237de92ed1276213b60b61968e2fc59817e0aa7 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/949722 Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* yorp: initial add of octopus BOM-A boardJett Rink2018-02-281-0/+15
BRANCH=none BUG=b:73811887 TEST=build yorp and all other boards Change-Id: I2c29ba86f29a3d25128c00c1b55e90f6843bcdd5 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/935367 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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