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* FIXUP: fix lsm6dsm driver specific data type declarationPaul Ma2018-06-221-2/+2
| | | | | | | | | | | | | | | | | | accelgyro_lsm6dsm driver use lsm6dsm_data as its driver specific data type rather than stprivate_data. Wrong data type will lead to random corrupted runtime data. Signed-off-by: Paul Ma <magf@bitland.corp-partner.google.com> BRANCH=none BUG=b:110013316 TEST=make buildall -j Change-Id: I50e0da293921c2662e97aa6f47c83519609186b5 Reviewed-on: https://chromium-review.googlesource.com/1105797 Commit-Ready: Paul Ma <magf@bitland.corp-partner.google.com> Tested-by: Paul Ma <magf@bitland.corp-partner.google.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* yorp: Program PWM3 alternate function based on board versionFurquan Shaikh2018-06-192-1/+13
| | | | | | | | | | | | | | | | | | | | GPIO80 is used for ENTERING_RW signal on V0 whereas it is used as an alternate function for KB_BL_PWM on V1+. Configuring the alternate function in gpio.inc breaks V0 boards w.r.t. ENTERING_RW signal. This change moves the configuration of alternate function for PWM3 to update_drivers_from_board_id. BUG=b:110084012 BRANCH=None TEST=Verified that firmware_DevMode passes. Change-Id: I82bf5df685d40981b70767008dafbe76ccb20ddf Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1106289 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* yorp: Fix GPIO PIN for ENTERING_RW_V0Furquan Shaikh2018-06-191-1/+1
| | | | | | | | | | | | | | | | | | ENTERING_RW_V0 is GPIO80 on yorp V0. This change fixes the pin configuration in gpio.inc BUG=b:110084012 BRANCH=None TEST=Verified that firmware_DevMode test passes along with the other set of CLs. Change-Id: I77c80c5b6926003cc678e4a0d2a1f11bef140f92 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1106288 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
* octopus: move LED battery state functions to common codeDiana Z2018-06-151-145/+16
| | | | | | | | | | | | | | | | | | | | | | Currently on other platforms, each board creates its own LED charging and power state functions (unless they use the std LEDs). In order to reduce the amount of repeated code between the different octopus boards, the LED power states and corresponding logic have been put into a common file which all boards can use for their LED tasks. Individual boards will still need to implement the LED common functions and their tables to indicate what their LED behavior is. This is implemented for yorp's LED only currently. BRANCH=none BUG=none TEST=make buildall, loaded EC code onto yorp to ensure LEDs still flash as they did before Change-Id: I05b704363e213306717d9728111477d6d7743a92 Signed-off-by: Diana Z <dzigterman@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1101167 Reviewed-by: Jett Rink <jettrink@chromium.org>
* thermistor: move thermistor tables into common codeJett Rink2018-06-152-103/+19
| | | | | | | | | | | | | | | | | The exact same 2 lookup tables are in multiple board files. We seem to reuse the 2 thermistor circuit enough that we should single source them in a common location. BRANCH=none BUG=none TEST=yorp sensors still function properly Change-Id: Ic393c609c78c8a51c55a67b639c1fb9e6c387d8a Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1100943 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
* yorp: implement late hibernate callJagadish Krishnamoorthy2018-06-121-0/+14
| | | | | | | | | | | | | | | | | Implement board_hibernate_late function to turn off the LED's. BUG=b:110057984 BRANCH=NONE TEST=On Yorp board, enter hibernate mode through key combination "Alt H Vol Up" , observe that LED is turned off. Change-Id: Idb412cbbbb549c54b449cd4571226e284dd88e6a Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1096665 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Vijay Hiremath <vijay.p.hiremath@intel.corp-partner.google.com>
* gpio: fixed GPIO_SEL_1P8V is cleared unexpectedly during i2c unwedging.Mulin Chao2018-06-121-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | For npcx ec, board driver needs to add GPIO_SEL_1P8V flag for SDA/SCL pins in gpio.inc when i2c port is configured to support low-voltage mode (1.8V). Npcx gpio driver will set the corresponding bits in LV_GPIO_CTL register later. But if there is an i2c unwedging mechanism occurred on those 1.8V i2c port, the bits of LV_GPIO_CTL will be cleared unexpectedly after unweding is completed. And it also will make ec consumes more 0.5mA current on each pin since IO is selected to 3.3V. The root cause is the GPIO flags of SCL/SDA have been changed to zero only after i2c unweding is done. This CL which solved this issue includes: 1. Add GPIO_INPUT and GPIO_SEL_1P8V flag in ALTERNATE macro array which pins belong to 1.8V i2c port. 2. Change type of flags in structure gpio_alt_func from uint16_t to uint32_t since bit overflow. BRANCH=none BUG=b:109884927 TEST=No build errors for npcx7 series. Saving 3.3mW power consumption on yorp if this patch is applied. Change-Id: I06eadd5df36c7f69e6741f1dee13c801bac18360 Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/1089604 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* yorp: remove old commentJett Rink2018-06-121-1/+0
| | | | | | | | | | | | | | Bug is already closed BRANCH=none BUG=b:74602071 TEST=none Change-Id: Ib3d4200810a495f4c803f9ecf662a9a2a655b3aa Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1098019 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
* yorp: update gpio and functionality based on latest schematicJett Rink2018-06-073-31/+94
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Change GPIO signals at runtime based on board version - SYS_RESTET_L, ENTERING_RW, USB2_OTG_ID - Add 2nd signal for 2nd USB-A port BC1.2 outbound charging - (GPIO96) USB_A1_CHARGE_EN_L (V1) maps to EN_BRD_ID (V0) so we can just enable the USBA port 1 signal on V0 with only a small power drain. It is not worth the EC codebase churn to add support for changing the number of USB-A ports at runtime (since it is a compile time constant now) - Yorp V0 is the only board that set USB_PORT_COUNT to 1 so we can make common octopus code only have the 2 port case. - Add placeholders for LED_3_L, WFCAM_VSYNC - Updated signal name comments to match schematics - Formatting cleanup for consistency BRANCH=none BUG=b:109747036,b:74388692 TEST=verified `sysjump rw` does not brown out board when only powering with USB C1 without battery. Since GPIO_C1_EN_SNK_V0 moved, the board would lock power out if GPIOs state was not maintained properly through sysjump transition. Change-Id: Ie4c72699ab23ee6f7d2fa77a78709e5b4343e46f Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1087815 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* octopus: remove ADCs for VBUSJett Rink2018-06-073-16/+0
| | | | | | | | | | | | | | | Hardware does not support ADCs for Vbus anymore for all boards except bip. Make bip the same as other octopus boards (i.e. not using ADCs for Vbus measurements). BRANCH=none BUG=b:109747036 TEST=CL stack works with current yorp Change-Id: I96b82b70799e8b70bf5d479a1714524fc1652140 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1089199 Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* octopus: rename USB-C signal namesJett Rink2018-06-072-7/+7
| | | | | | | | | | | | | | | Simple rename of gpio based on newest schematics for yorp and phaser BRANCH=none BUG=b:109747036,b:109747361 TEST=build Change-Id: I08d9010f16e623ca41bb66363d568c4b5bd687e8 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1089040 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* battery: Move fuel gauge code to commonEdward Hill2018-06-011-1/+1
| | | | | | | | | | | | | | | | | Move fuel gauge code to common to avoid duplication in octopus and grunt baseboards. BUG=b:79704826,b:74018100 BRANCH=none TEST=make -j buildall Change-Id: I58a615c9ed7906cb19b49c2baa36aaa619838cf1 Signed-off-by: Edward Hill <ecgh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1072637 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Vijay Hiremath <vijay.p.hiremath@intel.corp-partner.google.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* yorp: enable interrupt for base accel sensorJagadish Krishnamoorthy2018-05-303-4/+19
| | | | | | | | | | | | | | | | | Configure the accel sensor gpio to interrupt. Enable CONFIG_ACCEL_INTERRUPTS and CONFIG_ACCEL_FIFO to activate FIFO mode. BUG=b:74932344 BRANCH=NONE TEST=On Yorp board, "accelinfo on 1000" should output BASE ACCEL values. Change-Id: Icecbbe604b32b6bd691558d2898896f6d1443f19 Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1073645 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* yorp: drive PPC EN_SNK from TCPC gpioJett Rink2018-05-292-2/+21
| | | | | | | | | | | | | Since the PS8751 is now driving the EN_SNK GPIO on the PPC, we cannot reset without a battery otherwise we will brown out the board. BRANCH=none BUG=b:78896495,b:78021059 TEST=verified with reworked board. Change-Id: Ibadf46de922c49f5fdd08c43991e71f852ff7600 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1067711
* yorp: add keyboard backlight controlJett Rink2018-05-232-1/+9
| | | | | | | | | | | | | | Enable PWM control of backlight in EC for yorp and phaser. Proto build of bip will not have backlight control in EC. BRANCH=none BUG=b:79422226 TEST=none (no hardware to test with) Change-Id: Ib6ed4af4de3145b112ed43b4ca1ec9f931f3875f Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1050785 Reviewed-by: Justin TerAvest <teravest@chromium.org>
* octopus: implement device modeJagadish Krishnamoorthy2018-05-221-0/+2
| | | | | | | | | | | | | | | | | | To enable device mode, set the gpio USB2_OTG_ID in the respective boards to high. Pull the gpio low to disable device mode. BUG=b:79343083 BRANCH=NONE TEST=On Yorp board, for UFP mode gpio USB2_OTG_ID should be high, for DFP mode gpio USB2_OTG_ID should be low. In OS console, lspci should list xdci. (with chromiumos/third_party/coreboot/+/1064592) Change-Id: I70f13a9705626d9bcbe989239f6826d35d8fa536 Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1058832 Reviewed-by: Jett Rink <jettrink@chromium.org>
* octopus: enable trackpad (S3+) and backlight (S0)Jett Rink2018-05-182-30/+5
| | | | | | | | | | | | | | | | Enable trackpad when entering S3, and display backlight when entering S0 and disable them on the opposite transition. Moving common code to baseboard. BRANCH=none BUG=b:79900266 TEST=bip trackpad works in S3 as wake source. backlight turns off in S0ix and S3. Change-Id: I0937771093d87c020b3c0d94a482d108c5a5c180 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1064693 Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* yorp: Add battery temperature sensorDivya Sasidharan2018-05-182-3/+23
| | | | | | | | | | | | | | | BUG=b:79940719 BRANCH=None TEST=On yorp: Test if ectool tempsinfo all lists battery sensor. Change-Id: Ib70872cc8f91d322120714a9147dbdd8e40432aa Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1060577 Commit-Ready: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: Divya S Sasidharan <divya.s.sasidharan@intel.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* yorp: Enable tablet modeDivya Sasidharan2018-05-173-0/+19
| | | | | | | | | | | | | | | | Enables tablet mode to change screen rotation with respect to portrait / landscape mode. BUG=b:78898771 BRANCH=None TEST=make buildall -j Change-Id: Ib959daee5b2dfa24b0a31e6bbf91f238d251abd0 Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1038605 Commit-Ready: Divya S Sasidharan <divya.s.sasidharan@intel.com> Tested-by: Divya S Sasidharan <divya.s.sasidharan@intel.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* yorp: renegotiate Vbus down before hibernatingJett Rink2018-05-081-21/+0
| | | | | | | | | | | | | | | | | | When we support the lowest power mode for Nuvoton in the next spin, we will shed the TCPC/PPC power rail during hibernate. Before we drop the power for the PPCs we need to ensure that Vbus is lower than the hard-coded 6.8V dead-battery mode over-voltage threshold, otherwise we will lock ourselves out of power. BRANCH=none BUG=b:79218851 TEST=verified that yorp renegotiates Vbus to 5V when entering hibernate via ec `hibernate` cmd. Change-Id: I4a98573eefb5757eea02dc48c64d5f9358b5e0b7 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1047954 Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* yorp: Configure GPIO_HIB_WAKE_HIGH for AC_PRESENTFurquan Shaikh2018-05-071-2/+4
| | | | | | | | | | | | | | | | AC_PRESENT is active high and hence GPIO_HIB_WAKE_HIGH needs to be set in order to wake the EC up from hibernate. BUG=b:79220888 BRANCH=None TEST=make -j BOARD=yorp Change-Id: I91e1c2f0b615b8272d3d1916a284d34a56959f82 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1043343 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* yorp: Enable SINK_CTRL on PPC before hibernatingFurquan Shaikh2018-05-071-1/+9
| | | | | | | | | | | | | | | | | | | | | | It was observed on yorp that connecting AC when EC is in hibernation does not always reliably wake the EC up. The reason for this seems to be that USB_C0_CHARGE_ON from ANX7447 is not asserting SINK_CTRL and PPC does not pass through ACIN and thus ACOK_OD remains low. This change ensures that SINK_CTRL is enabled on all the ports before EC goes into hibernate state. BUG=b:79173959 BRANCH=None TEST=Verified that EC wakes up from hibernate reliably with AC insert. Change-Id: I14ff2c89511993fec53462ac606b92e5d9438739 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1043076 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* yorp: Shutdown AP when doing hibernateFurquan Shaikh2018-05-041-0/+12
| | | | | | | | | | | | | | | | | | | | When hibernate is run from EC console or using key combo, AP might not actually be in shutdown state. Thus, add a call to force chipset shutdown in board_hibernate and let AP drop down to S5. BUG=b:79171681 BRANCH=None TEST=Verified that hibernate with AP in S0 does not result in EC waking back up. Change-Id: I4103c51afb42944e05ec3965b421730fac3f867a Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1041278 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
* octopus: move more implementation to baseboardJett Rink2018-05-042-173/+2
| | | | | | | | | | | | | | Move driver configuration to baseboard in preparation for phaser board BRANCH=none BUG=none TEST=yorp still works Change-Id: Ifeb434d2d4103160acd6eb9f784533d1ae0ae35a Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1042729 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* octopus: remove pwm code for LEDsJett Rink2018-05-041-1/+0
| | | | | | | | | | | | | We are using LED as straight GPIO signals so remove pwm for now BRANCH=none BUG=none TEST=none Change-Id: I48b316b6df023217a7cc1bed7a741f72d1388026 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1042728 Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* yorp: Add support for SONY batteryDivya Sasidharan2018-05-042-0/+29
| | | | | | | | | | | | | | BUG=b:78906183 BRANCH=None TEST=make buildall -j; connect SONY battery and test if recognized on battery UI icon in OS. Change-Id: I15c7a9611c10de425f3ca34f7f8f737c65e47275 Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1041159 Commit-Ready: Divya S Sasidharan <divya.s.sasidharan@intel.com> Tested-by: Wenkai Du <wenkai.du@intel.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* yorp: Control backlight based on chipset transitionsFurquan Shaikh2018-05-022-0/+13
| | | | | | | | | | | | | | | | | | This change enables/disables backlight based on the chipset state transition. BUG=b:78897667 BRANCH=None TEST=None Change-Id: I4da331cb94f7a304a76fce93b73c38016f5b0f4d Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1036798 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
* octopus: move common function to baseboardJett Rink2018-05-021-65/+0
| | | | | | | | | | | | | | Move common variables and functions to baseboard from yorp and bip BRANCH=none BUG=none TEST=builds Change-Id: Ic74bec45f4ff6c833e4ef0620380f21b2ed6a041 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1040107 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Vijay Hiremath <vijay.p.hiremath@intel.corp-partner.google.com>
* octopus: move common CONFIG defines into baseboardJett Rink2018-05-021-145/+6
| | | | | | | | | | | | | | | The `make BOARD=yorp print-configs` and bip version show no diff before and after this change. BRANCH=none BUG=none TEST=verify the print-configs output does not change. Change-Id: If2cdc39b685f529ece707b9831052daf58e91dfa Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1038898 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Vijay Hiremath <vijay.p.hiremath@intel.corp-partner.google.com>
* yorp: enable low power mode on ECJett Rink2018-05-021-0/+2
| | | | | | | | | | | | BRANCH=none BUG=b:78497503 TEST=builds. Still needs more verification for low power mode Change-Id: Idab7a1577e4d99edc29d55ad4f99a662d9419c12 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1038896 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Vijay Hiremath <vijay.p.hiremath@intel.corp-partner.google.com>
* anx7447: convert automatic OCM erase into commandJett Rink2018-05-011-1/+1
| | | | | | | | | | | | | | | We do not want to erase the OCM flash automatically so we can ensure that we fix our supply chain issues. Add a command that will erase the OCM if needed. BRANCH=none BUG=b:77658388 TEST=verified command works on yorp Change-Id: Iaf6ada3b1e223d15ae0d9624bdcc54b90cb33b64 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1035428 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* npcx: change chip variants of npcx7 series for better clarification.Mulin Chao2018-04-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In this CL, we changed chip variants npcx7m6xb to npcx7m6fb and npcx7m7w to npcx7m7wb for better clafiication since it introduced new parameter "b" for chip generation in the same family series. In new npcx7 series naming rule, it follows: Format: NPCX7(M)(N)(G/K/F)(B/C) param M: 8: 128-pins package, 9: 144-pins package param N: 5: 128KB RAM Size, 6: 256KB RAM Size, 7: 384KB RAM Size param G/K/F/W: Google EC depends on specific features. param B/C: Chip generation in npcx7. (Generation A is ignored. It follows nameing rule in npcx5.) The all chip variants of npcx7 used in boards are also listed below: npcx7m6g - for npcx7 ec without internal flash on npcx_evb. npcx7m6f - for npcx7 ec with internal flash. npcx7m6fb - for npcx7 ec with internal flash, enhanced features. npcx7m7wb - for npcx7 ec with internal flash, enhanced features + WOV. BRANCH=none BUG=none TEST=No build errors for npcx7 series. Change-Id: I896ee33209efa5d7157c90515005db5f36318c76 Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/1025471 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* octopus: move common usb/battery code into baseboardJett Rink2018-04-264-761/+17
| | | | | | | | | | | | | Also implement a few remaining usb function for bip BRANCH=none BUG=b:75972988,b:76218141,b:74132235,b:78344554 TEST=verified yorp still functions Change-Id: I201408b5db689ac4a5bcab0011bc38698271b851 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1024279 Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* yorp: lower i2c speeds to 100kHzJett Rink2018-04-261-2/+2
| | | | | | | | | | | | | | | | | | We need to tune the i2c parameters for the nuvoton chip on our yorp board to be able to operate at 400kHz. Currently we do not need the extra speed or bandwidth, so we are reverting to a lower speed where the default timing parameters work well. BRANCH=none BUG=b:78554726,b:78225299 TEST=HDMI over TypeC works on yorp This reverts commit 2e7e6665b1e712a950eef8ae3d3f64ae0f1d2ec1. Change-Id: Ic4ba1d5ef25661bd6c7f9490450af65b4e1393ad Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1028752 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* board/yorp: fix PMIC_EN gpioAaron Durbin2018-04-251-1/+1
| | | | | | | | | | | | | | | | | | | | | | Apparently the symbol in the yorp schematic is incorrect for our part. The PMIC_EN signal on ball H6 is actually GPIO72 -- not GPIOD7. Adjust the gpio used for PMIC_EN. Note: GPIO72 needs to be put in gpio mode since it defaults to PWRGD functionality. However, gpio_pre_init() in chip/npcx/gpio.c enables gpio functionality by default. If that changes, the board options will need to change as well. BUG=b:78352179 TEST=Built. Booted. PMIC_EN goes up and down as expected. BRANCH=none Change-Id: I955f9a24e0fbecb0cda1380c237fa44c9a575e45 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1026375 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
* board/yorp: set the correct chip variantAaron Durbin2018-04-251-1/+1
| | | | | | | | | | | | | | | | | The yorp build is using part NPCX796FB0BX which evidently maps to npcx7m6xb. Therefore, set the correct variant to reflect reality. BUG=b:78352179 TEST=Built. Booted. BRANCH=none Change-Id: I3835b4664429c360ea946aad0a7bf3dc32f6eea1 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1024608 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
* yorp: Enable temperature sensorsDivya Sasidharan2018-04-243-3/+105
| | | | | | | | | | | | | BUG=b:77944804 BRANCH=None TEST=On yorp; test adc values, verify they are valid. Change-Id: I64191f33c594d8869391bab813902f59a63d2ea1 Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1018118 Commit-Ready: Divya Sasidharan <divya.s.sasidharan@intel.corp-partner.google.com> Tested-by: Divya Sasidharan <divya.s.sasidharan@intel.corp-partner.google.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* yorp: Fix force mode base accel configDivya Sasidharan2018-04-202-5/+7
| | | | | | | | | | | | | | | | Accel data read was (0, 0) without this change. BUG=b:74602071 BRANCH=None TEST=On yorp; on EC console test accelinfo on -> gives accel data Change-Id: I08073cccb2108b5d2189be5aa27a77adfae7677a Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1015974 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Divya S Sasidharan <divya.s.sasidharan@intel.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* APL/GLK: Move chipset shutdown to chipset taskFurquan Shaikh2018-04-191-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | In order to ensure that all chipset init/shutdown operations happen within the context of chipset task for APL/GLK: 1. Update chipset_force_shutdown to only set a flag force_shutdown to indicate that chipset shutdown is requested and wake the chipset task. 2. Make chipset task (within the power state machine) call internal_chipset_shutdown. 3. Make internal_chipset_shutdown reset force_shutdown flag and make a callback to weak function chipset_do_shutdown to trigger chipset shutdown. BUG=b:78259506 BRANCH=None TEST=Verified that "apshutdown" on EC console results in chipset shutdown action being taken within chipset task. Change-Id: If13b65ae47e3dce2e466320cc14c68239563f6ed Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1018737 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* APL/GLK boards: Use chipset_pre_init_callbackFurquan Shaikh2018-04-191-4/+2
| | | | | | | | | | | | | | | | This change updates all APL/GLK boards to use chipset_pre_init_callback instead of hook. BUG=b:78259506 BRANCH=None TEST=Verified that yorp still boots. Change-Id: I71ab0f1111e89a254db83fc58abfdfe8eacd3575 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1018734 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* system: update board version to return an error if encounteredJett Rink2018-04-191-2/+1
| | | | | | | | | | | | | | | | | | | | Now that board version can come from CBI, we can have a real error reading it. We should pass that error to the console or to the AP on the host command and let the AP firmware (or user) decided how to handle that error case Also update the CONFIG_BOARD_VERSION to be derived instead of needed in most cases. BRANCH=none BUG=b:77972120 TEST=Error reported on EC console and AP console when CBI is invalid on yorp Change-Id: Ib8d80f610ea226265a61e68b61965150cdc9bb04 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1015776 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* yorp: do not wait for 5V rail to go downJett Rink2018-04-171-2/+5
| | | | | | | | | | | | | | After using joint 5V rail code (CONFIG_POWER_PP5000_CONTROL) we cannot wait for the 5V rail to go down because another task may be using it. BRANCH=none BUG=b:78188213 TEST=apshutdown on yorp no longer watchdog resets Change-Id: Ibc7e3eb2f7b3271fccd6ef0d92cce156c20bd688 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1015845 Reviewed-by: Justin TerAvest <teravest@chromium.org>
* yorp: increase TCPC i2c bus speedJett Rink2018-04-171-3/+2
| | | | | | | | | | | | BRANCH=none BUG=b:74387239 TEST=i2cscan and USB-C ports still connect on yorp Change-Id: Ic76549d6f81536cf02e1aa858a95e67eb528bccd Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1014704 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
* yorp: Keep 5V rail high on jump to RWJustin TerAvest2018-04-172-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | The BQ24392 driver controls power on the PP5000_A rail so that BC1.2 detection can be performed when the AP is off. However, that rail is also controlled by the chipset task, so CONFIG_POWER_PP5000_CONTROL needs to be defined to keep 5V rail up when necessary. Calls to power_5v_enable() must only be done when the build has a chipset task (otherwise, that function is not defined). BRANCH=none BUG=b:77874283 TEST=Booted Yorp with software sync enabled Signed-off-by: Justin TerAvest <teravest@chromium.org> Change-Id: Ib75655944aa05e381da922da8e916dc5d4dd9f85 Reviewed-on: https://chromium-review.googlesource.com/1014397 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Divya S Sasidharan <divya.s.sasidharan@intel.com> Reviewed-by: Divya S Sasidharan <divya.s.sasidharan@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* yorp: use cbi for board versionJett Rink2018-04-133-87/+3
| | | | | | | | | | | | | | | | | | | | | Replace ADC-based board version with CBI/EEPROM board version. This will cause all of the existing boards to report -1 (or 65535) as their board version until you can update it from the kernel. To set your board version to 0 run the following command in the AP console when WP if off (e.g. battery removed) $ ectool cbi set 0 0 1 2 BRANCH=none BUG=b:77551185,b:77900842 TEST=wrote to cbi from ap console and verify flash state on ap and ec console Change-Id: I03987cc89ca4c14580dcf61de23780fe5304663b Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1008832 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* yorp: Add support for Sanyo batteryScott Collyer2018-04-131-0/+29
| | | | | | | | | | | | | | | | | | Currently we only support the Acer LG and Panasonic battery. There is a 3rd Acer battery type that Quanta could be providing us with for Yorp proto boards. This CL adds support for the Sanyo battery. BUG=b:74132235 BRANCH=none TEST=verifed that when connected to Sanyo battery that the battery is reported as present. Change-Id: I1810da59866795e93340163216412441be098795 Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/1011557 Commit-Ready: Jett Rink <jettrink@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* anx7447: Add functions to the anx7447 driver to check/erase OCM flashScott Collyer2018-04-131-0/+1
| | | | | | | | | | | | | | | | | | | | | This CL adds support to check if the OCM flash is erased and if not, will erase it at initialization time. These changes are encapsulated in a new config option CONFIG_USB_PD_TCPM_ANX7447_OCM_ERASE and this option is enabled for Yorp boards. BUG=b:77658388 BRANCH=NONE TEST=make -j buildall. Tested on a board that hadn't yet been erased. Verifed the message "anx7447: OCM flash checked and successfully erased" was in the EC log, but did not show up on subsequent reboots. Change-Id: I660e76a9498d3dc1ba821a04317b324f716c5089 Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/988414 Commit-Ready: Jett Rink <jettrink@chromium.org> Tested-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* yorp: Configure CONFIG_EXTPOWER_DEBOUNCE_MSDivya Sasidharan2018-04-111-1/+6
| | | | | | | | | | | | | | | | | | | | Without this configuration defined the board assumes battery only mode for G3->S5 boot up power sequence and thereby waits for power button press. BUG=b:76230069;b:75974377 BRANCH=None TEST=On yorp, with battery and external power connected reboot on EC console boot the SoC to S0. Verify on both ports. Change-Id: I837b7f99bd3c238ce74e394c773169d703ad9392 Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1008247 Commit-Ready: Aaron Durbin <adurbin@chromium.org> Tested-by: Divya S Sasidharan <divya.s.sasidharan@intel.com> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* yorp: Disable config for DRP_AUTO_TOGGLEDivya Sasidharan2018-04-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | | Since there are known issues with ANX7447 driver to work reliably in low power mode, disable DRP_AUTO_TOGGLE option since TCPC_LOW_POWER mode config and this one should be disabled together. BUG=b:77544959 BRANCH=None TEST=On yorp; on port 0 and 1 test without and with battery boots up. Please note with battery we may still need to press power button to get the SoC to boot up to S0 b:76230069. Detaching the Type-C charger with battery connected also shuts down the system which is a known failure b:77606986. Change-Id: I1b744cd9aa063328845f9a1cc7e36d291dfec9f5 Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1007629 Commit-Ready: Divya S Sasidharan <divya.s.sasidharan@intel.com> Tested-by: Divya S Sasidharan <divya.s.sasidharan@intel.com> Reviewed-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* yorp: Enable DP alternate modeDivya Sasidharan2018-04-102-6/+26
| | | | | | | | | | | | | | | | | | | This code enables alternate mode path for DP for both TypeC ports. BUG=b:77496487 BRANCH=None TEST=On yorp; check if the mux is set correctly for DP use cases. When PD message for hot plug is received by EC, EC (write register) ---> TCPC (GPIO) ---> SoC, and display comes up with both ports. Change-Id: Idfd0f85dc02a04adb266f2755a6d68dcb20141f8 Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1003330 Commit-Ready: Divya S Sasidharan <divya.s.sasidharan@intel.com> Tested-by: Divya S Sasidharan <divya.s.sasidharan@intel.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
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