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* tglrvp: Add back the ALL_SYS_PWRGD signalVijay Hiremath2019-11-082-3/+3
| | | | | | | | | | | | | | Adding back the ALL_SYS_PWRGD signal which was removed as part of the CL:1881753. BUG=b:143373337 BRANCH=none TEST=powerinfo shows all signals Change-Id: I8ddfb0ed61963839cd657840b9a5b80cebb5da86 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1900125 Reviewed-by: Keith Short <keithshort@chromium.org>
* Kodama: SMP battery cannot be charged in over discharge statexiong.huang2019-11-081-3/+27
| | | | | | | | | | | | | | | | | | | | SMP battery uses HW pre-charge circuit and pre-charge current is limited to ~50mA. Once the charge current is lower than IEOC level within CHG_TEDG_EOC, and TE is enabled, the charging power path will be turned off. Charger vendor advice that disable EOC and TE when battery stays over discharge state, otherwise enable EOC and TE. BUG=b:142630134 TEST=Verified on both SMP battery and Celxpert battery in over discharge state, all passed. BRANCH=kukui Change-Id: I7d6907d54ab555587a489333350de6e9aeffe60e Signed-off-by: Xiong Huang <xiong.huang@bitland.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1893901 Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* volteer: Configure ADC channelsKeith Short2019-11-081-3/+0
| | | | | | | | | | | | | | | | | | Configure ADC channels for temperature sensors. enum adc_channels is required by the isl9241 charger support. Addtional changes are still needed to support EC thermal capabilties. BUG=b:143768086 BRANCH=none TEST=make buildall Change-Id: Ia34464e56185e1693dd4c8aed378d7703c290742 Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1896640 Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Abe Levkoy <alevkoy@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* usbc: fix vbus discharge path for GPIOJett Rink2019-11-071-0/+2
| | | | | | | | | | | | | Code on Tot assumes that port count was the port to discharge instead of port parameter BRANCH=none BUG=none TEST=verified with unit test (in this CL) Change-Id: I17658a0c555f9cea56fa4ec1652e0faf62e3d6cc Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1896125
* servo_micro: add usart cmd to hold pins lowJett Rink2019-11-073-4/+105
| | | | | | | | | | | | | | | | | | | | | To enabled UART (UUT) programming mode for some ECs, we need to drive the EC_TX_SERVO_RX line low while the EC is rebooting. Add a console command that is controllable by dut-control that will drive the UART pins low while the UART is disabled, until the command to re-enable the UART is sent on the console. Also, remove unnecessary alternate mode initialization for USART4 (UART3). BRANCH=firmware-servo-11011.B BUG=b:143163043 TEST=flashed phaser with reworked servo_micro Change-Id: I1af1af7b48bf446936211740e16008a80ab2a39f Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1884190 Reviewed-by: Keith Short <keithshort@chromium.org>
* Drop LTO workaround from sweetberryStefan Reinauer2019-11-071-5/+0
| | | | | | | | | | | | | | | | Because it breaks external builds such as coverity builds. The issue needs to be fixed differently. BUG=b:132204142 TEST=flash on sweetberry and see usb endpoints work BRANCH=none Change-Id: I2ee1789e12dd5240fac4bf97a2638efa85446df6 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1851105 Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Commit-Queue: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Auto-Submit: Stefan Reinauer <reinauer@chromium.org>
* Trembyle: Add more IOEX GPIO definitionsEdward Hill2019-11-071-2/+10
| | | | | | | | | | | | BUG=none BRANCH=none TEST=build Change-Id: I64c5b46367774163f532bbcb9097657e2b83ad9f Signed-off-by: Edward Hill <ecgh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1904153 Reviewed-by: Denis Brockus <dbrockus@chromium.org> Commit-Queue: Denis Brockus <dbrockus@chromium.org>
* dratini/dragonair: add new SKUDevin Lu2019-11-071-3/+7
| | | | | | | | | | | | | | add unprovisioned SKUID to support kblight and convertible for pre-flash cbi. add SKU ID: 23 (Convertible, TS, Stylus) BUG=b:142987639, b:143994766 BRANCH=none TEST=make buildall -j. Change-Id: Ie8d4b611d8073ff993a94699d832ada6830a2771 Signed-off-by: Devin Lu <Devin.Lu@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1902892 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
* Kindred: support factory keyboard test.ben.chen2@quanta.corp-partner.google.com2019-11-072-1/+23
| | | | | | | | | | | | | | | | | | | | | | connector-to-GPIO map: {-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6}, {0, 7}, {-1, -1}, {-1, -1}, {1, 4}, {1, 3}, {-1, -1}, {1, 6}, {1, 7}, {3, 1}, {2, 0}, {1, 5}, {2, 6}, {2, 7}, {2, 1}, {2, 4}, {2, 5}, {1, 2}, {2, 3},{2, 2}, {3, 0}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, {-1, -1}, BUG=b:143927624 BRANCH=master TEST=`ectool kbfactorytest` PASS. Change-Id: I67b8ebd1edb238a265bd6f9e5e98100b5635a2d6 Signed-off-by: Ben Chen <ben.chen2@quanta.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1898256 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Commit-Queue: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org>
* puff: Complete GPIO list for EC.Andrew McRae2019-11-073-44/+148
| | | | | | | | | | | | | | | | | Fill out the GPIO entries for puff. Some dependencies on the hatch power sequencing still exist, and will need to be modified for the puff power handling. BRANCH=none BUG=b:143189339 TEST=Build image, buildall, tests Change-Id: I60074298be3d75e447c32ee3448f67149ec1bf81 Signed-off-by: Andrew McRae <amcrae@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1898261 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Andrew McRae <amcrae@chromium.org> Commit-Queue: Andrew McRae <amcrae@chromium.org>
* puff: Add fan configuration to EC.Andrew McRae2019-11-072-10/+11
| | | | | | | | | | | | | | | Add fan configuration to puff. BRANCH=none BUG=b:143327224 TEST=Build puff, tests, buildall. Change-Id: Ib968dafa297c7d17ea0d90c0b67869f5aca5e210 Signed-off-by: Andrew McRae <amcrae@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1899653 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Andrew McRae <amcrae@chromium.org> Commit-Queue: Andrew McRae <amcrae@chromium.org>
* nocturne_fp/hatch_fp: Document alternate namesTom Hughes2019-11-062-2/+17
| | | | | | | | | | | | | | | There are many variations of "board" names for the FPMCU, but they all refer to one of two hardware configurations. BRANCH=none BUG=none TEST=make buildall -j Change-Id: I5c57fab1976f2aea395d8319c4f9c52f8134129a Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1894454 Reviewed-by: Yicheng Li <yichengli@chromium.org> Reviewed-by: Craig Hesling <hesling@chromium.org>
* servo_v4: Use the correct voltage threshold on the flipped CC directionWai-Hong Tam2019-11-061-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the DTS mode, servo pulls up CC lines with different Rp values. When detecting DUT Rd value, servo senses the CC voltage values, and checks it using some table of voltage thresholds. The tables assume CC1 is the primary CC and CC2 is the alternative CC. When servo emulates the flipped CC scenario, should use the correct colume to check the voltage thresholds. BRANCH=servo BUG=b:136014621, b:140876537 TEST=Configed servo to emulate the flipped scenario in dts mode: > cc srcdts cc2 Verified it detect the correct Rd values in DUT (CC0 and CC1 are 2, i.e. TYPEC_CC_VOLT_RD): > tcpc 1 state Port C1, Ena - CC:1, CC0:2, CC1:2 Alert: 0x00 Mask: 0x007d Power Status: 0x48 Mask: 0x00 Without this patch, it detected wrong Rd values in DUT (CC0 is 2, i.e. TYPEC_CC_VOLT_RD, but CC1 is 0, i.e. TYPEC_CC_VOLT_OPEN): > tcpc 1 state Port C1, Ena - CC:1, CC0:2, CC1:0 Alert: 0x00 Mask: 0x007d Power Status: 0x48 Mask: 0x00 Change-Id: Iaf089356230f24f871636956780cb5652fec5c42 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1876800 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* dratini: enable keyboard factory scanningDevin Lu2019-11-062-0/+24
| | | | | | | | | | | | | | | | Clone from CL:1309572 This patch add for factory keyboard connector test. BUG=none BRANCH=none TEST=Short keyboard pins and make sure "ectool kbfactorytest" works. Change-Id: I06deb1539845bc3490c69943579aa4b6bbc1d4ab Signed-off-by: Devin Lu <Devin.Lu@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1898258 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* dratini: remove unused ALS sensor idDevin Lu2019-11-061-3/+1
| | | | | | | | | | | BUG=none BRANCH=none TEST=make buildall -j. Change-Id: I4cf3d353afaaf4d422421b1a35c137f74259f962 Signed-off-by: Devin Lu <Devin.Lu@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1898248 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
* hatch_fp/nocturne_fp: Disable CONFIG_SYSTEM_UNLOCKED by defaultTom Hughes2019-11-062-6/+2
| | | | | | | | | | | | | | | | The release branch disables CONFIG_SYSTEM_UNLOCKED, but to prevent confusion (and potential mistakes), we will just always disable CONFIG_SYSTEM_UNLOCKED since the write protection scheme for fingerprint is final. BRANCH=none BUG=b:130249462,b:73337313 TEST=make buildall -j Change-Id: I072a5e037d80fbde39a5b695da7b2bd6de64e04c Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1895605 Reviewed-by: Yicheng Li <yichengli@chromium.org>
* Aleena: support factory keyboard test.David Huang2019-11-052-0/+27
| | | | | | | | | | | | | | | | | | | | | | connector-to-GPIO map: {-1, -1}, {0, 5}, {1, 1}, {1, 0}, {0, 6}, {0, 7}, {-1, -1}, {-1, -1}, {1, 4}, {1, 3}, {-1, -1}, {1, 6}, {1, 7}, {3, 1}, {2, 0}, {1, 5}, {2, 6}, {2, 7}, {2, 1}, {2, 4}, {2, 5}, {1, 2}, {2, 3},{2, 2}, {3, 0}, {-1, -1}, {0, 4}, {-1, -1}, {8, 2}, {-1, -1}, {-1, -1}, BUG=b:143848117 BRANCH=master TEST="ectool kbfactorytest" Pass. Change-Id: I087c4f11338e58d20ad82ce94c4c64380945c56f Signed-off-by: David Huang <David.Huang@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1893909 Reviewed-by: Edward Hill <ecgh@chromium.org> Commit-Queue: David Huang <david.huang@quanta.corp-partner.google.com> Tested-by: David Huang <david.huang@quanta.corp-partner.google.com>
* Kodama: battery discharge power to system when battery charged to 4.1v at 45 ↵xiong.huang2019-11-051-0/+10
| | | | | | | | | | | | | | | | | | | deg C After battery charged to 4.1V at 45 deg C, the desired voltage of the smart battery is still 4.4V, and battery will discharge power to system. When smart battery temperature is more than 45 deg C, the max charging voltage for battery is set as 4.1V. BUG=b:142669003 BRANCH=kukui TEST=Verified on four DUTs in 45 deg C and passed. Change-Id: I2c2b0d43ed29b33beb37ba4d75ecb653f156c9a7 Signed-off-by: Xiong Huang <xiong.huang@bitland.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1880774 Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* treeya: fix rotation matrix of kx022 lid sensorLu Zhang2019-11-051-1/+0
| | | | | | | | | | | | | | | | The layout has been changed. Need to follow the HW changes. BUG=b:143848116 BRANCH=none TEST=Using ec console 'accelinfo on' verified lid angle now goes from 0 to 360 and swtiches to tablet mode after crossing 180 threshold. Signed-off-by: Lu Zhang <lu.zhang@bitland.corp-partner.google.com> Change-Id: I3ad16a44b419bcce38f0cdbf8d74e6b4876c7250 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1886590 Tested-by: Peichao Li <peichao.wang@bitland.corp-partner.google.com> Reviewed-by: Peichao Li <peichao.wang@bitland.corp-partner.google.com> Reviewed-by: Edward Hill <ecgh@chromium.org>
* Kodama: Modify celxpert battery parameterxiong.huang2019-11-041-2/+2
| | | | | | | | | | | | | | Base on celxpert battery SPEC, pre-charge current is 404mA and over discharge voltage is 2.8V. BUG=b:138826367 TEST=Base on celxpert battery SPEC. BRANCH=kukui Change-Id: I7714e2392f9de3190964f25980871ab78c2ad309 Signed-off-by: Xiong Huang <xiong.huang@bitland.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1893900 Reviewed-by: Ting Shen <phoenixshen@chromium.org>
* kukui_scp: Enable CONFIG_HOSTCMD_ALIGNEDYilun Lin2019-11-041-0/+2
| | | | | | | | | | | | | | | To have more efficient HC structure. The usage of SRAM only increase by 21 bytes. TEST=make BOARD=kukui_scp BUG=b:136979732 BRANCH=kukui Change-Id: I86dd582faceff9651320e566d916e68e47f0cb83 Signed-off-by: Yilun Lin <yllin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1893902 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Commit-Queue: Nicolas Boichat <drinkcat@chromium.org>
* puff: populate ADCs and temperature sensorsPeter Marheine2019-11-042-20/+90
| | | | | | | | | | | | | | Several analog channels are needed for power sequencing, and may as well fill them all in while we're here. BUG=b:143188569 TEST=image builds and links BRANCH=None Change-Id: I99c2def362b11bef0748adfe11cc7356bb1591c6 Signed-off-by: Peter Marheine <pmarheine@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1893016 Reviewed-by: Andrew McRae <amcrae@chromium.org>
* ec-fans: Make fans configuration const by default.Andrew McRae2019-11-0214-12/+14
| | | | | | | | | | | | | | | | It was pointed out to me that the fans config list was non-const, but there is only 2 boards that require non-const configuration, so by default make it const, but allow an override. BRANCH=none BUG=None TEST=EC compiles, make tests, buildall Change-Id: I3ef8c72f6774e1a76584c47d89287f446199e0f2 Signed-off-by: Andrew McRae <amcrae@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1893025 Reviewed-by: Andrew McRae <amcrae@chromium.org> Tested-by: Andrew McRae <amcrae@chromium.org> Commit-Queue: Andrew McRae <amcrae@chromium.org>
* servo_v4: The polarity is based on the flags in SRC DTS modeWai-Hong Tam2019-11-021-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the port in SRC DTS mode, it should not perform the polarity detection. The polarity is predetermined, as a board-specific setting. In the servo case, the polarity is based on the flags. This CL changes the protocol layer to check the port in SRC DTS mode and call the board-specific function board_get_src_dts_polarity() for the polarity. BRANCH=servo BUG=b:140876537 TEST=Configed servo as srcdts and unflipped direction: > cc srcdts cc2 Verified the power negotiation good and detected the correct polarity: > pd 1 state Port C1 CC2, Ena - Role: SRC-UFP State: SRC_READY, Flags: 0x415e Without this patch, it detected the wrong polarity and the power negotiation failed: > pd 1 state Port C1 CC1, Ena - Role: SRC-DFP State: SRC_DISCOVERY, Flags: 0x10608 Change-Id: I32c5dfffeaeb20a21db1417f3a1c98566b7f5e38 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1891255 Reviewed-by: Jett Rink <jettrink@chromium.org> Commit-Queue: Sean Abraham <seanabraham@chromium.org>
* Rename CONFIG_USB_PD_PORT_COUNT as CONFIG_USB_PD_PORT_MAX_COUNTKarthikeyan Ramasubramanian2019-11-01120-257/+268
| | | | | | | | | | | | | | | | | Certain SKUs of certain boards have lesser number of USB PD ports than defined by CONFIG_USB_PD_PORT_COUNT. Hence rename CONFIG_USB_PD_PORT_COUNT as CONFIG_USB_PD_PORT_MAX_COUNT. BUG=b:140816510, b:143196487 BRANCH=octopus TEST=make -j buildall; Boot to ChromeOS Change-Id: I7c33b27150730a1a3b5813b7b4a72fd24ab73c6a Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1879337 Tested-by: Karthikeyan Ramasubramanian <kramasub@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Commit-Queue: Jett Rink <jettrink@chromium.org>
* kindred: Modify EC fan control tableben.chen2@quanta.corp-partner.google.com2019-11-011-7/+7
| | | | | | | | | | | | | | | | | | | | | Modify EC fan control table by Thermal request. BUG=b:136567378 BRANCH=Master TEST=Manual Verify fan behavior by thermal team. Remove DPTF and check fan speed with temperature. When temperature over 25 degree, the fan start working. When temperature over 55 degree, the fan full run. And check system shutdown when temperature over 75 degree. Change-Id: I1f91eea6e98e65bd93f62c33a52ff3d91558abc1 Signed-off-by: Ben Chen <ben.chen2@quanta.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1873862 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Commit-Queue: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* juniper: add new battery for next juniper buildTing Shen2019-11-012-0/+28
| | | | | | | | | | | | | | BUG=b:143334368 TEST=1) See "[0.064610 found batt:PANASONIC]" on EC console 2) battery readings looks reasonable BRANCH=master Change-Id: I5a7091ea7db6ff3f524ac5bd99bc6a7d3bdcd181 Signed-off-by: Ting Shen <phoenixshen@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1880771 Reviewed-by: Eric Yilun Lin <yllin@chromium.org> Commit-Queue: Ting Shen <phoenixshen@chromium.org> Tested-by: Ting Shen <phoenixshen@chromium.org>
* puff: Scrub config and generate hardware structuresAndrew McRae2019-11-013-26/+156
| | | | | | | | | | | | | | | | | | Verify all CONFIG items in board/puff/board.h. Generate the necessary hardware reference structures in board.c Generate the minimum GPIO references in order to build cleanly. v2: Remove some of the fan and temp sensors config. BUG=b:143564865 TEST=Compile and link EC image. Change-Id: Ibc073718ad1c85705ab460d96202799f8c4fea06 Signed-off-by: Andrew McRae <amcrae@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1893013 Reviewed-by: Andrew McRae <amcrae@chromium.org> Commit-Queue: Andrew McRae <amcrae@chromium.org> Tested-by: Andrew McRae <amcrae@chromium.org>
* atlas: initialize max charge currentCaveh Jalali2019-11-011-5/+17
| | | | | | | | | | | | | | | | | | | | | | | | the isl923x is strapped to initialize the charge current to 3A. however, its default max charge current limit is 3.072. when the charge current exceeds the current limit, the charger asserts PROCHOT which means the AP gets throttled to 400MHz until the charge_state machine updates the current limit. on an unlocked system, we don't change the charge limit from its default, so we never apply the 5% derating needed to avoid the isl923x from over-currenting the charger. the solution is to over-ride the 3A strapping of the isl923x by appling a 5% derated current request early when we boot up. BUG=b:141533503 BRANCH=none TEST=atlas no longer boots into PROCHOT on 5v3a charger Change-Id: Idba55edf7b1c0eec36b6583aa0b276c3cb1f0c89 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1889312 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* volteer: Add manual power sequencingKeith Short2019-11-014-1/+220
| | | | | | | | | | | | | | | As backup if board driven power sequencing doesn't work, implement EC controlled power sequencing on Volteer. BUG=b:140556273 BRANCH=none TEST=make buildall TEST=make BOARD=volteer VOLTEER_POWER_SEQUENCE=y Change-Id: I62e30e5f153085e2e6c26005a77e2e1abe981b0a Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1881754 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* tigerlake/icelake: add support for SYS_PWROKKeith Short2019-11-013-2/+21
| | | | | | | | | | | | | | | | | Add code to pass through PG_EC_ALL_SYS_PWRGD from the platform to the PCH signal PCH_SYS_PWROK. These signals correspond to the Intel signal names ALL_SYS_PWRGD and PCH_SYS_PWROK, respectively. BUG=b:143373337 BRANCH=none TEST=make buildall -j Change-Id: Iff86508450a5bca8c97fb855fa1a3a586edd99ff Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1881753 Commit-Queue: Sean Abraham <seanabraham@chromium.org>
* atlas: fix charger selection messagesCaveh Jalali2019-11-011-2/+2
| | | | | | | | | | | | | | | this corrects the printed text and switches from CPRINTF to CPRINTS for time stamping. BRANCH=none BUG=none TEST=buildall passes Change-Id: I4647ef4348a44d3eb433afa96ad04f2483899bc0 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1886034 Commit-Queue: Sean Abraham <seanabraham@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* tglrvp: Correct GPIO alternate function parameterVijay Hiremath2019-11-011-11/+11
| | | | | | | | | | | | | | | | Modified the gpio.inc file to reflect the new changes done for the alternate function parameter. BUG=b:139427854 BRANCH=none TEST=make buildall -j Change-Id: I3eed1b825f390581975d44734b62b7a73a2acb98 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1880975 Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* cometlake: cleanup power signal namesKeith Short2019-10-311-1/+1
| | | | | | | | | | | | | | | Add X86 prefix to the Comet Lake signals names for consistency with other Intel APs. BUG=none BRANCH=none TEST=make buildall Change-Id: I70b2a261fd6fbc0e6de70e5d4cf3a90b35078d4e Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1888596 Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
* drallion_ish: Remove CONFIG_GMR_TABLET_MODE_CUSTOM from drallion ishMathew King2019-10-312-6/+0
| | | | | | | | | | | | | | | | GMR_TABLET_MODE_CUSTOM is needed on arcada_ish due to a hall sensor which is too sensitive. Drallion should not have the same problem. BUG=b:140311300 TEST='emerge-drallion chromeos-ish' ec log shows tablet mode events BRANCH=none Change-Id: Idde16dafb52c3da51b111031ed5144f5c428d62e Signed-off-by: Mathew King <mathewk@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1893185 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
* cr50: Move 30 ms ec_rst delay to after falling edgeMathew King2019-10-311-15/+9
| | | | | | | | | | | | | | | Platfoms with closed EC require at least 30 ms to put the EC in reset. In order to support flashrom over CCD move this 30 ms delay from before the deassertion of EC reset to after assertion. BUG=b:142100741 TEST=Run flashrom over CCD without failures BRANCH=cr50 Change-Id: Ia8bb207a4407733f3cf77c52ac9063cc7bec3f94 Signed-off-by: Mathew King <mathewk@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1881752 Reviewed-by: Keith Short <keithshort@chromium.org>
* tcpm/fusb302: implement low power modeTing Shen2019-10-311-0/+1
| | | | | | | | | | | | | | | | | Implement tcpc_low_power_mode to reduce power consumption in G3. BUG=b:142760774 TEST=measure power consumption on jacuzzi. verify that power consumption is reduced by 3~4mW see b:142760774 comment 3 for more detail. BRANCH=master Change-Id: I04436d3baaa97b7c049ae3f3d9a9510e5a2024d9 Signed-off-by: Ting Shen <phoenixshen@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1880773 Reviewed-by: Eric Yilun Lin <yllin@chromium.org> Commit-Queue: Ting Shen <phoenixshen@chromium.org> Tested-by: Ting Shen <phoenixshen@chromium.org>
* usb_pd: use enum tcpc_rp_value instead of intCaveh Jalali2019-10-3116-16/+16
| | | | | | | | | | | | | | | this changes the declaration and definitions of typec_set_source_current_limit() to take an enum tcpc_rp_value instead of int. BRANCH=none BUG=none TEST=buildall passes Change-Id: If633641a581eeb6085b94bc727e23fb57f7cd435 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1889117 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* hatch_fp: Configure unused GPIO pins.Ravi Chandra Sadineni2019-10-311-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | By default, STM32F4 pins are configured as inputs, except some JTAG pins which can impact the power consumption of the device in different power modes because pins are very sensitive to external noise in input mode I/O. To avoid extra I/O current, all pins should be configured as analog input (AIN); in this mode the Schmitt trigger input is disabled, providing zero consumption for each I/O pin. For more info please look at "USING STM32F4 MCU POWER MODES WITH BEST DYNAMIC EFFICIENCY"("AN4365") section 1.2.6 and STM32F412 reference manual section 7.3.12. BUG=b:130561737 BRANCH=None TEST=Flash bloonchipper and measure power before and after. fpenroll and fpmatch works fine. Change-Id: I85d76589be22b892c81680763cfb263746004a80 Signed-off-by: Ravi Chandra Sadineni <ravisadineni@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1883127 Reviewed-by: Craig Hesling <hesling@chromium.org> Reviewed-by: Tom Hughes <tomhughes@chromium.org>
* eSPI: Configure SLP_S3, SLP_S4 separatelyAbe Levkoy2019-10-3022-33/+53
| | | | | | | | | | | | | | | | | | Split the configuration option CONFIG_HOSTCMD_ESPI_VW_SLP_SIGNALS into separate options controlling SLP_S3 and SLP_S4. Allow volteer to configure SLP_S3 as a GPIO and SLP_S4 as an eSPI virtual wire. Cause a build error if virtual wires are configured, but eSPI is not. BUG=b:139553375,b:143288478 TEST=make buildall TEST=Build volteer with CONFIG_HOSTCMD_ESPI_VW_S4 defined but CONFIG_HOSTCMD_ESPI undefined; observe build error BRANCH=none Change-Id: I8c6737e2ccb1a77a882e5fa65c6eddb342209b61 Signed-off-by: Abe Levkoy <alevkoy@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1881758 Reviewed-by: Keith Short <keithshort@chromium.org>
* Remove GPIOs for eSPI VW sleep signalsAbe Levkoy2019-10-302-11/+0
| | | | | | | | | | | | | | | | | | Remove non-interrupt GPIO configurations for SLP_S3_L and SLP_S4_L for dragonegg and tglrvpu_ite. The GPIO names thus defined are only referenced in the rest of the codebase if virtual wires are not enabled for those signals, in which case the GPIOs will be configured as interrupts. BUG=b:143288478,b:139553375 TEST=Build dragonegg and tglrvpu_ite BRANCH=none Change-Id: I7b59bb315e333ab62257f206159d95a6d3c6a0ca Signed-off-by: Abe Levkoy <alevkoy@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1881757 Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* PCH_PLTRST_L: Use appropriate config optionAbe Levkoy2019-10-305-10/+4
| | | | | | | | | | | | | | | | | Define a GPIO for PCH_PLTRST_L based on CONFIG_HOSTCMD_ESPI, because that is the configuration option used to enable to use of the the GPIO signal name thus defined. Remove the now unused CONFIG_HOSTCMD_PLTRST_IS_VWIRE option. BUG=b:139553375,b:143288478 TEST=Build it83xx_evb, reef_it8320, and tglrvpu_ite BRANCH=none Change-Id: Ia0dbfee0c6c2eda566e79cad7ab6e0c685809c05 Signed-off-by: Abe Levkoy <alevkoy@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1881756 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org>
* puff: Initial EC files for puffAndrew McRae2019-10-297-0/+957
| | | | | | | | | | | | | | | Skeleton EC files for puff. Enough GPIOs and functions defined to allow files to build, but don't expect anything to work or be complete. BUG=b:143454886 TEST=None, code compiles. Change-Id: I4badd1741cf04c71b4ae687afe9d06d8e0b8a813 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1880784 Tested-by: Andrew McRae <amcrae@chromium.org> Commit-Queue: Andrew McRae <amcrae@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* hatch: Enable ANX7447 internal pu/pd on AUX for hatch variantsScott Collyer2019-10-294-0/+4
| | | | | | | | | | | | | | | | | | This CL enables the config option CONFIG_USB_PD_TCPM_ANX7447_AUX_PU_PD for hatch variants that have the ANX7447 TCPC. BUG=b:124410548 BRANCH=None TEST=On hatch, connect external monitor,usb device or CCD cable to type-c port0. Verifed each worked as expected. Change-Id: I7cd6ce65dac42dffd41a0f75fc844b634d7d312f Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1788333 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Nitin Kolluru <nkolluru@google.com> Commit-Queue: Scott Collyer <scollyer@chromium.org>
* trembyle: Add GPIO_USB_C0_IN_HPD and IOEX_USB_C0_DATA_ENDenis Brockus2019-10-281-0/+2
| | | | | | | | | | | | | | | | | These are not defined and are needed for MB USB-C to run at USB3.0 speeds BUG=b:143460349 BRANCH=none TEST=make buildall -j TEST=Verify USB3.0 when manually asserting these high Change-Id: I8a73b25521a5bcf217b6e0a0d881f00555ceabe9 Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1884268 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org> Commit-Queue: Edward Hill <ecgh@chromium.org>
* volteer: Remove ISR todoAbe Levkoy2019-10-281-1/+0
| | | | | | | | | | | | | | There is no need to change the ISR for RSMRST, so remove the todo. BUG=b:139553375 TEST=make buildall BRANCH=none Change-Id: I3ccc5c80432aa085f8492b96446456bf0ef1c1a4 Signed-off-by: Abe Levkoy <alevkoy@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1881755 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org>
* helios: Remove ALS OPT3001 configurationMichael5 Chen2019-10-282-40/+0
| | | | | | | | | | | | | | | Helios does not have an ambient light sensor (ALS). Remove the ALS OPT3001 configuration. BUG=b:142881461 BRANCH=None TEST=Manual Check EC console message. Change-Id: I91b94b3f9842621fc7b70e8dc9e84533174febfd Signed-off-by: Michael5 Chen <michael5_chen@pegatroncorp.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1871491 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
* kukui: set SPI pin to high speedTing Shen2019-10-263-9/+0
| | | | | | | | | | | | | | | | | The SPI pins should be configured to high speed to meet the spec. And since the pin assignment is same on all kukui families, move the setup code to baseboard/. BUG=b:138768646 TEST=verified by observe the waveform BRANCH=kukui Change-Id: I5b07767000bdf47101f83d338d06e7679c4f4848 Signed-off-by: Ting Shen <phoenixshen@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1770329 Reviewed-by: Eric Yilun Lin <yllin@chromium.org> Commit-Queue: Hung-Te Lin <hungte@chromium.org> Tested-by: Hung-Te Lin <hungte@chromium.org>
* krane: Modify the charge indicatorLeo Zhou2019-10-261-2/+13
| | | | | | | | | | | | | | | | Based on the OD, the charge indicator should be red under low battery BUG=b:142835019 BRANCH=kukui TEST=1. Charge DUT to battery SOC > 20%, then plug out charger 2. Wait for battery SOC <= 10%, notice the charge indicator Change-Id: I2013bc6182067ddf64bb790f5cbf4bc0621b7899 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1871502 Reviewed-by: Eric Yilun Lin <yllin@chromium.org> Tested-by: Leo Zhou <zhoubo@huaqin.corp-partner.google.com> Commit-Queue: Hung-Te Lin <hungte@chromium.org>
* drallion_ish: correct lid accelerometer rotation matrixJack Rosenthal2019-10-261-2/+2
| | | | | | | | | | | | | Z axis was inverted. BUG=b:140311300 BRANCH=none TEST=use ectool to verify sane values at various lid angles Change-Id: I48863fc336474f34e123ee37f495aff35251b111 Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1881930 Reviewed-by: Mathew King <mathewk@chromium.org>
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