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* usb_spi: refactor to allow use in different contextsstabilize-quickfix-13099.93.B-cr50_stabstabilize-13099.94.B-cr50_stabstabilize-13099.90.B-cr50_stabstabilize-13099.85.B-cr50_stabstabilize-13099.73.B-cr50_stabstabilize-13099.72.B-cr50_stabstabilize-13099.70.B-cr50_stabstabilize-13099.118.B-cr50_stabstabilize-13099.110.B-cr50_stabstabilize-13099.101.B-cr50_stabrelease-R84-13099.B-cr50_stabVadim Bendebury2020-05-141-29/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The code which allows to read a section of AP or EC flash and calculate the section's SHA256 sum does not allow calculating the sum over multiple non-adjacent flash areas. This patch changes the implementation to allow calculations over more than one region. Initialization, calculation and reporting of the result become three separate API entries. The loop counting the number of the read flash chunks, is being simplified, a watchdog kick added to the brief loop interruptions, as it turns out that sleeping alone is not enough to prevent watchdog expiration when calculating hash over large SPI flash ranges. Also simplified prototypes for usb_spi_board_enable() and usb_spi_board_disable(). BUG=b:153764696 TEST=created an RO descriptor for the Atlas DUT and verified that 'gsctool -O' succeeds. Cq-Depend: chrome-internal:2939596 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Change-Id: Iec7b8634c7c80ebc7600c5b708879eb322bc7fec Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2163569 Reviewed-by: Andrey Pronin <apronin@chromium.org>
* make cr50 agnostic about EC-EFS2Namyoon Woo2020-05-141-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch makes cr50 respond EC-EFS2 related TPM commands no matter it has the board property, BOARD_EC_CR50_COMM_SUPPORT or not. board_has_ec_cr50_comm_support() calls remain for configuring GPIO_EC_PACKET_MODE_EN only. BUG=b:155214584 TEST=checked gsctool running on Coral. [before] $ gsctool --getbootmode finding_device 18d1:5014 Found device. found interface 3 endpoint 4, chunk_len 64 READY ------- Error 8 in Getting boot mode [after] $ gsctool --getbootmode finding_device 18d1:5014 Found device. found interface 3 endpoint 4, chunk_len 64 READY ------- Boot mode = 0x00: NORMAL Also checked 'ec_comm' uart command. [before] > ec_comm No EC-CR50 comm support Invalid argument Usage: ec_comm [corrupt] [after] > ec_comm uart : 0xff packet mode : DISABLED phase : 0 preamble_count : 0 bytes_received : 0 bytes_expected : 0 response : 0x0000 ec_hash : UNLOADED <-- It is marked as unloaded, secdata_error_code : 0x00001203 <-- because of NVMEM error. boot_mode : NORMAL <-- Still, boot_mode is normal. Signed-off-by: Namyoon Woo <namyoon@google.com> Change-Id: I08dc9abd8f194c83484b5be9b0a5e8844b2fd221 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2185872 Tested-by: Namyoon Woo <namyoon@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Commit-Queue: Namyoon Woo <namyoon@chromium.org>
* VENDOR_CC_WP: allow to enable write protection (WP)Vadim Bendebury2020-04-141-1/+10
| | | | | | | | | | | | | | | | | | | | | | | The gsctool utility allows to examine the device WP status, but does not allow to set it. It would be useful to provide the user with a means of enabling WP at any time. This patch extends the existing vendor command VENDOR_CC_WP implementation to allow an optional one byte parameter. If the parameter is present, the Cr50 will unconditionally invoke set_wp_state(1) when processing the command. BUG=b:153881773 TEST=with the corresponding gsctool.c changes coming up in the next patch verified that attempts to enable WP when running the unmodified Cr50 image fail with error message "Early Cr50 versions do not support setting WP", and that the updated Cr50 image allows to enable WP using 'gsctool -a -w enable' Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Change-Id: I75c200bbb9085e9f74c227ef80f782defdaaa29e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2149519 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* Implement sequence for detecting trigger for AP RO verificationVadim Bendebury2020-04-131-0/+111
| | | | | | | | | | | | | | | | | | | | | | | | | | | | When supported, the AP RO verification would be triggered by the operator pressing and keeping pressed the power button and then pressing and releasing a few times the refresh key. As proposed in this patch, to trigger the verification the operator must complete the sequence within 3 seconds by pressing the refresh key three times. The sequences is controlled by periodic polling. Enabling refresh key press interrupts was investigated, the issue is that the key generates plenty of interrupts due to dribbling, to the tune of a hundred each time it is pressed. It is much cheaper to just poll every 20 ms. The CONFIG_AP_RO_VERIFICATION config flag controls enabling of this feature. BUG=b:141191727 TEST=enabled the new feature and verified proper operation by both detecting the trigger and abandoning the sequence due to released power button or not enough times pressed refresh key. Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Change-Id: I55376a87009d6f8020358ad11db1e47d0b8393ed Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2144944 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* Add a sw flag to indicate usb_i2c statusNamyoon Woo2020-04-091-7/+6
| | | | | | | | | | | | | | | Cr50 used to read GPIO_EN_PP3300_INA_L value to detect if USB_I2C is enabled. However it requires an external pullup. Instead, this patch adds a sw flag to indicate USB_I2C status, so that it can keep USB_I2C status regardless external HW factors. BUG=b:152946978 TEST=ran flash_ec on waddledee, ampton, and dragonegg. Signed-off-by: Namyoon Woo <namyoon@chromium.org> Change-Id: Ie1a3a8c790e9643a3b49b6c519167ee3bdecc650 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2140535 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* speed up AP State polling when CCD is active.Vadim Bendebury2020-04-081-2/+27
| | | | | | | | | | | | | | | | | | | It turns out that the Cr50 not shutting off the AP UART quickly enough causes violation of the JSL power sequence requirements due to the leakage caused by the active UART lines. Let's speed up AP state polling when CCD is active. When CCD is not active the UART is shut of to start with. BUG=b:152446186 TEST=running the new image verified that that timing constraints are not violated any more. Also verified reliable UART=>USB bridging operation. Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Change-Id: Iffb7f8bc33c4516bb7cf5cbf58c5ced277cd1aec Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2139732 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* tpm2: clean up stubs.cVadim Bendebury2020-03-251-17/+4
| | | | | | | | | | | | | | | Drop the unused function and use ccprintf() instead of uart_printf(). Using ccprintf() will make it easier to use this code when packet mode is enabled. Used tabs in the changed lines s to pacify repo upload. BUG=b:149964350 TEST=make buildall -j Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Change-Id: I97522e9278a4393ef75b9a6a90e6995ba2449f30 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2114237
* change the init proiorities of ec_efs_init() and ec_comm_init()release-R82-12974.B-cr50_stabNamyoon Woo2020-03-121-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch reprioritizes ec_comm_init() and ec_efs_init() so that they won't be executed prior to board_init(), which executes nvmem_init(). BUG=b:151187315 BRANCH=cr50 TEST=let cr50 reboot a few times, and checked the console message and the ec_comm command output that Kernel secdata was reloaded without error. Swapped cr50 image from normal to dev, vice versa, and repeated the rebooting. [Reset cause: hard] [0.003799 Inits done] strap pin readings: a1:2 a9:3 a6:0 a12:0 [0.005893 Valid strap: 0xe properties: 0xa00041] [0.007991 init_jittery_clock_locking_optional: run level high, ... [0.045539 init took 29953] [0.051185 tpm_rst_asserted] [0.052074 EC-COMM: Initializtion] Console is enabled; type HELP for help. ... > ec_comm ... response : 0xec00 ec_hash : LOADED secdata_error_code : 0x00000000 > Change-Id: Ia695896986374ac9d23ac111fe0086ec6a13923e Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2093102 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* introducing an unittest of EC-EFSNamyoon Woo2020-03-114-0/+77
| | | | | | | | | | | | | | | This patch adds a test case for EC-EFS functions. BUG=b:150650877 BRANCH=cr50 TEST=make run-ec_comm make runhosttests make buildall -j Signed-off-by: Namyoon Woo <namyoon@chromium.org> Change-Id: I90cdc3aa73cf8946da4cf094de5ca0adfaaa0a7c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2096338 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* move ec_comm implementation to common directoryNamyoon Woo2020-03-105-652/+2
| | | | | | | | | | | | | | | This patch moves ec_comm.c and ec_efs.c from board/cr50 to common/, so that they can be shared with other board configuration (like host). This is to build unittest for those files. BUG=none BRANCH=cr50 TEST=make buildall -j Signed-off-by: Namyoon Woo <namyoon@chromium.org> Change-Id: I67ac313054ebe4604848a176f0a42e3483957e74 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2094076 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* fix in EC-EFS command, SET_BOOT_MODENamyoon Woo2020-03-101-1/+1
| | | | | | | | | | | | | | | | This patch changes fixes the pre-condition to check before it processes the command, SET_BOOT_MODE. It should check if the current boot mode is NORMAL mode, but it used to check if the input parameter value is NORMAL mode. BUG=none BRANCH=cr50 TEST=make buildall -j Signed-off-by: Namyoon Woo <namyoon@chromium.org> Change-Id: I85e0a3a1ed27a276262a7b9d3889c826cca14d19 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2094075 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* cr50: Provision DIOM4 as inputVadim Bendebury2020-02-271-0/+10
| | | | | | | | | | | | | | | | | This will allow using this pin a physical presence indicator on certain platforms. BRANCH=cr50,cr50-mp BUG=b:144455668 TEST=tried the new image on the red board, observed DIOM4 level changing when shorting it to ground. Change-Id: I7c20b094d73d49321921c5afa67e0db9825ea82f Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2076499 Reviewed-by: Yicheng Li <yichengli@chromium.org> Commit-Queue: Yicheng Li <yichengli@chromium.org> Tested-by: Yicheng Li <yichengli@chromium.org>
* capitalize enum tpm_read_rv and tpm_write_rvstabilize-volteer-12931.B-cr50_stabNamyoon Woo2020-02-225-25/+25
| | | | | | | | | | | | This patch fixes a coding style violation in enum name. BUG=none BRANCH=cr50 TEST=none Change-Id: I53eb8aa0905ecfc841a4fe7a738df74d571e321b Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2065493
* EC-CR50 communicationNamyoon Woo2020-02-223-4/+335
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch supports EC-CR50 communication. EC activates EC-CR50 communication by setting high DIOB3, and send a command packet to CR50 through UART_EC_TX_CR50_RX. Cr50 processes the packet, and sends a response packet back to EC. EC deactivates EC-CR50 communication by putting low DIOB3. This patch supports two kinds of EC-CR50 commands: - CR50_COMM_CMD_SET_BOOT_MODE - CR50_COMM_CMD_VERIFY_HASH Cr50 stores some of EC-EFS context in a powerdown register before deep sleep and restores it after wakeup. This patch increases flash usage by 1456 bytes. BUG=b:119329144 BRANCH=cr50 TEST=Checked "ec_comm" console command on Octopus and reworked Helios. Checked uart_stress_tester.py running without character loss. Change-Id: I23e90b9f3e860a3d198dcee718d7d11080d06e40 Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1961145 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* cr50: add TPM vendor-specific commands to support EC-EFS2Namyoon Woo2020-02-221-0/+43
| | | | | | | | | | | | | | | | | | | Based on the design in go/ec-efs2, this patch adds two TPM vendor-specific commands: - VENDOR_CC_GET_BOOT_MODE - VENDOR_CC_RESET_EC BUG=b:141578322 BRANCH=cr50 TEST=tested with EC-EFS supporting EC/AP firmware. With CR50 dev image, tested with gsctool on Octopus and Helios by sending each of new vendor commands. Checked flash_ec working on Scarlet in bitbang mode. Change-Id: Ia8f38a7b9cc45b172a1a1ef7e216034e520b79c7 Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1956409 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* read EC Firmware hash from kernel secdata during board initNamyoon Woo2020-02-223-1/+73
| | | | | | | | | | | | | | Cr50 reads EC Firmware hash from kernel secdata. This data shall be used for EC-EFS (Early Firmware Selection) procedure. BUG=chromium:1020578, b:148489182 BRANCH=cr50 TEST=none Change-Id: Id8942b5b49dd5b0412d198a12ee0bf87fd59d47f Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1956159 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* ccdblock can block EC-CR50 communicationNamyoon Woo2020-02-203-4/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch introduces 'EC_CR50_COMM' a new option for ccdblock console command. It can be useful for system rescue purpose like you want to force cr50 to yield EC_UART (especially TX) port to servo. BUG=chromium:1047287 BRANCH=cr50, cr50-mp TEST=ran manually ccdblock. > ccdstate AP: off AP UART: off EC: on Rdd: connected Servo: undetectable CCD EXT: enabled State flags: UARTEC+TX I2C SPI CCD ports blocked: (none) > > > ccdblock EC_CR50_COMM enable CCD ports blocked: EC_CR50_COMM > [73.386550 CCD state: UARTEC I2C SPI] > > ccdstate AP: off AP UART: off EC: on Rdd: connected Servo: disconnected CCD EXT: enabled State flags: UARTEC I2C SPI CCD ports blocked: EC_CR50_COMM > > > ccdblock EC_CR50_COMM disable CCD ports blocked: (none) > [104.781623 CCD state: UARTEC+TX I2C SPI] ccdstate AP: off AP UART: off EC: on Rdd: connected Servo: undetectable CCD EXT: enabled State flags: UARTEC+TX I2C SPI CCD ports blocked: (none) Change-Id: I7816c201054f1793906bd19d4b58755593d2fbac Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2042118 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* restructure EC-EFS moduleNamyoon Woo2020-02-208-12/+134
| | | | | | | | | | | | | | | - add ec_efs, which tracks the system boot mode. - add ec_comm.h header file for EC-EFS related functions. - revised vboot.h header file. BUG=b:141143112 BRANCH=cr50 TEST=none Change-Id: Iec1bf466b832bac5ad6be8a52304c1d699a38fb2 Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2055363 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* optimize read_tpm_nvmem()Namyoon Woo2020-02-191-3/+6
| | | | | | | | | | | | | | | | | | This patch optimizes read_tpm_nvmem() by replacing NvGetIndexData() and NvGetIndexInfo() with NvReadIndexDta() and NvReadIndexInfo() respectively. This will reduce NvFindHandle() calls from three to one. BUG=b:148489182 BRANCH=cr50, cr50-mp TEST=The function execution time reduces from 1.2 msec to 550 usec. Cq-Depend:chromium:2038108 Change-Id: I6659480d8b60578f3d0b9dc3f62a677ae8489a57 Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2037920 Reviewed-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Andrey Pronin <apronin@chromium.org>
* control UART_EC RX/TX based on EC-CR50 communication statusNamyoon Woo2020-02-192-3/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch allows EC-CR50 communication to enable EC UART only if EC is on and bitbang mode is disabled. EC UART shall be enabled even when CCD_CAP_GSC_TX_EC_RX is disabled, EC UART is ccdblocked, or servo is connected. EC-CR50 comm supporting boards are supposed to have H1 dominate EC UART TX line against servo. Servo detection, which is checked every second, shall be delayed during EC-CR50 communication because EC UART TX pin (GPIO_SERVO_DETECT) is used as an output. Servo state shall be held as it was. Once EC-CR50 communication is done, the servo detection will resume or CCD state gets updated based on what it used to be before EC-CR50 communication. BUG=chromium:1035706 BRANCH=cr50 TEST=manually tested on a reworked Helios. // CCD connection only > ccdstate AP: off AP UART: off EC: on Rdd: connected Servo: undetectable CCD EXT: enabled State flags: UARTEC+TX I2C SPI CCD ports blocked: (none) > ecrst pulse Pulsing EC reset EC_RST_L is deasserted // Servo connection only > ccdstate AP: off AP UART: off EC: on Rdd: disconnected Servo: connected CCD EXT: disabled State flags: I2C CCD ports blocked: (none) Change-Id: I02667bee004d237d846393a18f247970982c71b7 Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2023239 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* control EC USB-UART bridgeNamyoon Woo2020-02-191-1/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This CL separates the control on USB-UART bridge of EC device from EC UART control. USB-UART bridge shall be enabled if CCD connection is detected and the CCD capability is enabled. Otherwise, EC USB-UART shall be disabled. By doing so, CCD capability can be observed even when EC-CR50 communication enables EC UART. This patch increases the flash usage by 204 bytes BUG=b:148247228 BRANCH=cr50, cr50_mp TEST=ran firmware_Cr50CCDServoCap on Helios. > ccd State: Locked Password: none Flags: 0x000001 Capabilities: 0000000000000000 ... > ccdstate AP: on AP UART: on EC: on Rdd: connected Servo: connected CCD EXT: enabled State flags: UARTAP UARTEC I2C USBEC > ccdstate AP: on AP UART: on EC: on Rdd: connected Servo: disconnected CCD EXT: enabled State flags: UARTAP+TX UARTEC USBEC CCD ports blocked: (none) > ccd State: Opened Password: none Flags: 0x800001 Capabilities: 5555454115000000 ... > ccdstate AP: on AP UART: on EC: on Rdd: connected Servo: connected CCD EXT: enabled State flags: UARTAP UARTEC I2C USBEC+TX CCD ports blocked: (none) > ccdstate AP: on AP UART: on EC: on Rdd: connected Servo: undetectable CCD EXT: enabled State flags: UARTAP+TX UARTEC+TX I2C SPI USBEC+TX CCD ports blocked: (none) Change-Id: I6bb560a05831105ff68a9e13e4b28b002ed98096 Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2018061 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* cr50: add Asurada strapMary Ruthven2020-02-191-0/+7
| | | | | | | | | | | BUG=b:147835918 BRANCH=cr50 TEST=none Change-Id: I07d4071c4fe99df0a030be1e087f43a696081c3c Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2051101 Reviewed-by: Namyoon Woo <namyoon@chromium.org>
* use gpio_set_wakepin() to enable or disable wake pinsNamyoon Woo2020-02-131-62/+29
| | | | | | | | | | | | | | | | | This uses gpio_set_wakepin() to setup the wake pins instead of writing to the PINMUX EXITEN registers directly. This patch reduces the flash usage by 248 bytes. BUG=b:35587259 BRANCH=cr50 TEST=checked pinmux configuration hasn't changed on coral. Checked firmware_Cr50DeviceState running good on coral. Change-Id: Ic4ef1751e34b85ea2719f257ebd9b7ad52355eec Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2047923 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* cr50: Defer call to board_reboot_ec() in key_combo0_irq()Mathew King2020-02-101-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | On Wilco devices the recovery key combination will trigger an irq which will reboot the EC to enter recovery mode. CL:1881752 moved a 30 ms delay and made it synchronous. This change works in most contexts except for within an irq which cannot sleep so when a user presses the recovery key combo the H1 will hard reboot when the sleep is called. This change defers the call to board_reboot_ec() so that it is no longer in the irq context. BUG=b:147404780 TEST=On Drallion and Sarien press pwr + F2, recovery mode is entered without to hold the keys for an extended period of time. Also verified that programming flash over CCD still works on Drallion. BRANCH=none Change-Id: Ib7ebbe2c67b575b6a99d01a4055bb00ee9d15b7e Signed-off-by: Mathew King <mathewk@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2020328 Reviewed-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org> Commit-Queue: Keith Short <keithshort@chromium.org> Tested-by: Keith Short <keithshort@chromium.org>
* make DIOB3 interruptible and wakable for EC-EFS2Namyoon Woo2020-02-085-8/+121
| | | | | | | | | | | | | | | | | | | | | If the board supports EC-CR50 communication, Cr50 enables both rising/falling-edge triggered interrupt on DIOB3 pin and makes it wakable as well.Cr50 connects GPIO_AP_FLASH_SELECT to DIOB4. If the board does not support EC-CR50 communication, Cr50 connects GPIO_AP_FLASH_SELECT to DIOB3. If EC puts high on DIOB3 to activate EC-CR50 communication, CR50 enables UART_EC RX and TX. BUG=chromium:1035706 BRANCH=cr50 TEST=none Change-Id: I1221a1a19219274622ab710568ce7c66ab2f1da7 Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1989581 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* revise the uart tx connect/disconnect functionsstabilize-quickfix-12871.27.B-cr50_stabstabilize-12871.91.B-cr50_stabstabilize-12871.65.B-cr50_stabstabilize-12871.57.B-cr50_stabstabilize-12871.253.B-cr50_stabstabilize-12871.24.B-cr50_stabstabilize-12871.103.B-cr50_stabstabilize-12871.102.B-cr50_stabstabilize-12859.B-cr50_stabrelease-R81-12871.B-cr50_stabNamyoon Woo2020-01-221-39/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch reduces redundant condition checking in connecting or disconnecting UART TX. BUG=none BRANCH=cr50 TEST=manually checked ccd state with/without servo connection and/or ccd connection. [AFTER] > ccdstate AP: on AP UART: on EC: on Rdd: connected Servo: connected CCD EXT: enabled State flags: UARTAP UARTEC CCD ports blocked: (none) > ccdstate AP: on AP UART: on EC: on Rdd: disconnected Servo: connected CCD EXT: disabled State flags: CCD ports blocked: (none) > ccdstate AP: on AP UART: on EC: on Rdd: connected Servo: undetectable CCD EXT: enabled State flags: UARTAP+TX UARTEC+TX I2C SPI CCD ports blocked: (none) > ccdstate AP: off AP UART: off EC: on Rdd: connected Servo: undetectable CCD EXT: enabled State flags: UARTEC+TX I2C SPI CCD ports blocked: (none) > ccdstate AP: on AP UART: on EC: on Rdd: connected Servo: disconnected CCD EXT: enabled State flags: UARTAP+TX I2C SPI CCD ports blocked: EC > ccdstate AP: on AP UART: on EC: on Rdd: connected Servo: disconnected CCD EXT: enabled State flags: I2C SPI CCD ports blocked: AP EC > ccdstate AP: on AP UART: on EC: on Rdd: connected Servo: ignored CCD EXT: enabled State flags: UARTAP+TX UARTEC+TX I2C SPI CCD ports blocked: IGNORE_SERVO WARNING: enabling UART while servo is connected may damage hardware Change-Id: Icea2978b15e15bbf7cea8e48fd2bf4fdecc78f46 Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2013823 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* cr50: add support for using a strap pin as a ccd gpioMary Ruthven2020-01-173-1/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change introduces a mechanism which allows to use one of board strap pins as the CCD gpio and makes DIOA9 the CCD pin on boards with strap os 0xE. This change uses 2 bits from the board properties to determine which pin is used as the ccd gpio. 0 - no ccd gpio 1 - DIOA1 2 - DIOA9 3 - DIOA12 DIOA6 is another strap pin, but there's only one valid strap with a 5kPU left, so I decided not to use another board property bit to support it as a possible ccd gpio. I want to save the board property bit, since we're running out of them and there are so many other I2C straps boards can use. We can add it later if we need to. BUG=b:147812066 BRANCH=cr50 TEST=manual. Use pinmux and gpiocfg to verify the output is only enabled when the gpio is asserted. no added brdproperties - nothing is different with pinmux run on Puff gpioset CCD_REC_LID_SWITCH 0 EC shows recovery button pressed gpioset CCD_REC_LID_SWITCH 0 EC shows recovery button released add BOARD_CCD_REC_LID_PIN_DIOA1 to SPI board pinmux output adds DIOA1 27 IN GPIO1_GPIO10 GPIO1_GPIO10 24 DIOA1 gpioset CCD_REC_LID_SWITCH 0 gpiocfg shows "GPIO1_GPIO10: read 0 drive 0" gpioset CCD_REC_LID_SWITCH 1 gpiocfg doesn't show GPIO1_GPIO10 as an output add BOARD_CCD_REC_LID_PIN_DIOA9 to SPI board pinmux output adds DIOA9 27 IN GPIO1_GPIO10 GPIO1_GPIO10 16 DIOA9 gpioset CCD_REC_LID_SWITCH 0 gpiocfg shows "GPIO1_GPIO10: read 0 drive 0" gpioset CCD_REC_LID_SWITCH 1 gpiocfg doesn't show GPIO1_GPIO10 as an output add BOARD_CCD_REC_LID_PIN_DIOA12 to I2C board pinmux output adds DIOA12 27 IN GPIO1_GPIO10 GPIO1_GPIO10 13 DIOA12 gpioset CCD_REC_LID_SWITCH 0 gpiocfg shows "GPIO1_GPIO10: read 0 drive 0" gpioset CCD_REC_LID_SWITCH 1 gpiocfg doesn't show GPIO1_GPIO10 as an output Change-Id: If74385135a572e7e5d0763fad9f5368fdec8d7a0 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2006210 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* add BOARD_EC_CR50_COMM_SUPPORT to board propertiesNamyoon Woo2020-01-144-4/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This CL add a board property indicating EC-CR50 communication support. The target boards are Volteer,Dedede,Puff, and Zork. It shall be detected if the H1 strap configuration value is either 0x0E or 0xE0. BUG=b:146567516, chromium:1027660 BRANCH=cr50 TEST=Flashed AP firmware through CCD on Grunt, Octopus, Scarlet and Atlas. This is the captured console log: --- UART initialized after reboot --- ... strap pin readings: a1:2 a9:2 a6:0 a12:0 [0.005886 Valid strap: 0xa properties: 0x41] > brdprop properties = 0x1141 > brdprop properties = 0x201141 > pinmux ... 400600b0: DIOB2 2 IN GPIO0_GPIO1 400600b8: DIOB3 3 IN GPIO0_GPIO2 400600c0: DIOB4 0 IN PD ... 40060100: GPIO0_GPIO2 7 DIOB3 ... 40060120: GPIO0_GPIO10 6 DIOB4 Flashed AP firmware on a reworked board with 1M ohm on DIOA1 and 5k ohm on DIOA9. This is the captured console log: --- UART initialized after reboot --- ... strap pin readings: a1:2 a9:3 a6:0 a12:0 [0.005886 Valid strap: 0xe properties: 0x200041] > brdprop properties = 0x201141 > pinmux ... 400600b0: DIOB2 2 IN GPIO0_GPIO1 400600c0: DIOB4 3 IN PD GPIO0_GPIO2 ... 40060100: GPIO0_GPIO2 6 DIOB4 ... 40060120: GPIO0_GPIO10 6 DIOB4 Change-Id: If60765190a385a0e728177911b1ec738c6a00d99 Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1979612 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* drop chip factory mode supportVadim Bendebury2020-01-132-22/+0
| | | | | | | | | | | | | | | | There is no need to keep the code supporting chip factory mode in Chrome OS production branches, this code is never used outside of the chip factory environment. BRANCH=cr50, cr50-mp BUG=none TEST=built an image, verified that an Atlas device boots up into the previously created Chrome OS account. Change-Id: If72635b014d15ef6e97fbc4fd5b54b61ec23299a Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1994369 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* drop unnecessary boards, chips and cts testsVadim Bendebury2020-01-07735-116994/+0
| | | | | | | | | | | | | | | | | | | | The only board which would be built from this branch is Cr50. bds, fizz and host boards are necessary for proper make infrastructure operation and tests. lm4 and npcx are chips used by the bds and fizz boards, so they are also kept around. BRANCH=cr50, cr50-mp BUG=b:145912698 TEST='make buildall -j' succeeds Change-Id: I937b2b8642c1fe91578fc9615438ae22c165b20f Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1986942 Reviewed-by: Namyoon Woo <namyoon@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Andrey Pronin <apronin@chromium.org>
* nvmem: do not waste time looking for legacy NVMEM spaceVadim Bendebury2019-12-133-0/+19
| | | | | | | | | | | | | | | | | | | | It takes 14.5 ms to decrypt two 12K flash spaces into SRAM, then calculate their hash to see if either one is is a valid NVMEM space. There is no need for this check when the 'other' Cr50 image is newer than {3,4}.18. BRANCH=Cr50, Cr50-mp BUG=b:132665283 TEST=with added instrumentation verified that in case the other slot is occupied by 0.0.22 image, the check takes 14.5 ms, when the other slot is occupied by 0.4.23 image the check takes 8 us. Change-Id: I0414ca3d7e90d343589a21e91319f35479632eff Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1967543 Reviewed-by: Keith Short <keithshort@chromium.org>
* cr50: change OWNERS to cr50 team membersMary Ruthven2019-12-104-12/+0
| | | | | | | | | | | | | | Change the OWNERS to cr50 team members and remove OWNERS files from all subdirectories. BUG=none BRANCH=none TEST=none Change-Id: I5ddff7c433a55b6724d92c026e9e64e82e1492ad Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1957850 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* g: display both RO and RW info map statusVadim Bendebury2019-12-061-2/+2
| | | | | | | | | | | | | | | | | | | | | | | Cr50 firmware is required to update the rollback prevention map in INFO1 for both RO and RW images. This patch adds code to display the state of the RO map and both RO_A and RO_B headers in addition to previously reported RW information. BRANCH=cr50, cr50-mp BUG=b:136284186 TEST=loaded the new image and observed reported rollback state: > sysinfo ... Rollback: 0/1/1 0/128/128 ... Change-Id: I32206545b6a59a5693e4274e62fcf0627780f61f Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1949546 Reviewed-by: Namyoon Woo <namyoon@chromium.org> (cherry picked from commit 565c54c270bd93ee30e8f8560d3d1691d128e762) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1954341
* cr50: add support for FIPS mode flag in FWMPVadim Sukhomlinov2019-12-062-2/+17
| | | | | | | | | | | | | | | | | | | | | | | | Added definition of FWMP_DEV_FIPS_MODE matching same definition in vboot. Support function board_fwmp_fips_mode_enabled() introduced to read it's status. It's not currently used, but will be consumed by FIPS code. BUG=b:138577491 BRANCH=cr50 TEST=make BOARD=cr50 Change-Id: Iebf672cfebfeb18ae62892097fbf1fa30a770338 Signed-off-by: Vadim Sukhomlinov <sukhomlinov@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1950813 Reviewed-by: Vadim Sukhomlinov <sukhomlinov@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Tested-by: Vadim Sukhomlinov <sukhomlinov@chromium.org> Auto-Submit: Vadim Sukhomlinov <sukhomlinov@chromium.org> Commit-Queue: Vadim Sukhomlinov <sukhomlinov@chromium.org> (cherry picked from commit bf8241699ba35984887e3f1a71d29ea1e92b21fe) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1954340 Tested-by: Vadim Bendebury <vbendeb@chromium.org> Commit-Queue: Vadim Bendebury <vbendeb@chromium.org>
* g: Add support for 192 and 256 bit AES-GCM in DCRYPTO_gcm_initVadim Sukhomlinov2019-12-061-2/+4
| | | | | | | | | | | | | | | | | | | DCRYPTO_gcm_init hardcoded key length to 128 bit causing preventing testing of 192 and 256 bit functionality for AES-GCM. BUG=b:135623371 BRANCH=cr50 TEST=compile, specific test for issue as described in bug Change-Id: I4fc41f6155661709115c57aa944c8976e17bffac Signed-off-by: Vadim Sukhomlinov <sukhomlinov@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1766098 Reviewed-by: Andrey Pronin <apronin@chromium.org> (cherry picked from commit 24f7511e41c1f8140b19d69d9440a3ea6f91bd89) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1954339 Tested-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Commit-Queue: Vadim Bendebury <vbendeb@chromium.org>
* cr50: use new conventions to determine key ladder modeVadim Bendebury2019-12-063-17/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | The new RW dev key does not follow the existing convention of bit 0x4 set in prod Key ID and unset in dev key ID. The suggested approach is to check values of some key manager registers to determine if the device is running in fully configured prod mode or not. BRANCH=cr50, cr50-mp BUG=b:144455990 TEST=tried running this patch on a node locked image: > sysinfo ... RO keyid: 0xaa66150f RW keyid: 0x334f70df ... Key Ladder: dev Change-Id: I73088ce44a8b8bf8e11a0d240d07152b49a3225b Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1915504 Reviewed-by: Andrey Pronin <apronin@chromium.org> (cherry picked from commit 74237689eb277bf1fe0e682cb256825508fa511f) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1954338
* usb_mux: cleanup the usb_mux_get() functionVijay Hiremath2019-11-264-18/+6
| | | | | | | | | | | | | | Simplified the usb_mux_get() function and made the MUX info prints same as in ectool. BUG=none BRANCH=none TEST=make buildall -j Change-Id: Iefb16e1dbd323afbe248b06fe9c53abc63be9a67 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1931284 Reviewed-by: Jett Rink <jettrink@chromium.org>
* puff: update PP3300_SNS dividerPeter Marheine2019-11-261-3/+9
| | | | | | | | | | | | | | The schematic has changed to 9.31k / 47k resistors on this input. BUG=b:1829597655 TEST=still builds BRANCH=None Change-Id: I2856df05b2611edd30d497a35bb871b8f5b173e9 Signed-off-by: Peter Marheine <pmarheine@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1935467 Reviewed-by: Andrew McRae <amcrae@chromium.org> Commit-Queue: Nicolas Boichat <drinkcat@chromium.org>
* treeya : Add new battery informationxiaoqiang.zhu2019-11-262-1/+94
| | | | | | | | | | | | | | | | | | | | | | | treeya need support three new batteries --SMP:L19M3PG1 --LGC:L19L3PG1 --Celxpert:L19C3PG1 The same manufacturer(SMP) has two kinds of batteries, manuf_name can't specify the unique battery, so need to check device_name. BUG=none BRANCH=none TEST=boot treeya board with new batteries, charging/discharging/cutoff work as expected. Change-Id: I09e2a68961e5df92c6b6d639963ac8894eb7ec20 Signed-off-by: xiaoqiang.zhu <xiaoqiang.zhu@bitland.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1933788 Reviewed-by: Edward Hill <ecgh@chromium.org> Reviewed-by: Peichao Li <peichao.wang@bitland.corp-partner.google.com> Tested-by: Peichao Li <peichao.wang@bitland.corp-partner.google.com> Commit-Queue: Edward Hill <ecgh@chromium.org>
* zork: make product ID project levelDenis Brockus2019-11-251-8/+0
| | | | | | | | | | | BUG=none BRANCH=none TEST=none Change-Id: I7cd71e246708dd4423b7fc3021a644e2988e2771 Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1930868 Reviewed-by: Jett Rink <jettrink@chromium.org>
* jinlon: add FAN2 supportDevin Lu2019-11-243-1/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | BUG=b:141259174 BRANCH=hatch TEST=faninfo can see the 2nd fan works with console. 2019-11-22 14:23:55 Fan 0 Actual: 3309 rpm 2019-11-22 14:23:55 Fan 0 Target: 3291 rpm 2019-11-22 14:23:55 Fan 0 Duty: 42% 2019-11-22 14:23:55 Fan 0 Status: 2 (locked) 2019-11-22 14:23:55 Fan 0 Mode: rpm 2019-11-22 14:23:55 Fan 0 Auto: yes 2019-11-22 14:23:55 Fan 0 Enable: yes 2019-11-22 14:23:55 Fan 0 Power: yes 2019-11-22 14:23:55 2019-11-22 14:23:55 Fan 1 Actual: 3101 rpm 2019-11-22 14:23:55 Fan 1 Target: 3291 rpm 2019-11-22 14:23:55 Fan 1 Duty: 37% 2019-11-22 14:23:55 Fan 1 Status: 2 (locked) 2019-11-22 14:23:55 Fan 1 Mode: rpm 2019-11-22 14:23:55 Fan 1 Auto: yes 2019-11-22 14:23:55 Fan 1 Enable: yes Change-Id: I88aa8efcbb55d8a64ae51c68b5a142e5a4997f46 Signed-off-by: Devin Lu <Devin.Lu@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1928542 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* krane: Use the PWM mode to adjust brightness as lowestLeo Zhou2019-11-221-4/+22
| | | | | | | | | | | | | | | | | | Adjust current=4ma, pwm=1/32, and change the state as: charging is blue charged full is green low battery is red BUG=b:137618886 BRANCH=kukui TEST=Do a full charging test, notice LED indicator status under different charge state Change-Id: Ic1b7a99ab3edaee5c92a5cae56bc6d9a321e9c23 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1918995 Reviewed-by: Eric Yilun Lin <yllin@chromium.org> Tested-by: Kook Zhang <zhangbinbin@huaqin.corp-partner.google.com> Commit-Queue: Leo Zhou <zhoubo@huaqin.corp-partner.google.com>
* it83xx/spi_master: correct the module IDtim2019-11-221-4/+4
| | | | | | | | | | | | | | The module ID in alternate function setting for spi master should be corrected as MODULE_SPI_MASTER. BUG=none BRANCH=none TEST=make buildall -j Change-Id: Ib52b09a5f1e0c496374d4ed2f3a222dab9af2eb0 Signed-off-by: tim <tim2.lin@ite.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1868133 Reviewed-by: Jett Rink <jettrink@chromium.org>
* all hatch variants: Make sure EC_RST_ODL is GPIO_LOCKEDShelley Chen2019-11-225-0/+55
| | | | | | | | | | | | | BUG=b:144886704 BRANCH=hatch TEST=make buildall Change-Id: I0d520a5c375a2b47c55a335da91f556ccfd59c29 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1928422 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org>
* all hatch variants: Assign SYS_RST_ODL to GPIOC5Shelley Chen2019-11-225-4/+5
| | | | | | | | | | | | | | | | | There is an error where SYS_RST_ODL is assigned to GPIO02 where it is actually assigned to GPIOC5 in the schematics. This should cause AP reset to fail from the ec console. BUG=b:141476349 BRANCH=hatch TEST=None (I don't have a hatch board to test this out on) Change-Id: I855a65489ce974ee92be4bf51a83d5af40e4e2da Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1928421 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org>
* Dratini/Jinlon: Add support for TEMP_SENSOR3Devin Lu2019-11-226-10/+28
| | | | | | | | | | | | | | A new temperature sensor is added to Dratini/Jinlon boards, close to the CPU. It is used to support the fan control. BUG=none BRANCH=hatch TEST=temp command in EC console Change-Id: Icd5974133da5e1aec81f2201f87e1b83b79c6169 Signed-off-by: Devin Lu <Devin.Lu@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1925802 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
* jinlon: change TCPC port 0 from ANX7447 to PS8751Devin Lu2019-11-223-9/+8
| | | | | | | | | | | | | | | | | This patch chagnes TCPC port 0 from ANX7447 to PS8751, It includes the gpio name, function name and reset signal. BUG=none BRANCH=hatch TEST=make sure tcpc port 0 is workable. Change-Id: I698d70750727080f46cffdc136ffd8a54967ca89 Signed-off-by: Devin Lu <Devin.Lu@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1918984 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Scott Collyer <scollyer@chromium.org> Commit-Queue: Paul Fagerburg <pfagerburg@chromium.org>
* Trogdor: Initial board commitWai-Hong Tam2019-11-228-0/+1648
| | | | | | | | | | | | | | | | | | | | | | | | | | | This is an initial commit for Trogdor. Use Cheza as a baseline. Make the change according to the schematic, e.g. * Reflect the GPIO change * Reflect the TCPC/PPC part change * Update the USB topology, e.g. no device mode support * Remove the detachable related code * Add keyboard support * Support keyboard backlight * Update the battery characteristic * Add initial support of muxing DP path * Support a single USB-A port * Change sensors from lid to base * Minor code style improvement BRANCH=None BUG=b:143616352 TEST=BOARD=trogdor make Change-Id: Ia9bb0adfcb8d347e6335fd3ae1e565b0f9d1a025 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1847204 Reviewed-by: Stephen Boyd <swboyd@chromium.org> Reviewed-by: Alexandru M Stan <amstan@chromium.org>
* cleanup: Segregate ioexpander related drivers in ioexpander folderVijay Hiremath2019-11-226-6/+6
| | | | | | | | | | | BUG=none BRANCH=none TEST=make buildall -j Change-Id: I7fe9ab23254dbd8515936d10ad6782305e76236c Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1925173 Reviewed-by: Jett Rink <jettrink@chromium.org>
* volteer: disable CONFIG_BRINGUPKeith Short2019-11-211-6/+0
| | | | | | | | | | | | | | | | Disable CONFIG_BRINGUP option now that the AP power up sequence is working. Also change the default console mask to disable CC_HOSTCMD, which is flooded with motion sense requests (0x60) from the kernel. BUG=b:142409811 BRANCH=none TEST=make buildall TEST=verify Volteer boots to OS automatically. Change-Id: I58f850188ca3981373af06369eb70c5887c7da31 Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1919402 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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