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* CR50: Fix ECC key generation to match the code used in factoryMeng-Huan Yu2018-11-221-15/+27
| | | | | | | | | | | | | | | | | | | | Fix the workaround of ECC key generation. The workaround crrev.com/c/360441 for b/35576109 use a wrong EK template to generate the hash (object name of publicArea), and the format of that embedded hash is incorrect either. BRANCH=none BUG=b:35576109,b:80207339 TEST=Dump the EK seed from CR50 and verify the public and private key are matched in both cr50-side (also checked returned value of CreatePrimary) and factory-side. Change-Id: Ia53084757d9d848fd92e6ca309de83450cb64309 Signed-off-by: Meng-Huan Yu <menghuan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1329261 Reviewed-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Andrey Pronin <apronin@chromium.org>
* Ampton: Correct accel sensor base reference dependent on sensor locationJames_Chao2018-11-211-8/+6
| | | | | | | | | | | | | | BUG=b:118756407 BRANCH=none TEST=accelinfo on Change-Id: I3e9f1791a12e5cb63572b1d50435b4e7a42b7ccd Signed-off-by: James_Chao <james_chao@asus.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/1343641 Commit-Ready: James Chao <james_chao@asus.corp-partner.google.com> Tested-by: James Chao <james_chao@asus.corp-partner.google.com> Reviewed-by: James Chao <james_chao@asus.corp-partner.google.com> Reviewed-by: Diana Z <dzigterman@chromium.org>
* liara: Use CONFIG_LED_PWM_CHARGE_STATE_ONLYEdward Hill2018-11-211-1/+1
| | | | | | | | | | | | | | | | | | | Liara only has a single LED on one side, and it should show only the charge state (instead of including chipset state and low battery state as well). Change from CONFIG_LED_PWM_ACTIVE_CHARGE_PORT_ONLY to use the newly added CONFIG_LED_PWM_CHARGE_STATE_ONLY. BUG=b:119746227 BRANCH=grunt TEST=Liara LED is on when charging from either side. Change-Id: If71339be836037a88eb17933ba1a817bd10d5002 Signed-off-by: Edward Hill <ecgh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1344796 Tested-by: Josh Tsai <josh_tsai@compal.corp-partner.google.com> Reviewed-by: Diana Z <dzigterman@chromium.org>
* atlas_ish: remove HostCommand task related.Kyoung Kim2018-11-211-3/+1
| | | | | | | | | | | | | | | | Atlas is migrated from Host Command to HECI protocol. Remove Host Command task and old ipc task. BUG=b:79676054 TEST=none Change-Id: Ic77b1d16de7772a1c69cba6fcf5d7d7849a06213 Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1263897 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Kyoung Il Kim <kyoung.il.kim@intel.com> Reviewed-by: Caveh Jalali <caveh@google.com> Reviewed-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
* Servo v4: reduce RO flash sizeDiana Z2018-11-202-2/+8
| | | | | | | | | | | | | | | Currently, the servo_v4 build is within 48 bytes of exceeding its RO flash size. With this change to remove the USART3 code from the RO image, there should be just about 350 free bytes of space. BRANCH=None BUG=None TEST=builds, hey_flash_used in RO elf file shows 0x170 free bytes Change-Id: I7ee8f6c964eb3e0fb009fba61430bab656c03c2e Signed-off-by: Diana Z <dzigterman@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1340545 Reviewed-by: Nick Sanders <nsanders@chromium.org>
* ocotpus: move VBUS_ADC config to baseJett Rink2018-11-1910-61/+11
| | | | | | | | | | | | | | | | All boards but yorp have added the ADC hardware support back for VBUS ADC measurements. Move code to common baseboard BRANCH=none BUG=none TEST=ADC measurements still works on phaser and fleex Change-Id: I36a7ba92df21de4c1188613c6a12da83fdba6eb6 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1337456 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Karthikeyan Ramasubramanian <kramasub@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org>
* Fizz: Set initial fan speed to 50%Daisuke Nojiri2018-11-191-0/+2
| | | | | | | | | | | | | | | | | This patch sets initial fan speed to 50% to reduce fan noise at start-up and resume. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=b:118701592 BRANCH=none TEST=Verify fan starts spinning on Fizz at 50% speed. Change-Id: I230eb2b6c33499f96d0583b5d75f2674960a35ff Reviewed-on: https://chromium-review.googlesource.com/1309036 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* Fizz: Add Jax supportDaisuke Nojiri2018-11-192-19/+26
| | | | | | | | | | | | | | | | | | | If OEM_ID is equal to 8 (Jax), the EC works as follows: - Set barrel jack adapter spec to (19V, 3.42A). - Set fan_count to zero Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=b:116588924 BRANCH=none TEST=Boot Fizz with OEM=8. Change-Id: Id6489b65a0bb71cd56d4fcf5e2fdbacb630aa99a Reviewed-on: https://chromium-review.googlesource.com/1308258 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* Ampton: enable the interrupt for GPIO_BASE_SIXAXIS_INT_LJames_Chao2018-11-192-1/+7
| | | | | | | | | | | | | | | BUG=none BRANCH=none TEST=accelinfo on Change-Id: I04764b0ce3f963f12f7977b08c89a375c2319d00 Signed-off-by: James_Chao <james_chao@asus.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/1335292 Commit-Ready: James Chao <james_chao@asus.corp-partner.google.com> Tested-by: James Chao <james_chao@asus.corp-partner.google.com> Reviewed-by: James Chao <james_chao@asus.corp-partner.google.com> Reviewed-by: Marco Chen <marcochen@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* kukui: Fix shipping mode VSYS leakage.Yilun Lin2018-11-191-1/+7
| | | | | | | | | | | | | | | | | | | | Follow the cut-off procedure recommended by Richtek. Also, tcpc_read/tcpc_write function will wake the TCPC up from low power mode and thus causing the TCPC re-init again, and this will break the register state we set. So, here we use mt6370_i2c_read/write to replace tcpc_read/write. TEST=boot system; Exec cutoff, and check that Vsys equals to zero. BUG=b:116682788 BRANCH=None Change-Id: I5cbd0df490ddb64b9376507e42a259c008c3ba16 Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/1335289 Commit-Ready: Yilun Lin <yllin@chromium.org> Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* cr50: Add board strapping options for Sarien/ArcadaKeith Short2018-11-162-8/+47
| | | | | | | | | | | | | | | | | | | | | Add 2 new board properties: * BOARD_WP_DISABLE_DELAY - forces an additional delay after detecting battery removal before disabling write protect * BOARD_CLOSED_SOURCE_SET1 - enables custom CR50 options for Sarien/Arcada boards that use a closed source EC Add Sarien/Arcada to board_cfg_table. BUG=b:118688072 BRANCH=none TEST=make buildall, flashed RW Cr50 firmware onto Careena board and verified boots new version Change-Id: Ic9ffdf4861c2239a1e68eb682152c70fb1f9bfc3 Signed-off-by: Keith Short <keithshort@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1310093 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* Liara: Add LGC batteryEdward Hill2018-11-162-0/+32
| | | | | | | | | | | | | | BUG=b:113823864 BRANCH=grunt TEST=Boot Liara with LGC battery; "cutoff" EC command succeeds; Plug in AC => boot to OS login. Change-Id: If2ea7bd1a6888b7bbe5f4eb0dd3217073d32e346 Signed-off-by: Edward Hill <ecgh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1337468 Tested-by: Josh Tsai <josh_tsai@compal.corp-partner.google.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* phaser: update gpio based on next revJett Rink2018-11-162-11/+21
| | | | | | | | | | | | | | | | | | The reset pin for ANX3447 was added. This pin used to be a 1.8V signal and it now a 3.3V signal, so we need to take care to ensure that older boards don't try to drive 3.3V into the SoC. Other changes are just renames. BRANCH=none BUG=none TEST=current phaser (ID=2) works Change-Id: Ife0a1617f94e4f4a40d43b16328d5540ea35b3ff Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1334031 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Karthikeyan Ramasubramanian <kramasub@chromium.org>
* Nami: Supply power up to 3A + 1.5ADaisuke Nojiri2018-11-161-0/+1
| | | | | | | | | | | | | | | | | | This change allows Nami to supply 3A on one port and 1.5A to the other without changing the max current of the currently active port. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=b:115291657 BRANCH=none TEST=Charge Pixel phone on one port and a USB fan on the other. Verify the current provided to the phone does not drop. Change-Id: I38208feedc616e363c9095f273ea926ea8ebbb12 Reviewed-on: https://chromium-review.googlesource.com/1322070 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* meep: set PD on unused interruptJett Rink2018-11-161-8/+5
| | | | | | | | | | | | | | | If the SKU does not populate the base accel, then we should not enable the interrupt and add a pull down to keep the line from floating. BRANCH=none BUG=none TEST=verfied similar change on bobba Change-Id: I29b4367905dadb741916bc5b9bb045bfc6b784ea Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1336289 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Karthikeyan Ramasubramanian <kramasub@chromium.org>
* fleex: set PD on unused interruptJett Rink2018-11-161-8/+5
| | | | | | | | | | | | | | | If the SKU does not populate the base accel, then we should not enable the interrupt and add a pull down to keep the line from floating. BRANCH=none BUG=none TEST=verfied similar change on bobba Change-Id: I85fdfc001bcafdf4d56a2459837c2f4f4f0b64fa Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1336288 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Karthikeyan Ramasubramanian <kramasub@chromium.org>
* phaser: set PD on unused interruptJett Rink2018-11-161-8/+5
| | | | | | | | | | | | | | | If the SKU does not populate the base accel, then we should not enable the interrupt and add a pull down to keep the line from floating. BRANCH=none BUG=none TEST=verfied similar change on bobba Change-Id: Ifd3ef029a18484a4c227db6fcc4312ea3a8603db Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1336287 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Karthikeyan Ramasubramanian <kramasub@chromium.org>
* bobba: add PD to unused lines to prevent floatJett Rink2018-11-161-11/+11
| | | | | | | | | | | | | | | | | | | | Depending on the model, we do not stuff the base accel or the camera. When we detect those SKU, do not enable the interrupt and add a pull down resistor to prevent the line from floating since there isn't an external pull BRANCH=none BUG=none TEST=Verified that sensors/board still work on Bobba360 and Bobba, also verified that power stayed the same or slightly lower (11.32mW on PP3300_ec_mw to 11.29mW over 10 sec average on bobba. 13.62mW->13.56mW for bobba360). Change-Id: I36b01dd79a0f493a2bf9d3cbae54e9863773a056 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1335686 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Karthikeyan Ramasubramanian <kramasub@chromium.org>
* Meep: update EC GPIOs for board version 1Diana Z2018-11-152-13/+20
| | | | | | | | | | | | | | | | | | | | Between board versions 0 and 1, meep added the Analogix reset GPIO. This line should never be driven high on proto boards, so it's set to open drain on board version 0. Other changes include reallocation of the previous WoV pins, and a renaming of the CCD_MODE pin. BRANCH=None BUG=None TEST=imaged meep proto to verify C0 reset was low, imaged meep EVT and verified default GPIO levels Change-Id: I22b40883b8677327887b92922d63d421e1a27596 Signed-off-by: Diana Z <dzigterman@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1334531 Reviewed-by: Karthikeyan Ramasubramanian <kramasub@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* Nami: Apply full factor to full capacityDaisuke Nojiri2018-11-151-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | This change applies 'full factor' to the battery full capacity. It makes the rest of the system see consistent charge percentage behavior. More concretely, with this change we can get rid of 'full factor' from Powerd because it sees the current charge equal to the full capacity. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> CQ-DEPEND=CL:1314048 BUG=b:109954565,b:80270446 BRANCH=none TEST=Verify display percentages printed by EC and power_supply_info move up synchronously on charge and the LED and the taskbar icon turn to full at the same time. Change-Id: Ic16463d457a6c5c2860b97476c78bdafb9021572 Reviewed-on: https://chromium-review.googlesource.com/1315411 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* atlas: clean up ROP PMIC registersCaveh Jalali2018-11-151-17/+28
| | | | | | | | | | | | | | | | | this replaces some ROP PMIC register magic numbers with their actual names. corrected a few comments about the bits we're writing into these registers along the way. BUG=b:75070158 BRANCH=none TEST=boots on atlas Change-Id: If3be6b4c1d550d7e0770450e9f713282835656b5 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1278096 Commit-Ready: Caveh Jalali <caveh@google.com> Tested-by: caveh jalali <caveh@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* Ampton: add sku id for convertible skuJames_Chao2018-11-151-2/+3
| | | | | | | | | | | | | | | | According to b:112290350, the convertible sku is 1,2,3,4 BUG=b:112290350 BRANCH=none TEST=build Change-Id: I2de55eb070741f3a0058fd390f897a863562f762 Signed-off-by: James_Chao <james_chao@asus.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/1335290 Commit-Ready: James Chao <james_chao@asus.corp-partner.google.com> Tested-by: James Chao <james_chao@asus.corp-partner.google.com> Reviewed-by: James Chao <james_chao@asus.corp-partner.google.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* cheza: Enable CONFIG_HOSTCMD_AP_RESET for debug usageWai-Hong Tam2018-11-151-0/+1
| | | | | | | | | | | | | | | | | | | Enable the host command to issue AP reset. BRANCH=none BUG=b:119261783 TEST=Manually tested as follow: Flashed EC image. Copied the compiled ectool to Cheza. Ran "ectool apreset". Checked EC console: [6698.093141 chipset_reset(4)] [6698.093753 power off 5] ... the power state changing S0 -> S5 -> S0 Change-Id: I2d3e425f7bd7dcb319f039ab4866b2a25197f499 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/1327842
* eve: Enable support for multi-profile DPTFFurquan Shaikh2018-11-152-1/+11
| | | | | | | | | | | | | | | | | | | | | | | | This change enables support for multi-profile DPTF on eve, which uses a hall sensor. Thus the following changes are made: 1. Select config CONFIG_DPTF_MULTI_PROFILE 2. Set profile number based on the TABLET_MODE_L GPIO state (input from the hall sensor indicating completely flipped mode). This change is being done only as a reference for future boards with hall sensors to enable multi-profile DPTF. DO NOT cherry-pick this to any eve branch. CQ-DEPEND=CL:1295851,CL:1295852 BUG=b:117844490 BRANCH=None (Do not cherry-pick to any eve branch) TEST=make -j buildall Change-Id: I71e2078d8f63cc4d5939b76ffca962f041a48e42 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1313471 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@google.com>
* soraka: Enable multi-profile DPTFFurquan Shaikh2018-11-152-0/+10
| | | | | | | | | | | | | | | | | | This change enables multi profile DPTF for soraka by selecting CONFIG_DPTF_MULTI_PROFILE and setting appropriate profile numbers based on base attach/detach state. CQ-DEPEND=CL:1295851,CL:1295852 BUG=b:17844490 BRANCH=None TEST=make -j buildall Change-Id: I7b48025f8eeca9fd585099dc5dce011963780117 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1313470 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@google.com>
* nautilus: Enable multi-profile DPTFFurquan Shaikh2018-11-151-0/+2
| | | | | | | | | | | | | | | | | | | | | | This change enables multi-profile DPTF by selecting the following config options: 1. CONFIG_DPTF_MULTI_PROFILE: Set appropriate profile number based on mode. 2. CONFIG_DPTF_MOTION_LID_NO_HALL_SENSOR: Indicate board does not have a hall sensor and hence profile numbers are updated by motion_lid driver. CQ-DEPEND=CL:1295851,CL:1295852 BUG=b:117844490 BRANCH=None TEST=make -j buildall Change-Id: Ib6f146d4465e815f7f008cc3e2682e412acc32bb Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1313469 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@google.com>
* usb-c: use higher priority task for interruptsJett Rink2018-11-1416-102/+134
| | | | | | | | | | | | | | | | | This should be the last step to make all boards on ToT follow go/usb-pd-slow-response-time. Theses boards all have the higher priority tasks, but they aren't being used since the tcpc interrupt wasn't scheduling calls on it. BRANCH=none BUG=b:112088135 TEST=builds Change-Id: I2c39e661e804f88edd5b34636b93e6e63a5af57f Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1283452 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* SN5S330: treat interrupts as level-sensitiveDiana Z2018-11-132-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | The SN5S330 PPC will pull its /INT pin low until all interrupts are cleared. Since the interrupt pin is treated as edge-sensitive, its handler needs to provide level-checking before exiting. Otherwise, if not all interrupts are cleared before the handler exits, the EC won't see another edge to call the handler again. Boards which share the PPC interrupt pin with other sources may choose to implement their own callback, if they are able to determine which chip was the source of the interrupt. BUG=b:118846062 BRANCH=None TEST=performed several power swaps and unplugs on a pair of Careenas, verifying that in instances where the handler had to loop around we correctly cleared the interrupts and the "ectool usbpdpower" output was normal Change-Id: Iccbe40976a746d109d67b9a91f8fbd81898f9b3f Signed-off-by: Diana Z <dzigterman@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1327123 Reviewed-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* Delan: LED PWM Channel Changekoko2018-11-131-2/+2
| | | | | | | | | | | | | | | | | | | | | Changing Delan led channel amber to pwm channel 2 white to pwm channel 0 BUG=b:118418060 BRANCH=none TEST=test on delan by 1. ectool led command 2. ettool pwmsetduty command 3. led behavior in S0, charging/discharging mode Change-Id: Ie0d5b9bc994556271ec7ab971da528a60d0e31f3 Signed-off-by: koko <ko_ko@compal.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/1326283 Commit-Ready: Elmo Lan <elmo_lan@compal.corp-partner.google.com> Tested-by: Elmo Lan <elmo_lan@compal.corp-partner.google.com> Reviewed-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org> Reviewed-by: Elmo Lan <elmo_lan@compal.corp-partner.google.com>
* touchpad_st: update logical maximum of y valueWei-Han Chen2018-11-081-1/+1
| | | | | | | | | | | | | | | | | | | | | | To make X and Y have the same resolution (ratio between logical coordinate and physical coordinate), the logical maximum of y is changed to 1573. This change requires ST firmware v36.0 (0x24) or above. If this is used on older ST firmware, it will still work, but the Y movement will be scaled. BRANCH=nocturne BUG=b:118363768, b:119236031 TEST=make buildall -j64, test on whiskers Signed-off-by: Wei-Han Chen <stimim@chromium.org> Change-Id: Ic6c5db496c28a2f0febb8a4073d738cd9ba45087 Reviewed-on: https://chromium-review.googlesource.com/1297870 Commit-Ready: Wei-Han Chen <stimim@chromium.org> Tested-by: Wei-Han Chen <stimim@chromium.org> Reviewed-by: Tai-Hsu Lin <sheckylin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* Nami: Use display battery percentage to control LEDDaisuke Nojiri2018-11-081-20/+27
| | | | | | | | | | | | | | | | | | | | | | | Currently, remaining capacity read from a battery is converted first by ACPI and then by powerd. Without knowing the conversion, EC is not able to control LEDs synchronously to the number on the display. This patch makes Nami EC use display percentages to control LEDs. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=b:109954565,b:80270446 BRANCH=none TEST=Verify charge LED changes to white (full) on Sona synchronously to the display percentage. TEST=Verify charge LED changes to blinking white (low) on Sona within 30 seconds synchronously to the display percentage. Change-Id: I5d451a24bed3a136dee4d7ac27a57caf75fcb856 Reviewed-on: https://chromium-review.googlesource.com/1309035 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* Jerry: Remove keyboard console commandDaisuke Nojiri2018-11-081-0/+1
| | | | | | | | | | | | | | | | This patch removes keyboard console command to create space. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=none BRANCH=none TEST=build Change-Id: Ie662ef7cf5d02b815a04283c11e883db2f78edcb Reviewed-on: https://chromium-review.googlesource.com/1313476 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* cheza: Make USB mux handled by TCPC chips and HPD handled by APWai-Hong Tam2018-11-072-4/+83
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In Cheza design, the USB mux (switching USB lanes to DP and/or USB SS) is handled by TCPC chips and the HPD is handled by AP (DP PHY). The CL adds some custom drivers to override the get() function (Linux extcon driver uses it to check the USB mux and HPD IRQ) by checking the virtual driver and redirect the other functions to the TCPC drivers. BRANCH=none BUG=b:118898133 TEST=Manually added a new console command to issue a HPD IRQ. +static int command_hpd_irq(int argc, char **argv) +{ + char *e; + int port; + const struct usb_mux *mux; + + if (argc != 2) + return EC_ERROR_PARAM_COUNT; + + port = strtoi(argv[1], &e, 10); + if (*e || port >= CONFIG_USB_PD_PORT_COUNT) + return EC_ERROR_PARAM1; + + mux = &usb_muxes[port]; + mux->hpd_update(port, 0, 1); + return EC_SUCCESS; +} +DECLARE_CONSOLE_COMMAND(hpd_irq, command_hpd_irq, + "[port]", + "Issue a HPD IRQ"); In EC console, typed "hpd_irq 0" and checked the result on AP: localhost ~ # ectool usbpdmuxinfo 0 Port 0: USB DP HPD_IRQ Port 1: USB INV Checked it again and HPD_IRQ should be cleared. localhost ~ # ectool usbpdmuxinfo 0 Port 0: USB DP Port 1: USB INV Change-Id: I4ddc274a637393391dd654c9ee75de7646746ad5 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/1316370 Reviewed-by: Stephen Boyd <swboyd@chromium.org>
* cheza: Apply the fix to handle two or more HPD eventsWai-Hong Tam2018-11-071-5/+0
| | | | | | | | | | | | | | | | | | | | | Apply the following fix to Cheza: http://crrev.com/c/388737 Some Type-C to DP adapters generate two or more HPD events while others generate only one HPD event. Currently hotplugging only works with the former adapter. Now hotplugging is triggered on one or more HPD events. BRANCH=none BUG=b:118838389 TEST=Plugged and unplugged a USB-C hub with HDMI port to port-0. Plugged and unplugged a HDMI monitor cable to the above hub. Checked the "typec 0" command showing proper results. Change-Id: If03e3db049fb3ba4de0f52b5084fd0457e3703d5 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/1313473 Reviewed-by: Stephen Boyd <swboyd@chromium.org>
* cheza: Don't mux the DP lines until HPD level goes highWai-Hong Tam2018-11-071-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no dedicated GPIO in the SoC to HPD detection. To follow the previous design, the DP PHY should be powered on/off using the EXTCON_DISP_DP cable state. The EXTCON_DISP_DP cable state is set iff the DP mux is enabled. So EC should not enable the DP mux until the HPD level goes high. The hpd_update() is used for HPD_IRQ only. BRANCH=none BUG=b:118838389 TEST=Plugged a USB-C hub with HDMI port to port-0. Checked: > typec 0 Port C0: polarity:CC1 Superspeed USB1 TEST=Plugged a HDMI monitor cable to the above hub. Checked: > typec 0 Port C0: polarity:CC1 Superspeed DP1+USB1 TEST=Unplugged the HDMI monitor cable. Checked: > typec 0 Port C0: polarity:CC1 Superspeed USB1 TEST=Plugged a USB-C to HDMI dongle to port-0. Checked: > typec 0 Port C0: polarity:CC1 No Superspeed connection TEST=Plugged a HDMI monitor cable to the above dongle. Checked: > typec 0 Port C0: polarity:CC1 Superspeed DP1 TEST=Unplugged the HDMI monitor cable. Checked: > typec 0 Port C0: polarity:CC1 No Superspeed connection Change-Id: I9d3ac705913dd1829931def0e4c141da13fbc07c Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/1313472 Reviewed-by: Stephen Boyd <swboyd@chromium.org>
* Project Delan: Update Battery Parametersamsp_liu2018-11-072-18/+75
| | | | | | | | | | | | | | | | | | This patch makes EC configure battery parameters differently based on manufacturer name BUG=b:118141617 BRANCH=none TEST=1.Verify BYD/LGC/Simplo battery can be found via EC console. 2.Battery can be charged and discharged +-5%. 3.Key in "ectool batterycutoff",then waiting 10 seconds plug-in AC and press power boutton can boot into os. Change-Id: I93431b524d59b905eca0cb83e4638d95abf68433 Signed-off-by: samsp_liu <samsp_liu@compal.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/1295892 Commit-Ready: Jonathan Brandmeyer <jbrandmeyer@chromium.org> Tested-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org> Reviewed-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org>
* Liara: Update LED behaviorJosh Tsai2018-11-071-5/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | There is no power status indicator LED in customer UX spec, so LED only shows the charging status. The LEDs status defined as below a lookup table. Charging Amber on Full Charged White on Discharging Off Error Amber, 250 ms on / 250 ms off BUG=b:116081524 BRANCH=none TEST=manual 1. Check charge led Amber on when battery is charging. 2. Check charge led White on when battery is full. 3. Check charge led is off when battery is discharge. 4. Check charge led amber on 250ms off 250ms when battery off. Change-Id: Id3e1741b5cc88014ce169cb44229072c80e1bcc4 Signed-off-by: Josh Tsai <josh_tsai@compal.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/1285929 Reviewed-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org> Reviewed-by: Raymond Chou <raymond_chou@compal.corp-partner.google.com> Reviewed-by: Ruby Lee <ruby_lee@compal.corp-partner.google.com>
* Cr50: Add valid PCR value for pinweaverIgor2018-11-071-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to bind the PIN authentication to PCR4, required for additional security, a set of valid PCR criteria is added as metadata in the leaf of the tree. Each criteria has a bitmask of PCR indexes and the digest sha256 that should be obtained from concatenation of PCR values for the respective indexes. Pinweaver will handle both types of requests, in old and the new format. For migration of old leaves that don't have the new field, the process expects cryptohome to detect that the leaf needs migration based on protocol used, leaf version and if the list of PCR criteria is empty. In case the leaf needs migration, cryptohome should insert a new leaf with the same data and remove the old one. The PCR criteria set is created on Chrome OS side. Details of that implementation is in https://chromium-review.googlesource.com/c/chromiumos/platform2/+/1124856 BRANCH=none BUG=chromium:812165 TEST=sudo V=1 make run-pinweaver -j pinweaver_client selftest Deploy old image on a device and create an account setting a PIN code as well. Deploy the new image and new CR50 build. Login and check that the migration works well. Also try to put device to sleep and unlock. Check that a new credential creation with new version works as well and sleep + unlock work as expected. Extend PCR4 on device and check that login/unlock works only for the user which obfuscated_username was used to extend the PCR. Also check that authentication works with cases when old cryptohome and new pinweaver is deployed, or old pinweaver and new cryptohome. CQ-DEPEND=CL:1124856 Change-Id: If778c4e46b9945afadfd2af7d58353005624d668 Signed-off-by: igorcov@chromium.org Reviewed-on: https://chromium-review.googlesource.com/1112014 Commit-Ready: Igor <igorcov@chromium.org> Tested-by: Igor <igorcov@chromium.org> Reviewed-by: Igor <igorcov@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Andrey Pronin <apronin@chromium.org>
* kukui: Enable TCPC low power mode.Yilun Lin2018-11-071-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | BUG=b:113641776 BRANCH=None TEST=make BOARD=kukui -j TEST=Test plug/unplug pd charger that can do pd negiotiate. TEST=Test plug/unplug peripheral that can sink power. TEST=apshutdown; sleep 10 && dut-control -t 3 ppvar_batt_ma ppvar_sys_ma @@ NAME COUNT AVERAGE STDDEV MAX MIN @@ sample_msecs 1030 2.90 0.13 4.57 2.55 @@ ppvar_batt_ma 1030 14.05 0.52 22.00 14.00 @@ ppvar_sys_ma 1030 14.00 0.22 18.00 12.00 Check the difference of ppvar_batt_ma and ppvar_sys_ma is within 0.1 ma. That is, battery does not provide more power than the system required. Change-Id: I425fbb02f5698ea48c2f0160552026cdd1a0fab4 Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/1297097 Commit-Ready: Yilun Lin <yllin@chromium.org> Tested-by: Tony Lin <tonycwlin@google.com> Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* Apel: add battery configurationJames_Chao2018-11-072-0/+28
| | | | | | | | | | | | | | | | BUG=b:115502621 BRANCH=master TEST=Build success now. Check the battery is working after we got proto board and battery. Change-Id: Id207d807439b16474ebcf9567bcaa1e9ccd83c20 Signed-off-by: James_Chao <james_chao@asus.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/1312516 Commit-Ready: James Chao <james_chao@asus.corp-partner.google.com> Tested-by: James Chao <james_chao@asus.corp-partner.google.com> Reviewed-by: James Chao <james_chao@asus.corp-partner.google.com> Reviewed-by: Marco Chen <marcochen@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* bobba: enable sensors sync via dedicated IRQ pinEnrico Granata2018-11-072-3/+2
| | | | | | | | | | | | | | | | | | | | This commit sets up the EC on bobba to send AP sync for sensor events via a dedicated GPIO pin (EC_INT_L) instead of the ACPI notifier chain. This is done in the interest of optimizing the performance of the sensor ring running on the AP. BRANCH=none BUG=b:118443377, crbug:896347 TEST=observe sensor events come in on Linux, and watch /proc/interrupts to see chromeos-ec IRQ count go up CQ-DEPEND=CL:1318068 Change-Id: I4d8cd089691f39f8617b1613d618e6f273d5f1fc Signed-off-by: Enrico Granata <egranata@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1298699 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* cr50: enable ITE CCD programmingVadim Bendebury2018-11-053-0/+69
| | | | | | | | | | | | | | | | | | | | | | | | | This patch enables support of ITE EC programming by Cr50. ITE EC sync sequence generator implementation is being added to the image, I2C RX and TX queue sizes are increased to be able to accommodate messages sent during programming session. Board level callback function is provided to request ITE SYNC sequence generation on the next boot, and to reset the H1 with a 10 ms delay, necessary for CCD host USB communications to quiesce. Board startup code is modified to when requested invoke function generating ITE SYNC sequence early in the boot before jitter configuration is locked. BRANCH=cr50, cr50-mp BUG=b:75976718 TEST=with the rest of the patches applied verified that it is possible to disable and re-enable clock jitter at run time. Change-Id: I88367b200ceb5b62613f96061d565faa56f4d75a Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1263898 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* cheza: Correct the PSYS ADC multiplierWai-Hong Tam2018-11-021-3/+3
| | | | | | | | | | | | | | | | | | | The resistor on the PSYS output is actually 5.6K Ohm, instead of 12.4K Ohm. Correct the ADC multiplier to reflect the impedance value. The worst-case anaylsis: ADC multipler: 2816 * 124000 * 2 / (1023 + 1) = 682000 max ADC register value: 1023 (10-bit) upper bound: 1023 * 682000 < 2^30 BRANCH=none BUG=b:118343126 TEST=Checked the "adc" console command. Change-Id: I6c96c60f08c6f50b53fd69d3aa0ee8f86c069545 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/1309049 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* Kalista: Modify gpio settingsTino Liu2018-11-021-8/+13
| | | | | | | | | | | | | | | | | | | | | | | GPIO67: PP3300_USB_PD_EN should be output high initially. GPIOC2: BOARD_VERSION2 -> SPKR5 (no function) GPIOB1: USB5_ENABLE -> TP48 GPIOC3: AC_JACK_CHARGE -> TP52 GPIO44: TYPE_C_87W -> TP120 GPIO33: TYPE_C_60W -> TP121 GPIOC5: ADP_IN -> TP123 GPIO66: TP249 -> TP127 GPIOC4: BOARD_VERSION1 -> TP128 GPIO01: BOARD_VERSION3 -> TP129 BUG=b:111571989 BRANCH=none TEST=make buildall pass, Kalista can boot Change-Id: I0661eecfc24061462e86e1b7e5b379ec10b1e472 Signed-off-by: Tino Liu <tino.liu@quanta.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/1309559 Commit-Ready: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* cr50: Rename tpm_nvmem_read to tpm_nvmem_opsLouis Collard2018-11-024-6/+6
| | | | | | | | | | | | | A future CL will add non-read operations. TEST=build BRANCH=none BUG=b:112604850 Change-Id: Ie024e30b81dff888dcb42adcd4e3b2daded2f4f7 Signed-off-by: Louis Collard <louiscollard@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1312517 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* kukui: Enable gauge_interrupt.Yilun Lin2018-11-013-4/+31
| | | | | | | | | | | | | | | | | | | Kukui has a pin out from battery pack to MAX17055 to sense battery temperature. If the temp is over the limit, MAX17055 sends alert to trigger charger task in time to prevent a damaged battery. TEST=manually set temperature upper limit to 30 Celcius degree, and see that when the battery temperature reaches 30 C, GAUGE_INT_ODL is asserted, and charger_task is woken up. BUG=b:111378620 BRANCH=None Change-Id: Id0718e210c8082bb280c62545a5ec75b3db8c6c2 Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/1270403 Commit-Ready: Yilun Lin <yllin@chromium.org> Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* Bobba: Modify base accel/gyro rotation for SKU with AR Cam.Tino Liu2018-11-011-0/+28
| | | | | | | | | | | | | | | | | Sparky360 with SKU ID 26 has AR Cam, and move base accel/gryo to AR Cam board. AR Cam board has about -16 bias with motherboard through Y axis. Modify base accel/gyro rotation reference for SKU with AR Cam. BUG=b:118646061 BRANCH=none TEST=compile pass, `ectool motionsense lid_angle` shows correct, factory testing ScreenRotation & TabletRotationBaseAccel test passed Change-Id: Ie2c2d2faa9cd562f5807eb31b1fc92f3fc792e74 Signed-off-by: Tino Liu <tino.liu@quanta.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/1304156 Reviewed-by: Diana Z <dzigterman@chromium.org>
* rammus: Correct accel sensor BMI160 base reference dependent on sensor location.michael_chen2018-10-311-2/+2
| | | | | | | | | | | | | | | | | | | | Base on BMI160 location, the x axis is positive correlation and the y, z axis negative correlation. Correct the MB base reference direction. BUG=b:118362153 BRANCH=ToT TEST=Manual 1. Using EC console command "accelinfo on" the check the Base Accel x, y, z value. 2. Run factory tool to verify. Change-Id: I5c7968e9294b2fca511808d30aad3a99d524643f Signed-off-by: michael_chen <michael5_chen@pegatroncorp.com> Reviewed-on: https://chromium-review.googlesource.com/1307273 Commit-Ready: michael chen <michael5_chen@pegatroncorp.com> Tested-by: michael chen <michael5_chen@pegatroncorp.com> Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
* meep: fix sensor data and accel orientationDevin Lu2018-10-311-5/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fix the lid and base accel orientation for EVT and change range value to 2g. BUG=none BRANCH=none TEST=When device is laying on a table, lid angle at 180, both sensors report gravity along Z axis: ectool motionsense Motion sensing active Sensor 0: 507 606 16748 Sensor 1: 17 -334 16442 Sensor 2: 0 0 0 Sensor 3: 0 0 0 When on the base bottom edge, report gravity along Y axis: ectool motionsense Motion sensing active Sensor 0: 403 16491 655 Sensor 1: 19 16163 1540 Sensor 2: 0 0 0 Sensor 3: 0 0 0 When on its left side, report gravity along X axis: ectool motionsense Motion sensing active Sensor 0: 16172 -374 1738 Sensor 1: 16315 -184 1280 Sensor 2: 0 0 0 Sensor 3: 0 0 0 and check the screen rotation was normally. Change-Id: Ic594c12fa4b03b594151eed4ffb0f0e5b42cad3d Signed-off-by: Devin Lu <Devin.Lu@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/1307282 Reviewed-by: Justin TerAvest <teravest@chromium.org>
* meep: enable keyboard factory scanningDevin Lu2018-10-312-0/+25
| | | | | | | | | | | | | This patch add for factory keyboard connector test. BUG=none BRANCH=none TEST=Short keyboard pins and make sure "ectool kbfactorytest" works. Change-Id: Ic343b99343f5f6d7a8967bf1c4bec642638d8568 Signed-off-by: Devin Lu <Devin.Lu@quantatw.com> Reviewed-on: https://chromium-review.googlesource.com/1309572 Reviewed-by: Justin TerAvest <teravest@chromium.org>
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