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* Nami: Control LED for AkaliDaisuke Nojiri2018-04-252-27/+69
| | | | | | | | | | | | | | | | | | | This patch adds LED control for Akali. Akali needs to show an irregular pattern in S3 (On 1 sec off 3 sec). This patch adds 'alternate' mode support. It allows an LED to extend off period. In alternate mode, an LED goes through on-off-off-off cycles. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=b:77827579 BRANCH=none TEST=Verify on Nami. Change-Id: Ia7541236a6c598173cb94089224ac8c0a3f63a68 Reviewed-on: https://chromium-review.googlesource.com/1024691 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Sona: Blink LED when battery is lowDaisuke Nojiri2018-04-251-1/+11
| | | | | | | | | | | | | | | | | This patch makes the battery LED on Sona blink in white when the state of charge is below 10%. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=b:74940319 BRANCH=none TEST=Verify battery LED blinks when soc is below 10%. Change-Id: Iee731a63787496ac15d97555564c8b02e1923256 Reviewed-on: https://chromium-review.googlesource.com/1020660 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* servo_v4: Remove `crash` command.Aseda Aboagye2018-04-251-0/+1
| | | | | | | | | | | | | | | Servo V4 is out of space, so remove the crash command to gain some back. BUG=None BRANCH=None TEST=make -j buildall Change-Id: I9e5617de2a41f12f60d1fab246acddbbcfa3bea2 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/1022964 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Nick Sanders <nsanders@chromium.org>
* samus_pd: Enable Link-Time Optimizations.Aseda Aboagye2018-04-251-0/+1
| | | | | | | | | | | | | | BUG=None BRANCH=None TEST=`make -j BOARD=samus` succeeds. TEST=samus_pd is able to boot up and negotiate correctly with zinger. Change-Id: I422be2772df3436bb398ffd3e58096039efcbebe Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/998828 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* kevin: Remove 'pwr_avg' command.Aseda Aboagye2018-04-251-0/+1
| | | | | | | | | | | | | | | Kevin is out of space, so disable this console command to get some back. BUG=None BRANCH=None TEST=make -j buildall Change-Id: Ic24b83187067e16ca438f31250c4272580f1e34f Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/922322 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* samus_pd: Remove `crash` command.Aseda Aboagye2018-04-251-0/+1
| | | | | | | | | | | | | | | | | | samus_pd is out of space again (groundhogday.jpg). Remove the `crash` command. This command is needed for a FAFT test (firmware_ECSharedMem) and you cannot qualify a firmware without it. However, for samus_pd, we don't seem to run this test against samus_pd itself, but just samus. BUG=None BRANCH=None TEST=make -j buildall Change-Id: I7e34a1a7a9fcdd36e1d97b1226b66dc3f25213f0 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/917012 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* wheatley: Enable CONFIG_COMMON_GPIO_SHORTNAMES.Aseda Aboagye2018-04-251-0/+2
| | | | | | | | | | | | | | | | | Wheatley needs more space (probably to store his book collection including works of Machiavelli). Therefore, enable CONFIG_COMMON_GPIO_SHORTNAMES to save space. BUG=None BRANCH=None TEST=make -j buildall Change-Id: Ia5dc8d36c9ae8dea6272a28677609f229a835f96 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/917011 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@google.com>
* board/yorp: fix PMIC_EN gpioAaron Durbin2018-04-251-1/+1
| | | | | | | | | | | | | | | | | | | | | | Apparently the symbol in the yorp schematic is incorrect for our part. The PMIC_EN signal on ball H6 is actually GPIO72 -- not GPIOD7. Adjust the gpio used for PMIC_EN. Note: GPIO72 needs to be put in gpio mode since it defaults to PWRGD functionality. However, gpio_pre_init() in chip/npcx/gpio.c enables gpio functionality by default. If that changes, the board options will need to change as well. BUG=b:78352179 TEST=Built. Booted. PMIC_EN goes up and down as expected. BRANCH=none Change-Id: I955f9a24e0fbecb0cda1380c237fa44c9a575e45 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1026375 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
* board/yorp: set the correct chip variantAaron Durbin2018-04-251-1/+1
| | | | | | | | | | | | | | | | | The yorp build is using part NPCX796FB0BX which evidently maps to npcx7m6xb. Therefore, set the correct variant to reflect reality. BUG=b:78352179 TEST=Built. Booted. BRANCH=none Change-Id: I3835b4664429c360ea946aad0a7bf3dc32f6eea1 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1024608 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
* bip: set correct AC_PRESENT debouce delayJett Rink2018-04-241-1/+6
| | | | | | | | | | | | BRANCH=none BUG=b:75974377 TEST=none Change-Id: Ib6fcc0ac7668614a487525196ea4f3a5f399c640 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1024278 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
* bip: add cbi board versionJett Rink2018-04-242-1/+4
| | | | | | | | | | | BRANCH=none BUG=b:78473271 TEST=none Change-Id: Ic7b500ed33b884c59036c41b9ce3e7925637ee69 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1024962 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* bip: use ITE as TCPC driver for C1Jett Rink2018-04-242-17/+19
| | | | | | | | | | | | | | The PS8751 is only being used as mux with the option of being a TCPC is we stuff resistor on the subboard. The default resistor configuration uses ITE EC as C1 TCPC. BRANCH=NONE BUG=b:78341944 TEST=none Change-Id: I4ccad314fa7eec0d205a155e42e52109cff5811f Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1024487
* yorp: Enable temperature sensorsDivya Sasidharan2018-04-243-3/+105
| | | | | | | | | | | | | BUG=b:77944804 BRANCH=None TEST=On yorp; test adc values, verify they are valid. Change-Id: I64191f33c594d8869391bab813902f59a63d2ea1 Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1018118 Commit-Ready: Divya Sasidharan <divya.s.sasidharan@intel.corp-partner.google.com> Tested-by: Divya Sasidharan <divya.s.sasidharan@intel.corp-partner.google.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* hammer: Disable side-band wake using detection pinNicolas Boichat2018-04-231-24/+0
| | | | | | | | | | | | | | | | | Side-band wake was only useful when the lid would go in deep-S3, where the USB interface is disabled. Since we are using S0ix on poppy and derivatives, the side band wake is useless, and, in some rare case, may actually cause issues. BRANCH=poppy BUG=b:77828249 TEST=Flash staff, can wake soraka from suspend, or from USB autosuspend. Change-Id: I23398a792157b32a5d79505dcffc92aaffd4fec2 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1011523 Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* Nami: Disable ALS for Pantheontoobest542018-04-231-2/+3
| | | | | | | | | | | | | | Use OEM ID to update motion_sensor_count to disable ALS for Pantheon. BUG=b:77937854 BRANCH=none TEST=Change oem id for Pantheon then to check the ALS was disabled. Change-Id: I4cb2ad16f3413a65b6f2df84eae2d1ced37b72f6 Signed-off-by: Raymond Chou <raymond_chou@compal.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/1010182 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Carter Sung <carter_sung@compal.corp-partner.google.com>
* meowth_fp: enable PCH interface in S0Vincent Palatin2018-04-222-6/+35
| | | | | | | | | | | | | | | | | | | | Enabling the SPI slave interface and the host interface depending on the detected PCH power state. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=b:71986991 TEST=On Meowth, check that the MCU interrupt is seen on the CPU side and we can still send host commands. TEST=On ZerbleBarn, verify that the SPI slave interface is enabled at startup. Change-Id: Ie7b22e69178bc7d34be6ab28ab24db82fefd5a02 Reviewed-on: https://chromium-review.googlesource.com/966023 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* meowth: Only power base when AP is on.Aseda Aboagye2018-04-201-16/+46
| | | | | | | | | | | | | | | | | | | | | | | | | Previously, the base power was enabled when the base was detected by the lid. However, we should only power the base when the AP is on since it just wastes power otherwise. This commit adds a pair of chipset hooks to kick the state machine on startup and disable it on shutdown. BUG=None BRANCH=None TEST=Flash meowth, attach base with AP off, verify that base power is not enabled. TEST=Remove base and attach base, verify that base power is disabled when removed and enabled when attached. TEST=Shut AP down, verify that base power is disabled. TEST=Remove base and attach base, verify that base power remains disabled. TEST=Power on AP with base detached, verify that base power remains off. Change-Id: I4379789987dbe91c72d699c4d184b5c5cc812e5f Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/1020525 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* atlas: update GPIO names to match new schematicsCaveh Jalali2018-04-202-15/+15
| | | | | | | | | | | | | | | | | | the latest schematics have been updated to reflect the I2C bus numbering used in the chip datasheets. this updates the software to be consistent with the new datasheets. this is only a renaming exercise, there are no physical changes to the board. BUG=b:75070158,b:78309559 BRANCH=none TEST=it compiles Change-Id: I16e6741c2e8a1dcc32b814a50ba12739f36fd8cf Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1020721 Commit-Ready: Caveh Jalali <caveh@google.com> Tested-by: caveh jalali <caveh@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* Sona: Blink LED on battery errorDaisuke Nojiri2018-04-201-13/+20
| | | | | | | | | | | | | | | | | | | | | This patch makes the battery LED blink at 0.5 sec interval in white when battery error is detected. This patch also changes the pulse interval resolution from 1 sec to 100 msec. There is no functionality change. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=b:74940319 BRANCH=none TEST=Verify pulsing and blinking are not affected. Verify battery LED blinks as intended on Sona. Change-Id: I0767a6004861b9f07bc846d2ba5bf0df9067a748 Reviewed-on: https://chromium-review.googlesource.com/1017305 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* yorp: Fix force mode base accel configDivya Sasidharan2018-04-202-5/+7
| | | | | | | | | | | | | | | | Accel data read was (0, 0) without this change. BUG=b:74602071 BRANCH=None TEST=On yorp; on EC console test accelinfo on -> gives accel data Change-Id: I08073cccb2108b5d2189be5aa27a77adfae7677a Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1015974 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Divya S Sasidharan <divya.s.sasidharan@intel.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* grunt: Send sensor MKBP events using host eventEdward Hill2018-04-191-0/+10
| | | | | | | | | | | | | | Add CONFIG_MKBP_EVENT and CONFIG_MKBP_USE_HOST_EVENT to send sensor events to AP. BUG=b:77342604 BRANCH=none TEST=view sensors in AIDA64 Android app in ARC++ Change-Id: I3687072903d251bccb2cdf7670b0780a906dd22d Signed-off-by: Edward Hill <ecgh@chromium.org> Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1012457
* stoney: Use chipset_pre_init callbackFurquan Shaikh2018-04-191-7/+0
| | | | | | | | | | | | | | | | Similar to intel_x86, move chipset stoney to using chipset_pre_init callback. BUG=None BRANCH=None TEST=make -j buildall Change-Id: I995bbda01ec78ecd28c302f269cf15739913ecd9 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1018738 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* APL/GLK: Move chipset shutdown to chipset taskFurquan Shaikh2018-04-191-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | In order to ensure that all chipset init/shutdown operations happen within the context of chipset task for APL/GLK: 1. Update chipset_force_shutdown to only set a flag force_shutdown to indicate that chipset shutdown is requested and wake the chipset task. 2. Make chipset task (within the power state machine) call internal_chipset_shutdown. 3. Make internal_chipset_shutdown reset force_shutdown flag and make a callback to weak function chipset_do_shutdown to trigger chipset shutdown. BUG=b:78259506 BRANCH=None TEST=Verified that "apshutdown" on EC console results in chipset shutdown action being taken within chipset task. Change-Id: If13b65ae47e3dce2e466320cc14c68239563f6ed Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1018737 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* fizz/nami: Use chipset_pre_init_callbackFurquan Shaikh2018-04-194-4/+4
| | | | | | | | | | | | | | | | This change updates fizz/nami boards to use chipset_pre_init_callback instead of hook. BUG=b:78259506 BRANCH=None TEST=make -j buildall Change-Id: Ib09c033c2f0c2c3d324c90776f7bbd8365a71f52 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1018735 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* APL/GLK boards: Use chipset_pre_init_callbackFurquan Shaikh2018-04-197-16/+12
| | | | | | | | | | | | | | | | This change updates all APL/GLK boards to use chipset_pre_init_callback instead of hook. BUG=b:78259506 BRANCH=None TEST=Verified that yorp still boots. Change-Id: I71ab0f1111e89a254db83fc58abfdfe8eacd3575 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1018734 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* system: update board version to return an error if encounteredJett Rink2018-04-1931-51/+36
| | | | | | | | | | | | | | | | | | | | Now that board version can come from CBI, we can have a real error reading it. We should pass that error to the console or to the AP on the host command and let the AP firmware (or user) decided how to handle that error case Also update the CONFIG_BOARD_VERSION to be derived instead of needed in most cases. BRANCH=none BUG=b:77972120 TEST=Error reported on EC console and AP console when CBI is invalid on yorp Change-Id: Ib8d80f610ea226265a61e68b61965150cdc9bb04 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1015776 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* Nami: Control LEDs for Nami/Vayne/SonaDaisuke Nojiri2018-04-184-101/+360
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Nami/Vayne uses a dual color LED to show power/charge status as follows: Charging Amber on (S0/S3/S5) Charging (full) White on (S0/S3/S5) Discharge in S0 White on Discharge in S3/S0ix Pulsing (rising for 2 sec , falling for 2 sec) Discharge in S5 Off Battery Error Amber on 1sec off 1sec Sona - Battery LED (dual color) AC is attached Solid ON White charging Solid ON Amber Discharge in S0 Off Battery Error Blinking white (0.5 sec On and 0.5 sec Off) Discharge in S3 Blinking white (1 sec On, 1 sec off regardless AC status) fuel < 10% Blinking white (1 sec On, 1 sec Off) Sona - Power LED (single color) System S0 Soliid On System S3 1 second on, 1 second off System S4/S5 Off Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=b:74940319,b:77941051,b:73999799 BRANCH=none TEST=Verify LED behaviors in S3, S0, charge, discharge on Nami and Sona Change-Id: I55b40742135a49f48044f561eb2dbd82b5556d07 Reviewed-on: https://chromium-review.googlesource.com/1011293 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* cheza: Lower the I2C speeds on TCPC buses to 400kHzWai-Hong Tam2018-04-171-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The initial I2C operating speed of the port-0 TCPC chip is 400kHz. It requires changing a register addr:0x48 to a value 0x03 to increase its speed to 1MHz. The BC1.2 chips on port-0 and port-1 also operate at 400kHz, according to the datasheet. So lower the I2C speeds on two TCPC buses to 400kHz. BRANCH=none BUG=b:78142256 TEST=Use console to enable TPCP power and check I2C communication: > gpioset EN_USB_C0_TCPC_PWR 1 > gpioset USB_C0_PD_RST_R_L 1 > i2cscan 1 Scanning 1 tcpc0...................................... 0x4a... 0x50........................ 0x80............................................................... > i2cxfer r 1 0x50 0x00 0xaa [170] Change-Id: I665136d738de50db8beeed338e3102fb5ca6fc84 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/1015763 Reviewed-by: Alexandru M Stan <amstan@chromium.org>
* yorp: do not wait for 5V rail to go downJett Rink2018-04-171-2/+5
| | | | | | | | | | | | | | After using joint 5V rail code (CONFIG_POWER_PP5000_CONTROL) we cannot wait for the 5V rail to go down because another task may be using it. BRANCH=none BUG=b:78188213 TEST=apshutdown on yorp no longer watchdog resets Change-Id: Ibc7e3eb2f7b3271fccd6ef0d92cce156c20bd688 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1015845 Reviewed-by: Justin TerAvest <teravest@chromium.org>
* cheza: Add initial support for ChezaWai-Hong Tam2018-04-175-0/+311
| | | | | | | | | | | | | | | | Add initial support, like UART, GPIO, I2C, buttons, etc. Add some hacks for early bring-up. BRANCH=none BUG=b:74395451 TEST=BOARD=cheza make TEST=Flashed the EC image to cheza. Verified AP power-on, booting coreboot/depthcharge with UART, and then booting kernel from USB. Change-Id: Id057abb491553bbffd3c57a6f48187ac2f2ff9a6 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/969420 Reviewed-by: Alexandru M Stan <amstan@chromium.org>
* yorp: increase TCPC i2c bus speedJett Rink2018-04-171-3/+2
| | | | | | | | | | | | BRANCH=none BUG=b:74387239 TEST=i2cscan and USB-C ports still connect on yorp Change-Id: Ic76549d6f81536cf02e1aa858a95e67eb528bccd Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1014704 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
* yorp: Keep 5V rail high on jump to RWJustin TerAvest2018-04-172-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | The BQ24392 driver controls power on the PP5000_A rail so that BC1.2 detection can be performed when the AP is off. However, that rail is also controlled by the chipset task, so CONFIG_POWER_PP5000_CONTROL needs to be defined to keep 5V rail up when necessary. Calls to power_5v_enable() must only be done when the build has a chipset task (otherwise, that function is not defined). BRANCH=none BUG=b:77874283 TEST=Booted Yorp with software sync enabled Signed-off-by: Justin TerAvest <teravest@chromium.org> Change-Id: Ib75655944aa05e381da922da8e916dc5d4dd9f85 Reviewed-on: https://chromium-review.googlesource.com/1014397 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Divya S Sasidharan <divya.s.sasidharan@intel.com> Reviewed-by: Divya S Sasidharan <divya.s.sasidharan@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* cr50: add s3 term for rk3399 devicesMary Ruthven2018-04-161-1/+2
| | | | | | | | | | | | | BUG=b:62200096 BRANCH=cr50 TEST=run suspend/resume tests on bob Change-Id: Idb249125f5967f6f9c80afbf991998425f9f5005 Signed-off-by: Mary Ruthven <mruthven@google.com> Reviewed-on: https://chromium-review.googlesource.com/991339 Commit-Ready: Mary Ruthven <mruthven@chromium.org> Tested-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* glkrvp_ite: Initial bring-up codeVijay Hiremath2018-04-148-0/+1379
| | | | | | | | | | | | | | | | Initial bring-up code for GLKRVP using ITE8320 MECC. BUG=b:77798195 BRANCH=none TEST=Able to boot to OS with host communication disabled Coreboot image. Change-Id: Iad0e22c9e7ef1c36889ef5e7f7e3f5a121f234e1 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1003766 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* cr50: add support for enabling terminations on ap suspendMary Ruthven2018-04-137-1/+124
| | | | | | | | | | | | | | | | | | | | | | | | | rk3399 systems need terminations on the SPI signals in S3 and all other low power states. Add support for enabling the pulldowns and pullups on the correct pins. With this change, if BOARD_NEEDS_S3_TERM is set in the board properties, cr50 will enable a pulldown on the AP TX Cr50 RX signal and a pulldown on all of the SPS signals. To keep the pulldowns from interfering with the sps peripheral, s3_term will also disable the input for those signals. BUG=b:62200096 BRANCH=cr50 TEST=Flash onto bob. Make sure cr50 enables and disables terminations when the AP suspends/resumes. Flash onto reef. Make sure it doesn't do anything. Change-Id: I4adaf6d66160bab1eb3cf3d343d4a79524ccf883 Signed-off-by: Mary Ruthven <mruthven@google.com> Reviewed-on: https://chromium-review.googlesource.com/991338 Commit-Ready: Mary Ruthven <mruthven@chromium.org> Tested-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* poppy: Prevent base detection from falling into reverse detection trapNicolas Boichat2018-04-131-12/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The problem here is that both normal detection range (120-300mV) and reverse connection detection range (450-500mV) are on the same side of the interrupt pin TTL level. So if we accidentally sample the ADC at the wrong time (either on connection, or after a side-band wake signal from base), we may fall into a trap where we assume that the base is connected in reverse, while the value may just be a transient. We have seen this case in the field, due to side-band wake pulse from base EC, but this could potentially happen on attach as well. The code debounces the reverse detection signal a little longer (this has no impact as the base is not functional anyway), so that we only consider that the base is connected in reverse if the ADC value is within the range twice in a row. BRANCH=poppy BUG=b:77828249 TEST=With HACK CL to emulate bug: - Press a few keys, hammer gets disconnected - Connect/disconnect hammer a few times, sometimes it does not get disconnected. TEST=Base connection, normal and reverse, still works properly. Change-Id: I2ccb911472dd591146e3b0e68400c8bd55368dba Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1010044 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* Nami: Enable Analogix USB-C portDaisuke Nojiri2018-04-135-23/+25
| | | | | | | | | | | | | | | Auto-toggling is currently disabled due to b/77544959. BUG=b:73793947 CQ-DEPEND=CL:988414 BRANCH=none TEST=Boot Nami. Verify PD power is negotiated and bettery is charged with a Zinger through the Analogix port. Change-Id: Ie817883027eb8623a8115aa8194fe4df50c3ce72 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/969989 Reviewed-by: Scott Collyer <scollyer@chromium.org>
* yorp: use cbi for board versionJett Rink2018-04-133-87/+3
| | | | | | | | | | | | | | | | | | | | | Replace ADC-based board version with CBI/EEPROM board version. This will cause all of the existing boards to report -1 (or 65535) as their board version until you can update it from the kernel. To set your board version to 0 run the following command in the AP console when WP if off (e.g. battery removed) $ ectool cbi set 0 0 1 2 BRANCH=none BUG=b:77551185,b:77900842 TEST=wrote to cbi from ap console and verify flash state on ap and ec console Change-Id: I03987cc89ca4c14580dcf61de23780fe5304663b Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1008832 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* yorp: Add support for Sanyo batteryScott Collyer2018-04-131-0/+29
| | | | | | | | | | | | | | | | | | Currently we only support the Acer LG and Panasonic battery. There is a 3rd Acer battery type that Quanta could be providing us with for Yorp proto boards. This CL adds support for the Sanyo battery. BUG=b:74132235 BRANCH=none TEST=verifed that when connected to Sanyo battery that the battery is reported as present. Change-Id: I1810da59866795e93340163216412441be098795 Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/1011557 Commit-Ready: Jett Rink <jettrink@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* anx7447: Add functions to the anx7447 driver to check/erase OCM flashScott Collyer2018-04-131-0/+1
| | | | | | | | | | | | | | | | | | | | | This CL adds support to check if the OCM flash is erased and if not, will erase it at initialization time. These changes are encapsulated in a new config option CONFIG_USB_PD_TCPM_ANX7447_OCM_ERASE and this option is enabled for Yorp boards. BUG=b:77658388 BRANCH=NONE TEST=make -j buildall. Tested on a board that hadn't yet been erased. Verifed the message "anx7447: OCM flash checked and successfully erased" was in the EC log, but did not show up on subsequent reboots. Change-Id: I660e76a9498d3dc1ba821a04317b324f716c5089 Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/988414 Commit-Ready: Jett Rink <jettrink@chromium.org> Tested-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* Documentation for CCD and servo_microstabilize-10575.58.Bstabilize-10575.54.Brelease-R67-10575.BMark Hayter2018-04-133-0/+176
| | | | | | | | | | | | | | | | | | | | Add markdown documentation (from reviewed doc) for the Servo Micro as an example of CCD. Tested with emacs markdown preview (markdown package) which is almost the same as gitiles. BUG=none BRANCH=none TEST=emacs markdown preview Signed-off-by: Mark Hayter <mdhayter@chromium.org> Change-Id: Ic5877a3b80313089ab9c79e376b4ee1f58e573eb Reviewed-on: https://chromium-review.googlesource.com/996893 Commit-Ready: Mark Hayter <mdhayter@chromium.org> Tested-by: Mark Hayter <mdhayter@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Nick Sanders <nsanders@chromium.org>
* cleanup: it83xx: pull pnpcfg_settings[] to the chip-levelDino Li2018-04-123-273/+0
| | | | | | | | | | | | | | | | | With this change, we don't need to declare pnpcfg_settings[] for each it83xx based board. BUG=b:76022972 BRANCH=none TEST=make buildall -j, boot to kernel on reef_it8320. Change-Id: I39eb465ba7d6191dce4ab1a39787a2c925ec3b91 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/1009544 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* atlas: manage USB-C high speed muxesstabilize-10569.BCaveh Jalali2018-04-122-0/+23
| | | | | | | | | | | | | | | | | | this adds control over the USB high speed muxes as a function of DP HPD. this allows an external monitor to be added/removed with chromeos extending the display as appropriate. BUG=b:77151172 BRANCH=none TEST=chromeos detects external monitor plugin and extends display Change-Id: I7df7a8136ddaa4eeaca800d29b46350dafd8f838 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1009208 Commit-Ready: Caveh Jalali <caveh@google.com> Tested-by: Caveh Jalali <caveh@google.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@google.com>
* yorp: Configure CONFIG_EXTPOWER_DEBOUNCE_MSDivya Sasidharan2018-04-111-1/+6
| | | | | | | | | | | | | | | | | | | | Without this configuration defined the board assumes battery only mode for G3->S5 boot up power sequence and thereby waits for power button press. BUG=b:76230069;b:75974377 BRANCH=None TEST=On yorp, with battery and external power connected reboot on EC console boot the SoC to S0. Verify on both ports. Change-Id: I837b7f99bd3c238ce74e394c773169d703ad9392 Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1008247 Commit-Ready: Aaron Durbin <adurbin@chromium.org> Tested-by: Divya S Sasidharan <divya.s.sasidharan@intel.com> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* yorp: Disable config for DRP_AUTO_TOGGLEDivya Sasidharan2018-04-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | | Since there are known issues with ANX7447 driver to work reliably in low power mode, disable DRP_AUTO_TOGGLE option since TCPC_LOW_POWER mode config and this one should be disabled together. BUG=b:77544959 BRANCH=None TEST=On yorp; on port 0 and 1 test without and with battery boots up. Please note with battery we may still need to press power button to get the SoC to boot up to S0 b:76230069. Detaching the Type-C charger with battery connected also shuts down the system which is a known failure b:77606986. Change-Id: I1b744cd9aa063328845f9a1cc7e36d291dfec9f5 Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1007629 Commit-Ready: Divya S Sasidharan <divya.s.sasidharan@intel.com> Tested-by: Divya S Sasidharan <divya.s.sasidharan@intel.com> Reviewed-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* poppy: Move PMIC init to a deferred functionNicolas Boichat2018-04-111-1/+4
| | | | | | | | | | | | | | | | | Instead of doing I2C traffic in an init hook, move it to a deferred function to be called outside of INIT_HOOK processing. (identical to CL:1001474 on eve branch, moved to poppy board file) BUG=b:77336348 BRANCH=poppy TEST=while true ; do ectool reboot_ec RO ; ectool reboot_ec RW ; done for 24 hours Change-Id: Icd9c2096ca026da6308b74582144886b30ea965f Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1003436 Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* Nami: Disable ALS for Sonaraymondchou2018-04-101-1/+1
| | | | | | | | | | | | | | | | Use OEM ID to update motion_sensor_count to disable ALS for Sona. BUG=b:77185923 BRANCH=none TEST=Change oem id for Sona then to check the ALS was disabled. Change-Id: I25714d0a2d2c0f4e9855a70fcb12cb9e65bae9f8 Signed-off-by: raymondchou <raymond_chou@compal.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/986034 Commit-Ready: Raymond Chou <raymond_chou@compal.corp-partner.google.com> Tested-by: Raymond Chou <raymond_chou@compal.corp-partner.google.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: stanley zhong <stanley_zhong@compal.corp-partner.google.com>
* cr50:usb_spi: add Cheza EC supportMary Ruthven2018-04-101-4/+11
| | | | | | | | | | | | | | | | | | | The Cheza EC requires EC_RX_H1_TX be held low while the EC is being reset to enter gang mode. This change adds another programming mode to ec usb spi programming to do that. BUG=b:74388083 BRANCH=cr50 TEST=The cheza boards aren't in, so I just tested EC_TX_CR50_RX_OUT gpioset EC_TX_OUT 0 and 1 setup EC_TX_CR50_RX_OUT correctly as an output when asserted and an input when deasserted. Change-Id: I7fc9cba954f2af5a841f00ce5bf8a27251b33bbe Signed-off-by: Mary Ruthven <mruthven@google.com> Reviewed-on: https://chromium-review.googlesource.com/1003529 Commit-Ready: Mary Ruthven <mruthven@chromium.org> Tested-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* chgstv2: Check charger power in prevent_power_on.Aseda Aboagye2018-04-102-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | charge_prevent_power_on() had sections which were gated on the following CONFIG_* option: CONFIG_CHARGER_LIMIT_POWER_THRESH_BAT_PCT However, the block of code that this gated didn't even take the battery percentage into account and made it very confusing as to why. This commit simply changes the CONFIG_* option used to gate to be the following: CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON This better reflects the checks that were actually being made. Additionally, this CONFIG_* option is defined by default for boards that have a chipset task and is initialized to 15W, which is the power that indicates that the charger is likely to speak USB PD. BUG=b:76174140 BRANCH=None TEST=make -j buildall Change-Id: Ic9158dd7109ce6082c6d00157ff266842363b295 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/977431 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org>
* yorp: Enable DP alternate modeDivya Sasidharan2018-04-102-6/+26
| | | | | | | | | | | | | | | | | | | This code enables alternate mode path for DP for both TypeC ports. BUG=b:77496487 BRANCH=None TEST=On yorp; check if the mux is set correctly for DP use cases. When PD message for hot plug is received by EC, EC (write register) ---> TCPC (GPIO) ---> SoC, and display comes up with both ports. Change-Id: Idfd0f85dc02a04adb266f2755a6d68dcb20141f8 Signed-off-by: Divya Sasidharan <divya.s.sasidharan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/1003330 Commit-Ready: Divya S Sasidharan <divya.s.sasidharan@intel.com> Tested-by: Divya S Sasidharan <divya.s.sasidharan@intel.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
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