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* brya: Limit IMVP9 tuning to board ID 1Caveh Jalali2021-05-271-0/+3
| | | | | | | | | | | | | | | | We introduced tuning values for the IMVP9 PMIC for board ID 1 to improve stability. More recent boards should have the desired values pre-programmed, so we do not need to apply tuning parameters. BRANCH=none BUG=b:188945301,b:185275955 TEST=boots on board ID 1 Change-Id: I9b6967a43f6d5c8b37bc3a7344347c278bdf698a Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2922002 Reviewed-by: Boris Mittelberg <bmbm@google.com> Commit-Queue: Boris Mittelberg <bmbm@google.com>
* Test: Make host calls for power supply mockableDiana Z2021-05-271-2/+2
| | | | | | | | | | | | | | Add test_mockable for power supply ready and reset so tests may detect when Vbus is applied and removed. BRANCH=None BUG=b:153071799 TEST=make -j buildall Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: I43d8d3cc5107b4e94338850fa807ae0eedc6d4b5 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2921282 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
* brya: Set hibernate wake sources polarityCaveh Jalali2021-05-271-5/+6
| | | | | | | | | | | | | | | | | This sets the wake source polarity on GPIOs we use as wake sources. LID_OPEN and ACOK are active high while the GSC_EC_PWR_BTN_ODL is active low. BRANCH=none BUG=b:183452273 TEST=booted on brya board ID 1 Change-Id: I13fded03bbe3f40ed9699f6e8c32e7532c87bc41 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2921292 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: CH Lin <chlin56@nuvoton.com> Commit-Queue: Furquan Shaikh <furquan@chromium.org>
* base_state: implement basestate host commandTing Shen2021-05-276-18/+18
| | | | | | | | | | | | | | | | | | | | | This CL introduces an unified method to force base attach/detach, to deprecate the hard-coded gpio pin name table in hammerd/hammertests/common.py. Also modifies base_force_state to use the same parameter type as host command. BUG=b:188625010 TEST=manually, run `ectool basestate attach|detach|reset` on coachz BRANCH=trogdor,kukui Signed-off-by: Ting Shen <phoenixshen@google.com> Change-Id: I5235661727cbbd15015c49d588ec70605e4a33e8 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2910472 Reviewed-by: Wai-Hong Tam <waihong@google.com> Tested-by: Ting Shen <phoenixshen@chromium.org> Commit-Queue: Ting Shen <phoenixshen@chromium.org>
* volteer: Remove console help commandAbe Levkoy2021-05-271-0/+3
| | | | | | | | | | | | | | Save 5268 B of flash on volteer_apmodeentry and 5268 B on volteer. BUG=b:189363246 TEST=make buildall BRANCH=firmware-volteer-13672.B-main Signed-off-by: Abe Levkoy <alevkoy@chromium.org> Change-Id: I30a21260f7692be3288712b02625acd968994c60 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2920636 Reviewed-by: Scott Collyer <scollyer@chromium.org> Commit-Queue: Scott Collyer <scollyer@chromium.org>
* cret: add Power LED behaviorjohnwc_yeh2021-05-274-77/+67
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add Battery control for Cret. Power LED: System S0: White System S0ix: Blinking white (1 sec on, 1 sec off) System S5/G3: Off. Battery LED: DC mode: System S0: off. System S5/G3: Off. System battery low: Blinking Amber (1 sec on, 1 sec off). AC mode: Charging: Amber. Full charged: White. Battery low or AC only: Blinking Amber (1 sec on, 1 sec off). BUG=b:188900681 BRANCH=dedede TEST=test on cret ，battery 、 Power LEDs are work. Signed-off-by: johnwc_yeh <johnwc_yeh@compal.corp-partner.google.com> Change-Id: I184753a738576772e37baa37e0484e9cd9834b7b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2919152 Reviewed-by: Elthan Huang <elthan_huang@compal.corp-partner.google.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Elthan Huang <elthan_huang@compal.corp-partner.google.com> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* brya: Board ID 1: Handle BATT_PRES reassignmentCaveh Jalali2021-05-272-6/+27
| | | | | | | | | | | | | | | | | | We are transitioning GPIO definitions to be correct for board ID 2. In order to support board ID 1 with the same EC image, some GPIOs need to be reconfigured to their legacy settings at runtime when board ID 1 is detected. For board ID 2, the battery presence detect GPIO has moved to the previous keyboard backlight enable pin. BRANCH=none BUG=b:183452273 TEST=booted on brya board ID 1, check battery present status on ID_1_EC_BATT_PRES_ODL. Cq-Depend: chromium:2914207 Change-Id: Ibae2a5e1f43c83360535e0d60c2a343bf9ef2421 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2916413
* brya: Board ID 1: Handle TCPC_RST reassignmentCaveh Jalali2021-05-273-3/+43
| | | | | | | | | | | | | | | | | | We are transitioning GPIO definitions to be correct for board ID 2. In order to support board ID 1 with the same EC image, some GPIOs need to be reconfigured to their legacy settings at runtime when board ID 1 is detected. For board ID 2, the TCPC C0/C2 reset GPIO has moved to a previously unused pin. The original pin is now an ADC input pin. BRANCH=none BUG=b:183452273 TEST=verified TCPC C0/C2 can be reset on board ID 1 using ID_1_USB_C0_C2_TCPC_RST_ODL. Change-Id: I52d8044ed10379346ae36d4f5d6cbe7446867182 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2914209 Reviewed-by: Boris Mittelberg <bmbm@google.com>
* brya: Board ID 1: Handle KB_BL_EN reassignmentCaveh Jalali2021-05-272-2/+26
| | | | | | | | | | | | | | | | | | | We are transitioning GPIO definitions to be correct for board ID 2. In order to support board ID 1 with the same EC image, some GPIOs need to be reconfigured to their legacy settings at runtime when board ID 1 is detected. For board ID 2, the keyboard backlight enable GPIO has moved to a previously unused pin and its polarity is inverted. The original pin is now an ADC input pin. BRANCH=none BUG=b:183452273 TEST=verified keyboard backlight function with "kblight" EC console command Change-Id: I86a1b09c9aaab8f6275a65cd1331f135b152f538 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2914208 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Boris Mittelberg <bmbm@google.com>
* brya: Board ID 2: Update generated-gpio.inc from spreadsheetCaveh Jalali2021-05-271-6/+6
| | | | | | | | | | | | | | | This updates the byra GPIO definitions to match the board ID 2 schematics. BRANCH=none BUG=b:183452273 TEST=booted on board ID 1 with following patches Change-Id: I55f1f926f7adbd113c8e8a4dcdff9ec2ae667ab6 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2914207 Reviewed-by: Boris Mittelberg <bmbm@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* honeybuns: Move configs for MP release to board.hScott Collyer2021-05-263-0/+20
| | | | | | | | | | | | | | | | | This CL moves the configs that are needed to be changed for an MP release to the board.h files from baseboard.h. BUG=b:183686750 BRANCH=quiche TEST=make BOARD=quiche/gingerbread/baklava Signed-off-by: Scott Collyer <scollyer@google.com> Change-Id: I7c602ecb2f2af02638be080613bb83dee568c332 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2911737 Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Scott Collyer <scollyer@chromium.org>
* oak: Disable AMON BMON console command to save spaceVijay Hiremath2021-05-261-1/+0
| | | | | | | | | | | | | | | | | BUG=none BRANCH=none TEST=make BOARD=oak -j Before: 24 bytes in flash and 11760 bytes in RAM still available on oak RO 12716 bytes in flash and 11760 bytes in RAM still available on oak RW After: 408 bytes in flash and 11760 bytes in RAM still available on oak RO 13052 bytes in flash and 11760 bytes in RAM still available on oak RW Change-Id: Ib14376020e06e54b679ba5b6af853b219b0c0c3d Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2920792 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* Revert "brya: reduce TCPC debug level to unblock testing"Boris Mittelberg2021-05-261-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 7275ced0eadbf0adfe307f2e3c49f830e488f89a. Reason for revert: PD State names are required for FAFT to work Original change's description: > brya: reduce TCPC debug level to unblock testing > > Important EC log messages are getting overlapped by TCPC/PD messages. The > default level is now set to 0. > > BRANCH=none > BUG=b:186707521 > TEST=running FAFT PD with `pd dump 0` works > > Signed-off-by: Boris Mittelberg <bmbm@google.com> > Change-Id: Ia3415c878e49bae01460f5e2acb6b8ce736b9986 > Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2904553 > Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> > Reviewed-by: caveh jalali <caveh@chromium.org> Bug: b:186707521 Change-Id: Ied5f926f87d75917295e36b4f6bd70fd6318d7d1 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2920799 Bot-Commit: Rubber Stamper <rubber-stamper@appspot.gserviceaccount.com> Commit-Queue: caveh jalali <caveh@chromium.org>
* Homestar:LED:LED function realizationtongjian2021-05-261-65/+57
| | | | | | | | | | | | BUG=b:187539586 TEST=make -j BOARD=homestar Verify build on EVT board BRANCH=Trogdo Signed-off-by: tongjian <tongjian@huaqin.corp-partner.google.com> Change-Id: I9c77b60e11135df5e289ef32adfe34fef3134760 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2915162 Reviewed-by: Wai-Hong Tam <waihong@google.com>
* brya: Board ID 1: Set GPIO PCHHOT as inputCaveh Jalali2021-05-261-1/+1
| | | | | | | | | | | | | | | This fixes the definition of the PCHHOT GPIO to be an input on the EC side. This signal can be used to monitor the PCH status. Updated the GPIO spreadsheet for board ID 1 and regenerated file. BRANCH=none BUG=b:184811017 TEST=boots on brya board ID 1 Change-Id: Idde5ef2e95c1690833532eb598c257a001499f4d Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2918476 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* asurada: implement customized usb port power controlTing Shen2021-05-262-2/+4
| | | | | | | | | | | | | | | | | | | | | Some Sandisk stickers would enter fault status (down-train to USB2 or not detected) if Vbus is applied before xhci initialization. To fix this, copy usb_port_power_dumb.c to baseboard folder to implement board-specific enable mechanic. BUG=b:187149602 TEST=manually BRANCH=asurada Signed-off-by: Ting Shen <phoenixshen@google.com> Change-Id: I80536b640b4f67a4c17a3da7b193c92ab2f7b3eb Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2909972 Tested-by: Ting Shen <phoenixshen@chromium.org> Auto-Submit: Ting Shen <phoenixshen@chromium.org> Reviewed-by: Eric Yilun Lin <yllin@google.com> Commit-Queue: Eric Yilun Lin <yllin@google.com>
* haboki: Update fw_config_dbTommy Chung2021-05-261-6/+12
| | | | | | | | | | | | | | | | Update fw_config_db to meet cbi_fw_config table on haboki. BUG=b:189154383 BRANCH=none TEST=on haboki, make sure that all DB configs act correctly. Signed-off-by: Tommy Chung <tommy.chung@quanta.corp-partner.google.com> Change-Id: I014afd6939094db12f4abd76483a21567e3aee8f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2905035 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Bob Moragues <moragues@chromium.org> Reviewed-by: Zick Wei <zick.wei@quanta.corp-partner.google.com> Commit-Queue: Henry Sun <henrysun@google.com>
* kracko: Update fw_config_dbTommy Chung2021-05-261-6/+12
| | | | | | | | | | | | | | | Update fw_config_db to meet cbi_fw_config table on kracko. BUG=b:189131006 BRANCH=dedede TEST=on kracko, make sure that all DB configs act correctly. Signed-off-by: Tommy Chung <tommy.chung@quanta.corp-partner.google.com> Change-Id: I0a2ccd9a90127a51042c115176e382900c396bf4 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2902075 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Henry Sun <henrysun@google.com> Commit-Queue: Henry Sun <henrysun@google.com>
* lantis: Update fw_config_dbTommy Chung2021-05-261-6/+12
| | | | | | | | | | | | | | | Update fw_config_db to meet cbi_fw_config table on lantis. BUG=b:186393848 BRANCH=dedede TEST=on lantis, make sure that all DB configs act correctly. Signed-off-by: Tommy Chung <tommy.chung@quanta.corp-partner.google.com> Change-Id: I7cade5d603f815a60ba89c6cdf86ac48b41eafe3 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2902073 Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Henry Sun <henrysun@google.com>
* drawcia: Update fw_config_dbTommy Chung2021-05-261-6/+12
| | | | | | | | | | | | | | | | Update fw_config_db to meet cbi_fw_config table on drawcia. BUG=b:186393848 BRANCH=dedede TEST=on drawcia, make sure that all DB configs act correctly. Signed-off-by: Tommy Chung <tommy.chung@quanta.corp-partner.google.com> Change-Id: I1d123f6119911840f3ffae9d3746820ca3e5511d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2902071 Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Devin Lu <Devin.Lu@quantatw.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Henry Sun <henrysun@google.com>
* usb_common: Assert CCD_MODE when DTS connectedRob Barnes2021-05-262-1/+2
| | | | | | | | | | | | | | | | | | Drive CCD_MODE_ODL from EC when EC sees DTS connected to CCD port. This will fix some cases where the Cr50 is not able to detect that a CCD debug cable has been connected. BUG=b:175056327 TEST=Connect/disconnect SuzyQ cable, see assert/unassert in log Check gpioget on CR50 and ec, confirm CCD_MODE_ODL is correct Connect/disconnect charger, do not see assert/unassert in log Repeat with ServoV4 BRANCH=None Change-Id: I411e75a47f2e1303ddbd9caa63a9417630c99b46 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2659282 Reviewed-by: Denis Brockus <dbrockus@chromium.org>
* Kakadu: add the support for ICM42607wen zhang2021-05-253-2/+103
| | | | | | | | | | | | | | | Bosh notice that BMI160 are going EOL, so we intend to import ICM42607 for Kakadu BUG=b:189077747 BRANCH=kukui TEST=1.make BOARD=kakadu 2.ectool motionsense can get the sensor data Change-Id: If73306784e276c21f158c6977e02b532087b2b22 Signed-off-by: wen zhang <zhangwen6@huaqin.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2910568 Reviewed-by: Ting Shen <phoenixshen@chromium.org>
* guybrush: Disable SOC_TEMP for board_version > 1Rob Barnes2021-05-241-0/+19
| | | | | | | | | | | | | | | | SOC_TEMP is being replaced with i2c temp sensor in board version 2. Disable SOC_TEMP so it doesn't cause thermal trips on board version 2. Move board_get_soc_temp to board level since variants will not need this logic. BUG=b:188540408 TEST=Boot guybrush, see SOC temp is correct BRANCH=None Signed-off-by: Rob Barnes <robbarnes@google.com> Change-Id: I8880b74993d0a942894f1c06346c534d1f39466d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2906314 Reviewed-by: Diana Z <dzigterman@chromium.org>
* brya: Skip mp2964 tuning on expected AP global resetCaveh Jalali2021-05-241-0/+6
| | | | | | | | | | | | | | | | | | | | Due to CSE lite boot behavior, the AP goes through an additional global reset. This shows up as a transition back down to S5 on the EC. CHIPSET_SHUTDOWN and CHIPSET_STARTUP hooks are executed when this happens, so we need to remember that we've been here before and only run mp2964 update the first time through. BRANCH=none BUG=b:185424011 TEST=verified mp2964 tuning only runs once using EC console logs Change-Id: I08007dfa62bf842c51e4f6474322302409f4256c Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2911509 Reviewed-by: Boris Mittelberg <bmbm@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Commit-Queue: Boris Mittelberg <bmbm@google.com> Commit-Queue: Tim Wawrzynczak <twawrzynczak@chromium.org>
* lindar: modify PD_MAX_POWER_MW to 45W.arthur.lin2021-05-241-1/+1
| | | | | | | | | | | | | | | Modify PD_MAX_POWER_MW to 45000 from 60000. BRANCH=firmware-volteer-13672.B BUG=b:188855362 TEST=make buildall -j Signed-off-by: arthur.lin <arthur.lin@lcfc.corp-partner.google.com> Change-Id: Iaa62c3f0f343d3e88f83b21bb15832e82856e3cd Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2911100 Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Zhuohao Lee <zhuohao@chromium.org> Commit-Queue: Zhuohao Lee <zhuohao@chromium.org>
* brya: board ID 2: Move RT_RST to different pinCaveh Jalali2021-05-222-12/+16
| | | | | | | | | | | | | | | Brya board ID 2 moves the USB_C0_RT_RST_ODL pin from GPIO02 to GPIO07 of the nct3808. BRANCH=none BUG=b:188826559 TEST=still able to read BB registers using EC console Change-Id: I82875230ea7c2ecaedfbd4a1672031b81a4bd022 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2912056 Reviewed-by: Boris Mittelberg <bmbm@google.com> Commit-Queue: Boris Mittelberg <bmbm@google.com>
* dooly: fix lux overflowZick Wei2021-05-211-19/+25
| | | | | | | | | | | | | | | | | | | | We saw under some low light environment lux will switch between 0 to extreme high value, wich will cause display backlight flash, this CL fix this issue due there is overflow in calculation. BUG=b:188205311 BRANCH=puff TEST=make sure panel backlight not flash in low light environment. Signed-off-by: Zick Wei <zick.wei@quanta.corp-partner.google.com> Change-Id: I47680e0c84d84f183fd5c2b973429e9964539049 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2909095 Tested-by: Zick Wei <zick.wei@quanta.corp-partner.google.com> Tested-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-by: Gwendal Grignou <gwendal@chromium.org> Commit-Queue: Gwendal Grignou <gwendal@chromium.org>
* nucleo-h743zi: Check if AP is on when processing HOOK_INIT hooksPatryk Duda2021-05-211-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Call ap_deferred() function directly (not as deferred function) from board_init(). This change causes CS pin interrupt to be enabled while running board_init() init hook, just after SPI initialization. It removes 43ms window when SPI is initialized but we are not able to communicate because interrupt on CS line is not enabled. This change only affects RW firmware. After main(), only hook task is marked as ready, so we are switching to it and start executing HOOK_INIT hooks (spi_init() and board_init() are called). SPI initialization is performed, but CS interrupt is still not enabled (spi_init() checks if chipset is on). The interrupt is enabled on HOOK_CHIPSET_RESUME. For RW side HOOK_CHIPSET_RESUME is emitted when SLP_L and SLP_ALT_L are set to 1 (see ap_deferred()). ap_deferred() is a deferred function so it is called from hook task context. It is scheduled always in board_init() or in slp_event() when SLP_L and SLP_ALT_L changes. When hook task finishes executing all HOOK_INIT hooks it enables other tasks with task_enable_all_tasks(). Now task with higher priority is scheduled (CONSOLE, HOSTCMD, FPSENSOR tasks have higher priority than HOOK task). When all higher priority tasks are waiting for events hook task is scheduled and we can finally run ap_deferred() function which should enable interrupt on CS pin (if AP is running). BUG=b:185467818 BRANCH=none TEST=make -j buildall TEST=Flash nucleo-h743zi board and check if it is fully functional Signed-off-by: Patryk Duda <pdk@semihalf.com> Change-Id: I9a3b80688b67e8babaf51e38859f6f43b19201f8 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2905656 Reviewed-by: Craig Hesling <hesling@chromium.org>
* nucleo-f412zg: Check if AP is on when processing HOOK_INIT hooksPatryk Duda2021-05-211-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Call ap_deferred() function directly (not as deferred function) from board_init(). This change causes CS pin interrupt to be enabled while running board_init() init hook, just after SPI initialization. It removes 43ms window when SPI is initialized but we are not able to communicate because interrupt on CS line is not enabled. This change only affects RW firmware. After main(), only hook task is marked as ready, so we are switching to it and start executing HOOK_INIT hooks (spi_init() and board_init() are called). SPI initialization is performed, but CS interrupt is still not enabled (spi_init() checks if chipset is on). The interrupt is enabled on HOOK_CHIPSET_RESUME. For RW side HOOK_CHIPSET_RESUME is emitted when SLP_L and SLP_ALT_L are set to 1 (see ap_deferred()). ap_deferred() is a deferred function so it is called from hook task context. It is scheduled always in board_init() or in slp_event() when SLP_L and SLP_ALT_L changes. When hook task finishes executing all HOOK_INIT hooks it enables other tasks with task_enable_all_tasks(). Now task with higher priority is scheduled (CONSOLE, HOSTCMD, FPSENSOR tasks have higher priority than HOOK task). When all higher priority tasks are waiting for events hook task is scheduled and we can finally run ap_deferred() function which should enable interrupt on CS pin (if AP is running). BUG=b:185467818 BRANCH=none TEST=make -j buildall TEST=Flash nucleo-f412zg board and check if it is fully functional Signed-off-by: Patryk Duda <pdk@semihalf.com> Change-Id: Ia71c30a1e738411f566a7f29354c04a337cdce6c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2905655 Reviewed-by: Craig Hesling <hesling@chromium.org>
* nucleo-dartmonkey: Check if AP is on when processing HOOK_INIT hooksPatryk Duda2021-05-211-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Call ap_deferred() function directly (not as deferred function) from board_init(). This change causes CS pin interrupt to be enabled while running board_init() init hook, just after SPI initialization. It removes 43ms window when SPI is initialized but we are not able to communicate because interrupt on CS line is not enabled. This change only affects RW firmware. After main(), only hook task is marked as ready, so we are switching to it and start executing HOOK_INIT hooks (spi_init() and board_init() are called). SPI initialization is performed, but CS interrupt is still not enabled (spi_init() checks if chipset is on). The interrupt is enabled on HOOK_CHIPSET_RESUME. For RW side HOOK_CHIPSET_RESUME is emitted when SLP_L and SLP_ALT_L are set to 1 (see ap_deferred()). ap_deferred() is a deferred function so it is called from hook task context. It is scheduled always in board_init() or in slp_event() when SLP_L and SLP_ALT_L changes. When hook task finishes executing all HOOK_INIT hooks it enables other tasks with task_enable_all_tasks(). Now task with higher priority is scheduled (CONSOLE, HOSTCMD, FPSENSOR tasks have higher priority than HOOK task). When all higher priority tasks are waiting for events hook task is scheduled and we can finally run ap_deferred() function which should enable interrupt on CS pin (if AP is running). BUG=b:185467818 BRANCH=none TEST=make -j buildall TEST=Flash nucleo-dartmonkey board and check if it behaves correctly Signed-off-by: Patryk Duda <pdk@semihalf.com> Change-Id: I93413c002aa98e8ebdb96aca2764b8ee1551d5f7 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2905654 Reviewed-by: Craig Hesling <hesling@chromium.org>
* brya: Move battery_hw_present to boardCaveh Jalali2021-05-211-0/+8
| | | | | | | | | | | | | | | | This moves the battery_hw_present() function from the baseboard to the board file. We have a GPIO shuffle in the works for brya that requires board specific knowledge to support multiple revisions of the board. BRANCH=none BUG=b:183452273 TEST=battery works fine on brya ID 1 Change-Id: Ida698911539486cc68f509efd8533325b59e031e Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2912055 Reviewed-by: Boris Mittelberg <bmbm@google.com> Commit-Queue: Boris Mittelberg <bmbm@google.com>
* brya: Add lid_open interrupt annotationCaveh Jalali2021-05-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | This updates the GPIOD2 (the lid open interrupt) pin alternate mode declaration to include the interrupt declaration. This is done for consistency by the gpio.inc generator; there is no functional change as the GPIO_INT() declaration already sets the interrupt mode. Note: The reason the existing declaration works is because the npcx support code treats interrupt flags as additive w.r.t. the GPIO(...) declaration. Other flags are not additive and must be specified a 2nd time. Best practice is to always specify the complete set of config flags. BRANCH=none BUG=b:185322560 TEST=visual inspection Signed-off-by: Caveh Jalali <caveh@chromium.org> Change-Id: I29c5ed44479dfcc732d01d46ccab5ed1ecaa314b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2912054 Reviewed-by: Boris Mittelberg <bmbm@google.com> Commit-Queue: Boris Mittelberg <bmbm@google.com>
* Cherry: change gyro snesor to ICM-42607-PSue Chen2021-05-213-20/+33
| | | | | | | | | | | | | Change base accelgyro driver to icm42607. BUG=b:187748640 BRANCH=none TEST=console "accelinfo on" and ectool motionsense show correctly. Signed-off-by: Sue Chen <sue.chen@quanta.corp-partner.google.com> Change-Id: Ib53f72ae283a7bf5a6193dcf3b656121af94c66f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2909954 Reviewed-by: Ting Shen <phoenixshen@chromium.org>
* Cherry: Add battery informationSue Chen2021-05-212-13/+70
| | | | | | | | | | | | | New battery: AP16L5J BUG=none BRANCH=none TEST=Check found battery info in console and cutoff work. Signed-off-by: Sue Chen <sue.chen@quanta.corp-partner.google.com> Change-Id: Ife754ad23063b3471fff097a5c34f7cbc57c2a5a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2812600 Reviewed-by: Ting Shen <phoenixshen@chromium.org>
* cherry: Add temp sensor for chargerSue Chen2021-05-212-1/+6
| | | | | | | | | | | | | Using ADC channel 7 to read charger temperature. BUG=b:187463588 BRANCH=none TEST=Console commad "temps" and ectool can read the temperature. Signed-off-by: Sue Chen <sue.chen@quanta.corp-partner.google.com> Change-Id: I031523859c0ff91f0041263ecf6a4a48048da819 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2891283 Reviewed-by: Ting Shen <phoenixshen@chromium.org>
* Homestar:Battery:Modify battery parameters for SMP and Sunwodatongjian2021-05-211-4/+4
| | | | | | | | | | | | | | | 1.Currently SMP and Sunwoda batteries are used 2.fix batterycutoff fail BUG=b:184829414 TEST=make -j BOARD=homestar Verify build on EVT board BRANCH=Trogdo Signed-off-by: tongjian <tongjian@huaqin.corp-partner.google.com> Change-Id: Ieeb2a20673cb0717c9042e2d73d02d1adb40c573 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2897068 Reviewed-by: Wai-Hong Tam <waihong@google.com>
* Genesis: Fix LED behavior at initSue Chen2021-05-201-0/+7
| | | | | | | | | | | | | | Check power state to change LED state while initialize the LEDs. BUG=b:188740216 BRANCH=puff TEST=Check the LED behavior is correct. Signed-off-by: Sue Chen <sue.chen@quanta.corp-partner.google.com> Change-Id: Ibe50f4c7835821dd24872f5ab8ec3a882251e9e5 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2905673 Reviewed-by: Joe Tessler <jrt@chromium.org> Commit-Queue: Joe Tessler <jrt@chromium.org>
* Genesis: LED PWM channels' IO type change to push-pullSue Chen2021-05-201-4/+2
| | | | | | | | | | | | | | Remove open-drain flags in led pwm ch.0 and ch.2 BUG=b:188740216 BRANCH=puff TEST=none Signed-off-by: Sue Chen <sue.chen@quanta.corp-partner.google.com> Change-Id: I6bd0df05f683fe841f1cb96b8a46793d93ec57f3 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2905159 Reviewed-by: Joe Tessler <jrt@chromium.org> Commit-Queue: Joe Tessler <jrt@chromium.org>
* adlrvpp_mchp1521: Add code for ADL-P-DDR4 RVP using Microchip ECPoornima Tom2021-05-206-0/+604
| | | | | | | | | | | | | | | | | | | ADL-P-DDR4 RVP has on board Microchip EC-MEC1521. This code enables RVP powering ON using this on board EC, instead of Mica EC. As this onboard EC doesn't have internal flash memory, EC binary of 512KB size generated is flashed to external SPI Flash1(32MB size) available on RVP over SPI using servo.This image from flash1 is then bootloaded by MEC1521, when powered ON. BUG=b:186669325 BRANCH=none TEST=ADL-P-DDR4 board with Microchip 1521 EC booted to S0. Signed-off-by: Poornima Tom <poornima.tom@intel.com> Change-Id: I39f937f60e2f79b0d2de195621084e3276e36bf2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2755363 Tested-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: caveh jalali <caveh@chromium.org>
* cleanup: mchp boards: Use standard eSPI configsPoornima Tom2021-05-203-9/+9
| | | | | | | | | | | | | BUG=b:186669325 BRANCH=none TEST=make buildall -j Signed-off-by: Poornima Tom <poornima.tom@intel.com> Change-Id: I8f1cc9f3e053ad53061e0c19170a0f638d439c13 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2906443 Tested-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: caveh jalali <caveh@chromium.org> Commit-Queue: Vijay Hiremath <vijay.p.hiremath@intel.com>
* cret: Add three battery parameterjohnwc_yeh2021-05-192-8/+110
| | | | | | | | | | | | | | | | | Add three battery type for cret. And add device name to identify. BUG=b:183875170 BRANCH=dedede TEST=make BOARD=cret Signed-off-by: johnwc_yeh <johnwc_yeh@compal.corp-partner.google.com> Change-Id: I923eed50eb08be38a60a01c28dc2eb9e35f9d255 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2905166 Reviewed-by: Elthan Huang <elthan_huang@compal.corp-partner.google.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Elthan Huang <elthan_huang@compal.corp-partner.google.com> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* config: Populate CONFIG_SUPPRESSED_HOST_COMMANDSGwendal Grignou2021-05-1912-27/+3
| | | | | | | | | | | | | | | | | | | | | Commands that are send peridically or in high number are not reported on the console through CONFIG_SUPPRESSED_HOST_COMMANDS variable. Use the same set of commands throughout to avoid misses like newer command EC_CMD_GET_UPTIME_INFO. BUG=none BRANCH=none TEST=buildall Signed-off-by: Gwendal Grignou <gwendal@google.com> Change-Id: I0041576538a8cc659c262118b1503777b9ea8578 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2851452 Reviewed-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Craig Hesling <hesling@chromium.org> Tested-by: Gwendal Grignou <gwendal@chromium.org> Commit-Queue: Gwendal Grignou <gwendal@chromium.org>
* Homestar:Sensor:Update the sensor matrixtongjian2021-05-191-1/+1
| | | | | | | | | | | | BUG=b:187379242 TEST=make -j BOARD=homestar Verify build on EVT board BRANCH=Trogdor Signed-off-by: tongjian <tongjian@huaqin.corp-partner.google.com> Change-Id: I08f2ab2f32150cf07d10b9987b9f19f18d9b566d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2878756 Reviewed-by: Wai-Hong Tam <waihong@google.com>
* brya: reduce TCPC debug level to unblock testingBoris Mittelberg2021-05-191-0/+3
| | | | | | | | | | | | | | | Important EC log messages are getting overlapped by TCPC/PD messages. The default level is now set to 0. BRANCH=none BUG=b:186707521 TEST=running FAFT PD with `pd dump 0` works Signed-off-by: Boris Mittelberg <bmbm@google.com> Change-Id: Ia3415c878e49bae01460f5e2acb6b8ce736b9986 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2904553 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: caveh jalali <caveh@chromium.org>
* blipper: add a thermal sensor configMike Lee2021-05-183-3/+15
| | | | | | | | | | | | | | | 1.add a new thermal sensor for detect typeC field temp 2.modify sensor name BUG=b:188367187 BRANCH=dedede TEST=make BOARD=blipper,'ectool temps all' test ok Signed-off-by: Mike Lee <mike5@huaqin.corp-partner.google.com> Change-Id: Iae0624ca33a80125b58b92e5b564c6211c107931 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2902061 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* bloonchipper: Check if AP is on when processing HOOK_INIT hooksPatryk Duda2021-05-181-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Call ap_deferred() function directly (not as deferred function) from board_init_rw(). This change causes CS pin interrupt to be enabled while running board_init() init hook, just after SPI initialization. It removes 43ms window when SPI is initialized but we are not able to communicate because interrupt on CS line is not enabled. This change only affects RW firmware. FPMCU log without this change: [Reset cause: reset-pin soft sysjump] [1.322620 Inits done] [1.322665 hook_task: running HOOK_INIT] [1.322713 hook notify 0] [1.322754 spi_init: init] [1.322794 spi_init: SPI initialized] [1.322846 board_init: init] [1.322901 FP_SPI_SEL: DEVELOPMENT] [1.322954 TRANSPORT_SEL: SPI] [1.323009 hook_task: enabling all other tasks] Console is enabled; type HELP for help. > [1.323106 event set 0x0000000000002000] [1.323176 hostcmd init 0x0000000000002000] [1.323238 FP_SENSOR_SEL: FPC] FPC libfpsensor.a v0.2.0.064 [1.365068 hook call deferred 0x8100365] [1.365132 ap_deferred: SLP_L is 1] [1.365180 ap_deferred: SLP_ALT_L is 1] [1.365232 hook notify 6] [1.365271 spi_chipset_startup: enabling interrupt] After main(), only hook task is marked as ready, so we are switching to it and start executing HOOK_INIT hooks (spi_init() and board_init() are called). SPI initialization is performed, but CS interrupt is still not enabled (spi_init() checks if chipset is on). The interrupt is enabled on HOOK_CHIPSET_RESUME. For RW side HOOK_CHIPSET_RESUME is emitted when SLP_L and SLP_ALT_L are set to 1 (see ap_deferred()). ap_deferred() is a deferred function so it is called from hook task context. It is scheduled always in board_init_rw() or in slp_event() when SLP_L and SLP_ALT_L changes. When hook task finishes executing all HOOK_INIT hooks it enables other tasks with task_enable_all_tasks(). Now task with higher priority is scheduled (CONSOLE, HOSTCMD, FPSENSOR tasks have higher priority than HOOK task). When all higher priority tasks are waiting for events hook task is scheduled and we can finally run ap_deferred() function which should enable interrupt on CS pin (if AP is running). FPMCU log with this change, interrupt is enabled 300us after SPI is initialized: [Reset cause: reset-pin soft sysjump] [1.322458 Inits done] [1.322503 hook_task: running HOOK_INIT] [1.322551 hook notify 0] [1.322592 spi_init: init] [1.322632 spi_init: SPI initialized] [1.322684 board_init: init] [1.322740 FP_SPI_SEL: DEVELOPMENT] [1.322793 TRANSPORT_SEL: SPI] [1.322837 ap_deferred: SLP_L is 1] [1.322885 ap_deferred: SLP_ALT_L is 1] [1.322936 hook notify 6] [1.322975 spi_chipset_startup: enabling interrupt] [1.323113 hook_task: enabling all other tasks] BUG=b:185467818 BRANCH=none TEST=make -j buildall Signed-off-by: Patryk Duda <pdk@semihalf.com> Change-Id: I91f868c01458ac5b7d02c4e5d2a7ae51060ffc50 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2900222 Reviewed-by: Craig Hesling <hesling@chromium.org>
* pirika: Implement keyboard matrix functionKirk Wang2021-05-182-1/+45
| | | | | | | | | | | | | | | | | 1. Base on keyboard spec, modify the keyboard related setting. BUG=b:187343638 BRANCH=none TEST=make BOARD=pirika and pirette 1. Verify keyboard function behavior. Signed-off-by: Kirk Wang <kirk_wang@pegatron.corp-partner.google.com> Change-Id: I865b7e913c8901f5f02e974b3224d6d4c29891eb Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2900118 Reviewed-by: Alex1 Kao <alex1_kao@pegatron.corp-partner.google.com> Reviewed-by: Shou-Chieh Hsu <shouchieh@chromium.org> Commit-Queue: Shou-Chieh Hsu <shouchieh@chromium.org>
* Trogdor: Enable Trogdor as a convertibleWai-Hong Tam2021-05-173-1/+78
| | | | | | | | | | | | | | | | | | | | | | | | Trogdor rev-0 and rev-1 are clamshell designs. Trogdor rev-2 is a convertible design. We don't support rev-0 and rev-1. Make it straight to a convertible: * Add the lid acceleration sensor * Just assign a random rotation metrix, as no chassis * Add the GPIO TABLET_MODE_L interrupt * Enable lid angle detection that disables keyboard * Enable sensors in S3 for the above angle detection BRANCH=None BUG=b:187343625 TEST=Build the Trogdor image and enable "accelinfo on" which shows the lid accel reading and the lid angle. As the lid accel sensor is not mounted to the lid surface. The lid accel reading and the lid angle are not accurate. Change-Id: I16af2c63181eb6037fbf6742c07427e20064c335 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2895920 Reviewed-by: Stephen Boyd <swboyd@chromium.org>
* dartmonkey: Check if AP is on when processing HOOK_INIT hooksPatryk Duda2021-05-171-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Call ap_deferred() function directly (not as deferred function) from board_init_rw(). This change causes CS pin interrupt to be enabled while running board_init() init hook, just after SPI initialization. It removes 43ms window when SPI is initialized but we are not able to communicate because interrupt on CS line is not enabled. This change only affects RW firmware. FPMCU log without this change: [Reset cause: reset-pin soft sysjump] [1.322620 Inits done] [1.322665 hook_task: running HOOK_INIT] [1.322713 hook notify 0] [1.322754 spi_init: init] [1.322794 spi_init: SPI initialized] [1.322846 board_init: init] [1.322901 FP_SPI_SEL: DEVELOPMENT] [1.322954 TRANSPORT_SEL: SPI] [1.323009 hook_task: enabling all other tasks] Console is enabled; type HELP for help. > [1.323106 event set 0x0000000000002000] [1.323176 hostcmd init 0x0000000000002000] [1.323238 FP_SENSOR_SEL: FPC] FPC libfpsensor.a v0.2.0.064 [1.365068 hook call deferred 0x8100365] [1.365132 ap_deferred: SLP_L is 1] [1.365180 ap_deferred: SLP_ALT_L is 1] [1.365232 hook notify 6] [1.365271 spi_chipset_startup: enabling interrupt] After main(), only hook task is marked as ready, so we are switching to it and start executing HOOK_INIT hooks (spi_init() and board_init() are called). SPI initialization is performed, but CS interrupt is still not enabled (spi_init() checks if chipset is on). The interrupt is enabled on HOOK_CHIPSET_RESUME. For RW side HOOK_CHIPSET_RESUME is emitted when SLP_L and SLP_ALT_L are set to 1 (see ap_deferred()). ap_deferred() is a deferred function so it is called from hook task context. It is scheduled always in board_init_rw() or in slp_event() when SLP_L and SLP_ALT_L changes. When hook task finishes executing all HOOK_INIT hooks it enables other tasks with task_enable_all_tasks(). Now task with higher priority is scheduled (CONSOLE, HOSTCMD, FPSENSOR tasks have higher priority than HOOK task). When all higher priority tasks are waiting for events hook task is scheduled and we can finally run ap_deferred() function which should enable interrupt on CS pin (if AP is running). FPMCU log with this change, interrupt is enabled 300us after SPI is initialized: [Reset cause: reset-pin soft sysjump] [1.322458 Inits done] [1.322503 hook_task: running HOOK_INIT] [1.322551 hook notify 0] [1.322592 spi_init: init] [1.322632 spi_init: SPI initialized] [1.322684 board_init: init] [1.322740 FP_SPI_SEL: DEVELOPMENT] [1.322793 TRANSPORT_SEL: SPI] [1.322837 ap_deferred: SLP_L is 1] [1.322885 ap_deferred: SLP_ALT_L is 1] [1.322936 hook notify 6] [1.322975 spi_chipset_startup: enabling interrupt] [1.323113 hook_task: enabling all other tasks] BUG=b:185467818 BRANCH=none TEST=make -j buildall Signed-off-by: Patryk Duda <pdk@semihalf.com> Change-Id: I51a30b1cec35d19d6cdf3241a310e7427c750f88 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2891863 Reviewed-by: Craig Hesling <hesling@chromium.org>
* qcom: Generalize the filenames for Qualcomm chipsetsWai-Hong Tam2021-05-177-7/+7
| | | | | | | | | | | | | | | The existing SC7180 power sequence can be reused on its next generation. Generalize the filenames, sc7180.c/sc7180.h to qcom.c/qcom.h. BRANCH=None BUG=b:187980397 TEST=Built all the Chromium EC images and Zephyr EC images. Change-Id: Ie04218ef0a12a4e8aa2db353040c5c39c533ae6f Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2893484 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Alexandru M Stan <amstan@chromium.org>
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