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* PMU tps65090 driverRong Chang2012-05-312-0/+2
| | | | | | | | | | | | | | This is an initial commit of tps65090 pmu driver. An empty charging task added. Signed-off-by: Rong Chang <rongchang@chromium.org> BUG=chrome-os-partner:9756 TEST=manual When connected to a battery, the EC uart console will display battery status on value change. Check pmu register with 'i2c r 0x90 4'. Output should be '0x03'. Change-Id: I99e243d203c438751af0c3647556cbf9a94e928f
* Add stm32 I2C master driverRong Chang2012-05-312-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A polling mode I2C master driver. Interfaces for read/write byte and word are implemented. i2c_read_string() is currently an empty function. CONFIG_SMART_BATTERY added to daisy board for testing. Move smart_battery.o back to CONFIG_SMART_BATTERY since it is not depended on charging state machine. Signed-off-by: Rong Chang <rongchang@chromium.org> BUG=chrome-os-partner:9724 TEST=manual/host commands > battery Temp: 0x0bad = 298.9 K (25.8 C) Manuf: Device: Chem: Serial: 0x0001 V: 0x1cb7 = 7351 mV V-desired: 0x20d0 = 8400 mV V-design: 0x1c20 = 7200 mV I: 0x0000 = 0 mA I-desired: 0x0bb8 = 3000 mA Mode: 0x6001 Charge: 49 % Abs: 47 % Remaining: 2705 mAh Cap-full: 5575 mAh Design: 5800 mAh Time-full: 0h:0 Empty: 0h:0 Change-Id: I9f4e9e8819955ad1b107fb3b70ac2559d9b02b55
* Merge "stm32: use level interrupt instead of edge"Vincent Palatin2012-05-304-10/+8
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| * stm32: use level interrupt instead of edgeVincent Palatin2012-05-304-10/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Using low level trigger interrupt rather than falling edge is more robust since we avoid detecting glitches or missing interrupts. This is backward compatible with the AP software expecting falling edge. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=chrome-os-partner:8869 TEST=On Daisy, check we can still enter text in U-Boot console and Chrome browser (and check interrupt count increase as expected). Change-Id: Ide2b27f9129173530d137b5d70d998ebd8f8e669
* | Add basic SPI support to linkRandall Spangler2012-05-302-0/+3
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds SPI transaction support, and a debug command to read a few values from the SPI EEPROM. Note that the SPI controller is normally *disabled* with all its I/Os high-Z, so this will not interfere with main processor or Servo on the SPI bus. The bus is only enabled during the SPIROM command itself. BUG=chrome-os-partner:7844 TEST=manual 1) Reboot system 2) on EC console, 'spirom'. Should print Man/Dev ID : 0xef 0x16 JEDEC ID : 0xef 0x40 0x17 Unique ID : 0xd1 0x61 0x44 0xb0 0x63 0x5d 0x40 0x32 Status reg 1: 0x00 Status reg 2: 0x00 Note that unique ID is, well, unique, so it won't match my value. But it should still be something not all 0xff's. 3) Power on the system. x86 should still boot normally, indicating that the EC isn't interfering with the SPI bus. Change-Id: I53bf5fdbbe7a37949375d0463e30e408cc6fb6a8
* Add a way to set indiviual sensitivity factor for each TMP006 sensorVic Yang2012-05-281-4/+5
| | | | | | | | | | | | Each TMP006 temperature sensor has different sensitivity factor. Let's add a field to set different sensitivity factor for each sensor. Also update the factors to get more reasonable temperature readings, but still need more precise calibration. BUG=chrome-os-partner:9599 TEST=Build and read tempearture succeeded. Change-Id: Ib4feea3b78b71f6d37c9a02668ffa7bd9e63d390
* Add system_is_locked() to prevent sysjump on consumer systemsRandall Spangler2012-05-253-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | This returns true when both HW and SW write protect are enabled. Once WP is enabled, sysjump will be locked out. system_is_locked() can be used to gate other dangerous-ish commands too. Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:7468 TEST=manual sysinfo -> unlocked, copy A sysjump B -> works flashwp lock reboot (make sure flashinfo shows WP asserted and flash locked; note there is a HW bug on proto1 which makes this flaky) sysinfo -> locked, copy A sysjump B -> fails (remove WP screw) reboot hard flashwp unlock Change-Id: I849b573675c2c1cb4c44b9a05d6973e38247ca23
* Better help for console commandsRandall Spangler2012-05-252-0/+4
| | | | | | | | | | | | | | | | | | | | Additional help messages and usage are gated by CONFIG_CONSOLE_CMDHELP, so we can turn it on if there's space (adds about 3KB to image size) and turn it off when there isn't. Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=none TEST=manual 1) help 2) help list 3) help gpioset 4) gpioset -> wrong number of params 5) gpioset fred 0 -> param1 bad 6) gpioset cpu_prochot fred -> param2 bad Change-Id: Ibe99f37212020f763ebe65a068e6aa83a809a370
* stm32: fix keyboard FIFOVincent Palatin2012-05-251-0/+3
| | | | | | | | | | | | | | When the FIFO is empty, returns the last read entry not the next one. also rewrite the FIFO index increment to generate slightly better code. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=chrome-os-partner:8869 TEST=On Snow, in U-Boot using "stdin=mkbp-keyb" type on internal keyboard and see the correct text. Change-Id: I189d230053de40dd563ce672db82dd6217e545e3
* Add FMAP even if VBOOT is not activatedv1.0.0Vincent Palatin2012-05-222-6/+0
| | | | | | | | | | | This simplifies the re-flashing for stm32 based platforms. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=chrome-os-partner:8865 TEST=On Daisy, flashrom -p internal:bus=lpc -w ec.bin Change-Id: I66860383c34110b1edf852929c244a2b682bc105
* stm32: add flash driver for stm32f100 SoCVincent Palatin2012-05-211-0/+3
| | | | | | | | | | | | Implementation of the flash driver for the stm32f100 chip used on Snow board. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=chrome-os-partner:8865 TEST=On Snow board, use "flashwrite/flasherase" commands from EC console and verify result with "rw" command. Change-Id: Ie8b8be3d549ff9ec8c3036d5f4a97480daa5e03e
* Use common host command processing for Daisy I2CVincent Palatin2012-05-184-4/+8
| | | | | | | | | | | | This also updates the communication protocol between the EC and the AP in a non backward compatible way. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=chrome-os-partner:9614 TEST=on Daisy with updated kernel driver, use the keyboard in ChromeOS Change-Id: I5a50e9a74b9891153a37ea79318c8a66a1b0c5ca
* Add a list of I2C portsRandall Spangler2012-05-174-21/+26
| | | | | | | | | | | | | | | | | This cleans up I2C init and debug commands across boards. Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=none TEST=on link and bds: i2cscan lightbar run powerbtn (to power on system) temps (to read i2c temp sensors) battery (to read battery) charger (to read charger) Change-Id: If3fb0cdb8d3178592bf68cbb2e72bc4b7f71dec5
* Disable unused BDS functionalityRandall Spangler2012-05-177-293/+11
| | | | | | | | | | | | | This was used on the hybrid Badger-Lumpy systems for one-off testing. It wouldn't necessarily work on a bare Badger board, and maintaining it resulted in frequent build breaks. Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=none TEST=build link, bds, daisy; boot link and bds Change-Id: Ib64ccad9f38d76832ab57f7254dbf32f3d5e4a5e
* Add AC state change hookRandall Spangler2012-05-173-1/+4
| | | | | | | | | | | | | | And start wiring to x86_power so it can detect AC state changes (needed to enable/disable turbo). *YES*, this compiles for BDS/Daisy now... Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:9069 TEST=plug/unplug AC power and look for "x86 AC on" / "x86 AC off" in debug log Change-Id: I8399fab9637d6635a1c615f07448fd45b86bc25f
* daisy/snow: seperate EC_INT and CODEC_INT handlingDavid Hendricks2012-05-154-15/+15
| | | | | | | | | | | | | | | | | | This patch splits apart EC_INT and CODEC_INT handling for two reasons: 1. Allow other tasks to interrupt the AP without triggering the keyboard noise suppression. 2. Allow more work to be done after a keystroke is detected but before interrupting the AP. This is intended to prevent latency issues with the noise suppression. Also, Snow does not currently have CODEC_INT hooked up, so it does not need the extra function for suppressing keystroke noise. BUG=chrome-os-partner:9594 TEST=tested on daisy (keys still respond), locally compiled for snow. Change-Id: I73bd42bb7263005b11724337162646092292556f Signed-off-by: David Hendricks <dhendrix@chromium.org>
* Merge "daisy/snow: define KB_OUTPUTS in board.h, remove KB_COLS"Gerrit2012-05-152-0/+6
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| * daisy/snow: define KB_OUTPUTS in board.h, remove KB_COLSDavid Hendricks2012-05-152-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | An upcoming CL will use the number of keyboard outputs (currently and incorrectly called KB_COLS) in another file. So this is a good time to clean up the naming to remove some column/row ambiguity and move the #define to board-specific configuration. BUG=none TEST=locally compiled for link and daisy Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: I155e3d6f2069c582517016c1116eaf668ffca86a
* | Merge "Enable vboot for BDS too."Gerrit2012-05-152-2/+3
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| * | Enable vboot for BDS too.Bill Richardson2012-05-152-2/+3
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | The recovery switch is the DOWN button. BUG=none TEST=manual Install on BDS, open console. Press the reset button, it should boot to firmware A. Hold the DOWN button, press the reset button. It should stay in RO. Change-Id: I82f72a56df463c7cc67bde7e09f3be1545c76129 Signed-off-by: Bill Richardson <wfrichar@chromium.org>
* | Rearrange task prioritiesRandall Spangler2012-05-151-5/+5
|/ | | | | | | | | | | | | | Charging state machine doesn't need to be able to preempt everybody. Keyboard scanning and power button should preempt, because they need to debounce/scan at a stable rate. Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=none TEST=system still boots Change-Id: Id57c680b9fa4652bc10d19270620d63788a7b269
* Change polarity of PROCHOT signal to match EVTRandall Spangler2012-05-142-2/+2
| | | | | | | | | | | | This would throttle proto1 systems, if it weren't for a HW bug which means we don't have prochot control over proto1 systems at all. Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:8982 TEST=system still boots Change-Id: Ie42c034141f24795ec2bfee592e194001d3cd174
* Enable verified boot for EC firmwareBill Richardson2012-05-104-0/+4
| | | | | | | | | | | | | | | | | | | | BUG=chrome-os-partner:7459 TEST=manual In the chroot: cd src/platform/ec make BOARD=link The firmware image (build/link/ec.bin) is signed with dev-keys. Reflash the EC and try it, and it should verify and reboot into RW A. Additional tests (setting USE_RO_NORMAL, poking random values into VBLOCK_A or FW_MAIN_A to force RW B to run, etc.) are left as an exercise for the reader. I've done them and they work, though. Change-Id: I29a23ea69aef02a11aebd4af3b043f6864723523 Signed-off-by: Bill Richardson <wfrichar@chromium.org>
* Use open drain reset signals, and clean up signals to 5VALW-powered devicesRandall Spangler2012-05-101-7/+4
| | | | | | | | | | | | | | | | | | | | | | Open drain cleanup minimizes leakage and signal glitching on shared reset/signal lines, and is tidier than explicitly switching the signals between inputs/outputs. Touchscreen and lightbar are powered by +5VALW so their signals need to be dropped when +5VALW is off to avoid leakage, and so they see a clean reset signal when they're powered up. Moved +5VALW power-on to S5-S3 transition, to minimize power draw in S5. This also ensures that 5VALW-powered devices get reset when the device bounces through S5. (No effect on proto1, where 5VALW is not under EC control.) Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:9172 TEST=boot and shutdown system; still works. Change-Id: Ia4bf0703292a189c324ce283d1e79a33776ee40f
* daisy: Disable keyscan messagesSimon Glass2012-05-101-0/+3
| | | | | | | | | | | | These messages are unnecessary and seem to hang the EC for a while. Punt them for now. BUG=none TEST=build and boot on daisy; see that keyboard still works, and messages do not appear Change-Id: I62963b62eb3e7cee86162784f364d7b1da37f631 Signed-off-by: Simon Glass <sjg@chromium.org>
* Drop DPWROK when system is off for more than 10 secrelease-R20-2268.BRandall Spangler2012-05-091-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | This saves ~70mw of power. To make this work, I also had to stretch the power button signal to give the system a chance to come back up when the user taps the power button. Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:9574 TEST=manual For each of the following tests, wait ~15 sec after the system is powered off to give it a chance to drop DPWROK. 1) tap power button -> system turns on 2) hold power button 1 sec -> system turns on 3) open lid -> system turns on 4) silego reset (power+refresh, or power+esc on proto1) -> system stays off 5) silego recovery (power+esc+refresh) -> system turns on 6) hold down power button and type 'reboot' on EC console -> system turns on 7) type 'powerbtn' on EC console -> system turns on Change-Id: I781cf3e665104192521b7fb9ff75a3c3e7f43464
* Fix polarity of radio-disable GPIOsRandall Spangler2012-05-092-4/+4
| | | | | | | | | | | | Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:8932 TEST=manual 1) gpioget with system off -> ENABLE_WLAN = 0, RADIO_ENABLE_* = 0 2) gpioget with system on -> ENABLE_WLAN = 1, RADIO_ENABLE_* = 1 Change-Id: I397a195b4539083c622b85d63703c334cae931fb
* Merge "stm32: add flash programming support"Gerrit2012-05-091-0/+3
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| * stm32: add flash programming supportVincent Palatin2012-05-091-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implements the on-chip flash erasing and writing functions. The actual writing is done from a routine in internal RAM (using the special .iram.text section) with interrupt disabled as we cannot read flash during the writing process. The write-protect feature is only lightly tested. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=chrome-os-partner:8865 TEST=run on Daisy, from the EC console, use flasherase and flashwrite commands and observe the results using rw command. Change-Id: I4c64cf28b23df52b18500b42a32a7d3668d45ba6
* | Make CPU_PROCHOTn high-Z (input) unless we're driving it low.Randall Spangler2012-05-081-1/+2
| | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:9563 TEST=manual Measure +3VALW power before and after change with system in S5. Should drop by ~50mW. Change-Id: I264694a80b2e558e46708de6ab1bfb146f79eb68
* | Add gpio_set_flags() and system_get_board_version()Randall Spangler2012-05-081-1/+6
|/ | | | | | | | | Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:9117 TEST=version; board version should be 0 on proto1 and 1 on EVT Change-Id: Ic64ad0d009151fbda09f5c1605ef50ae708cb6ae
* Add GPIO for PCH SRTCRST#Randall Spangler2012-05-072-3/+5
| | | | | | | | | | | | In case ctl decides to put it on a separate GPIO, he'll use PC7. If he doesn't, we can reclaim this GPIO. Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:7576 TEST=gpioget; signals should be present. PCH_SRTCRSTn should be 1. Change-Id: I4ca4437515d62c36d00fd28093ca41e806ce351a
* Add GPIOs for WLAN power control and PCH RTCRST#Randall Spangler2012-05-072-0/+10
| | | | | | | | | Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:7576 TEST=gpioget; signals should be present. PCH_RTCRSTn should be 1. Change-Id: Ibdfbf555c0bb919a1a459308b5d832b50df2ffe3
* Add GPIOs for EVT board version stuffing resistorsRandall Spangler2012-05-072-2/+8
| | | | | | | | | Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:9117 TEST=gpioget; signals should be present Change-Id: I27473d4d4e0a0b2832ffe3b3dde7cd487367390e
* Initial Snow board portDavid Hendricks2012-05-044-0/+223
| | | | | | | | | | | | | | | Mostly stolen from Daisy. Notable differences: - No SYSCFGEN required for external interrupts ? - No GPIO H bank on STM32F100, OSC_IN and OSC_OUT are not available --> CODEC_INT and ENTERING_RW signals are missing BUG=None TEST=Tested on ADV2/Snow, able to see EC serialconsole Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: I955e2ff180d064294d67b630ae2ee6cfcfe52ab9
* daisy: fix a bug in the GPIO enum listingDavid Hendricks2012-05-041-2/+0
| | | | | | | | | | | These GPIOs should have been removed in fd5d6c. BUG=Yes. TEST=built a new image and booted Daisy-EVT1 Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: Idce4384cdbe548c2e4fe2be8b52e4275445c9f1b
* daisy: Rename power signals to indicate polaritySimon Glass2012-05-032-4/+4
| | | | | | | | | | | | | | | | | GPIO_KB_PWR_ON and GPIO_PMIC_PWRON are active low, so add _L to each name to make this clearer. BUG=chrome-os-partner:9424 TEST=very ad-hoc: 1. build and boot on daisy, flash U-Boot with USB using 'cros_bundle_firmware -w usb', inserting daisy USB cable when it says 'Reseting board via servo...' 2. Press cold reset, then power on, see that it powers on 3. Then hold power-on for 8 seconds and see that it power off 4. XPSHOLD function not tested yet Change-Id: Ibdc0064477c36e8658ef5605cdd5811c2283aff9 Signed-off-by: Simon Glass <sjg@chromium.org>
* Fix a bug in temperature sensor address definitionVic Yang2012-05-031-2/+2
| | | | | | | | | | | | The address of charger temperature sensor and memory temperature sensor are interchanged. Fix this in this CL. Signed-off-by: Vic Yang <victoryang@chromium.org> BUG=chrome-os-partner:9450 TEST=Manual Change-Id: I20ae4d39ef13992ca7cac32bb2e6be12e195731e
* remove deprecated stm32-based boardsVincent Palatin2012-05-028-335/+0
| | | | | | | | | | | We no longer support ADV EVT0 board and Discovery reference design. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=None TEST=make BOARD=daisy && make BOARD=link Change-Id: I7eb81e5271c070b17f018ac9c14491f1804c0e08
* daisy: EVT1 pin mappingDavid Hendricks2012-05-021-7/+7
| | | | | | | | | | | This modifies the existing daisy's board.c to use the new pin mapping. BUG=None TEST=Tested on Daisy-EVT1 Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: I717ce78df1ed29843d1498e979956c6ffdb05e80
* introducing chip variant for stm32 family [2/3]Vincent Palatin2012-05-013-0/+3
| | | | | | | | | | | | Add a parameter to define the chip variant and pass it to build/make processes. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=chrome-os-partner:9057 TEST=make BOARD=daisy ; make BOARD=adv ; make BOARD=discovery Change-Id: I87b65b582ed5fc2cf5966446e15224ac15e328e9
* introducing chip variant for stm32 family [1/3]Vincent Palatin2012-05-016-23/+23
| | | | | | | | | | | | just rename STM32L to STM32. Most of the STM32L15x code is common with STM32F1xx. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=chrome-os-partner:9057 TEST=make BOARD=daisy ; make BOARD=adv ; make BOARD=discovery Change-Id: I819eff5fcd23deff57f5f6dedcf37e6c421b96c2
* stm32: fix ADV compilationVincent Palatin2012-05-012-4/+4
| | | | | | | | | | | power related GPIO has been renamed, update the board definitions. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=None TEST=make BOARD=adv Change-Id: I2f0e1e9e93af22c1a6f64f354336bf0c30e9c5cd
* daisy v1.02: power sequencing updatesDavid Hendricks2012-04-272-4/+4
| | | | | | | | | | | | | | | | | | | | | | | Note: This will not work on older (0.94 boards). - Use power button (KB_PWR_ON) to drive power sequencing events and disable EC_PWRON. This is because EC_PWRON and KB_PWR_ON shared an external interrupt line. Daisy v2.x will fix this so that both can be enabled. Note: KB_PWR_ON is active low, wihle EC_PWRON is active high. - Relay power button state to PMIC. Also, since we are driving PMIC_PWRON instead of PMIC_ACOK now, so updated the naming. - Add a keyboard power button debounce period to avoid accidentally powering the system back on after keyboard power-off. Signed-off-by: David Hendricks <dhendrix@chromium.org> BUG=None TEST=tested on daisy (frh@ verified behavior using a scope) Change-Id: I5338eebe42c9b43a07af371a450db23276b2a574
* link: enable +5V always-on at startupVincent Palatin2012-04-272-0/+2
| | | | | | | | | | | | | | | | | | | The EVT boards will have an enable signal for the +5V always-on rail connected to GPIO PK4. Just turn it on at startup to ensure that EVT boards will run out of the box with the current EC firmware. (PK4 is a test point on proto-1 board, this should be harmless). We can later implement fancier power saving scheme by enabling it only when we enter S3. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=chrome-os-partner:9284 TEST=boot Linux kernel on Link proto-1 and Link-1 proto-1 reworked with +5V Always-on enable on PK4. Change-Id: I26527480c7cd364f3fabcaabaadd079a332f9c1c
* Fix test configurations build errorsVincent Palatin2012-04-2510-10/+30
| | | | | | | | | | | | | fix small modularity issues to ensure we are able to compile all boards in "tests" configuration. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=chrome-os-partner:8546 TEST=make BOARD=link tests && make BOARD=bds tests make BOARD=daisy tests && make BOARD=adv tests && make BOARD=discovery tests Change-Id: I9eed0195af6bfd3b47ef74e3cb27966c4365c345
* stm32l: set SYSCFGEN for boards using stm32lDavid Hendricks2012-04-253-4/+5
| | | | | | | | | | | | This sets the SYSCFGEN bit. Writes to external interrupt config registers (SYSCFG_EXTICRn) will not stick unless this is set. Signed-off-by: David Hendricks <dhendrix@chromium.org> BUG=none TEST=tested on daisy Change-Id: I9a92b424e9ac1f909206f89ed773248807619ab2
* Use console output instead of uart output for console commandsRandall Spangler2012-04-241-16/+16
| | | | | | | | | | | | This completes console output cleanup. The remaining calls to uart_puts() and uart_printf() actually need to be that way. Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:7464 TEST=manual Change-Id: Ib1d6d370d30429017b3d11994894fece75fab6ea
* Implement task profilingRandall Spangler2012-04-241-0/+1
| | | | | | | | | | | | | | Also tracks the distribution of IRQs, so we can see what's triggering interrupts. Task profiling is optional, enabled via CONFIG_TASK_PROFILING. Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:7464 TEST=taskinfo Change-Id: I266f2b49bff9648cda446210d5a302b460fec244
* Set BOOTCFG register to test valueRandall Spangler2012-04-242-0/+14
| | | | | | | | | | | | | | Needed for testing preprogramming chips Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:8769 TEST=manual hibernate 1; should reboot rw 0x400fe1d0; should print: read word 0x400fe1d0 = 0xfffffdfe Change-Id: I95b419d7285a0bf5204f95d1f68f64dc212bb39e
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