| Commit message (Collapse) | Author | Age | Files | Lines |
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BRANCH=big
BUG=chrome-os-partner:26533
TEST=emerge-nyan_big chromeos-ec; flash big board, verify
ec is alive and version is reported as big
Change-Id: Idbf84d029b5c7b7c198f8c4a2bd2a90d79524441
Reviewed-on: https://chromium-review.googlesource.com/188926
Tested-by: Katie Roberts-Hoffman <katierh@chromium.org>
Reviewed-by: Yung-chieh Lo <yjlou@chromium.org>
Commit-Queue: Katie Roberts-Hoffman <katierh@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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The charger task was holding this either on or off in S3, no matter what we
wanted. We really only need to set it at S3->S0 or S3->S5, or when the
lid opens or closes. The rest of the time we should be able to turn it off
and on with gpioset, for testing purposes.
BUG=chrome-os-partner:26502
BRANCH=ToT
TEST=manual
Check the state with
gpioget TOUCHSCREEN_RESET_L
Open and close the lid, suspend the AP with powerd_dbus_suspend, etc. The
touchscreen should be on when the lid is open and the AP is in either S3 or
S0, off when the lid is closed or the AP is off.
Then
gpioset TOUCHSCREEN_RESET_L 1
gpioget TOUCHSCREEN_RESET_L
gpioset TOUCHSCREEN_RESET_L 0
gpioget TOUCHSCREEN_RESET_L
The change should persist as long as nothing else changes.
Change-Id: If7b6f809b1b28ae2699d0fbc6c9b2305fc57cbff
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/188869
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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Refactored the i2c unwedge code to place it in the common directory
so that any EC chip can use it.
Added to the STM32F and LM4 boards, code to automatically detect and
unwedge the i2c bus at the start of an i2c transaction. Note that STM32L
already had this ability.
To enable unwedging of the i2c port though, the gpio pins for SDA and
SCL must be defined in the i2c_ports[] array in the board.c file. This
allows the i2c module to bit bang the unwedging for the given port. If
SDA and SCL are not defined for the port, then the unwedge code will
not run.
BUG=chrome-os-partner:26315, chrome-os-partner:23802
BRANCH=none
TEST=Manual testing on machines with different EC chips.
Testing made extensive use of https://chromium-review.googlesource.com/66389
in order to force wedging of the i2c bus so that we can attempt to unwedge
it. Note that you can easily test if the bus is wedged by running i2cscan.
On pit and spring:
On pit, after each of the following, I verified that the bus was automatically
unwedged.
On spring, the unwedge only runs at reboot, so, for the non-reboot wedge
commands, I manually ran console command unwedge, and verified that the bus
became unwedged.
(1) Bit bang a transaction but only read part of the response.
Command to wedge: i2cwedge 0x90 0 2 2
(2) Bit bang a transaction to do a "write" and stop while the other side is
acking. Command to wedge: i2cwedge 0x90 0 1
(3) Same as (1) but do a reboot instead of returning and see
that the unwedge works at init time w/ no cancelled transactions.
Command to wedge: i2cwedge 0x90 0 6 2
(4) Same as (2) but do a reboot instead of returning and see
that the unwedge works at init time w/ no cancelled transactions.
Command to wedge: i2cwedge 0x90 0 5
On glimmer:
Added code to call i2c_unwedge in accel_init(). Then tested unwedging the
accelerometer with the following. One extra difficulty testing this with
the accelerometer is that sometimes the bit you stop on is high, which
means it won't be wedged at all, the next start transaction will reset
the bus. So, sometimes running i2cwedge won't wedge the bus and sometimes
it will depending on the acceleration data.
(1) Big bang transaction to do a "read" of accelerometer and stop partway:
i2cwedge 0x1c 0x0f 2 2
i2cscan to make sure bus is actually wedged
i2cunwedge
i2cscan to make sure bus is now unwedged.
(2) Bit bang transaction to do a "read" and stop partway, then reboot:
i2cwedge 0x1c 0x0f 6 2.
i2cscan to verify that the bus is working after the reboot.
Change-Id: Ie3328e843ffb40f5001c96626fea131c0f9ad9b1
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/188422
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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The EC had inputs with internal pullups on SUS_STAT#, SUSPWRDNACK, and
SLP_SX#. But we never used those signals for anything. The pullups
cost 1.5 mW power in S3. So, remove those signals and their pullups.
They can be turned back on via CONFIG_CHIPSET_DEBUG.
BUG=chrome-os-partner:25568
BRANCH=rambi
TEST=build with and without CONFIG_CHIPSET_DEBUG. Verify gpioget and
powerindebug show the signals only when it's defined.
Change-Id: I0851243615c91a3aa8aa1b28df70809b578d2e74
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/188389
Reviewed-by: Dave Parker <dparker@chromium.org>
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Added rotation of accelerometer data into a standard reference frame
so that the host does not have to know about the orientation of the
sensors.
Also added a calibration routine to calibrate the rotation matrix to
get to the standard reference frame. Cleanup up calibration in the
process to make it more user friendly.
Changed the default accelerometer sampling rate to 100Hz.
BUG=chrome-os-partner:25599
BRANCH=rambi
TEST=Tested the full calibration routine on a glimmer at my desk.
Used 'taskinfo' and verified that the higher sampling rate does not
bog down the EC. I found that the motion sense task is running for
about 200ms every 10 seconds, so about 2% CPU load.
Change-Id: I9ca1a4252f62a54016009c7d5e43b4cb1adf7e1d
Original-Change-Id: Id554511f7cc9549dfc9ed2d6337216bfa639359d
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/187172
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/188385
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This was always supposed to be open drain.
BUG=chrome-os-partner:22870
BRANCH=ToT,samus
TEST=manual
Try turning it off and back on again. ;-)
gpioset TOUCHSCREEN_RESET_L 0
gpioset TOUCHSCREEN_RESET_L 1
gpioset TOUCHSCREEN_RESET_L 0
Change-Id: I5e2a49c979294f68b86e2c91d2ccee5f6128ef5a
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/188045
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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BUG=chrome-os-partner:25977
BRANCH=None
TEST=Run 'adc' console command on a heavily loaded system while
charging the battery. The current reported should be around the
CONFIG_CHARGER_INPUT_CURRENT limit.
Change-Id: I1b4089d00182ce7d286b387361a63edade626f38
Original-Change-Id: I18e5bbb0a45312afbcb7d989517a86b97646c2da
Signed-off-by: Dave Parker <dparker@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/187018
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/187887
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Previously, the AP could only set the current wireless power state.
It couldn't determine what the EC would do in S3, nor could it get the
current wireless power state. Extend the wireless command to do so,
and add an EC console command to aid in debugging.
BUG=chrome-os-partner:25655
BRANCH=rambi
TEST=manual; expected numbers are from EC 'wireless' command
AP off -> 0x0, 0x9
AP on -> 0xd 0x9
AP suspended -> 0x9 0x9
AP on -> 0xd 0x9
ectool wireless 0x1 -> 0x1 0x9
ectool wireless 0xd -> 0xd 0x9
ectool wireless 0 0 0 0 -> 0xd 0x9 (and prints 0xd 0x9 to root shell)
ectool wireless 5 -1 -1 0 -> 0x5 0x9
AP suspended -> 0x1 0x9 (doesn't turn on 0x8, just turns off 0x4)
AP on -> 0xd 0x9
ectool wireless 0 0 0 -1 -> 0xd 0x0
AP suspended -> 0x0 0x0
AP on -> 0xd 0x9
Change-Id: I8ead2d4a4423b51ec4f638bf94c62de98726b25c
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/187273
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Added unit test for motion_sense lid angle calculations.
Added unit test for math_util arc_cos() function.
BUG=none
Original-BUG=chrome-os-partner:25640
BRANCH=rambi
TEST=make buildall
Original-Change-Id: I35debf6fc0e2d9996debc2ede175acaa060df627
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/186720
Reviewed-by: Vic Yang <victoryang@chromium.org>
(cherry picked from commit 55c3e8ee14693d6d667b5d21f0dcbb14d185ccbe)
Change-Id: I017315128f318424cd3000affae785c69afd29d6
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/187434
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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Nyan uses common/charge_state instead. So, fix the dependence.
Since snow/spring/pit are using common/pmu_tps65090_charger, keep them.
BUG=None
BRANCH=Nyan
TEST=build and works fine on Nyan 3.2
Change-Id: I985f7980578ac22602b1fbffa51edf039078bc05
Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/186337
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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Samsung change the temperature range in battery discharing state from (0
<=temp < 100) to (-20 <= temp < 70) from this year. That's why we have to
change the battery_temperature_range structure value as soon as possible
so that our reliability team check the battery.
BUG=chrome-os-partner:25731
TEST=Boot on the pit / pi and then check the battery is working or
not in the oven.
BRANCH=pit
Change-Id: I3289d22176af043e80a881f1626da386e823d857
Signed-off-by: Jaehoon Kim <jh228.kim@samsung.com>
Reviewed-on: https://chromium-review.googlesource.com/186040
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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BUG=None
BRANCH=rambi
TEST=None
Change-Id: I702173af23e6207129149bdb83ec7116fec8af66
Signed-off-by: Dave Parker <dparker@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/185394
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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cutoff() returns 0 on success, not non-zero.
BUG=chrome-os-partner:25646
BRANCH=rambi
TEST=ectool batterycutoff succeeds
Change-Id: Icca0c53aba82381b73dd679de5df3a97153d0662
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/185737
Reviewed-by: Benson Leung <bleung@chromium.org>
Reviewed-by: Dave Parker <dparker@chromium.org>
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This gives the AP a way to see that temperature for DPTF. Alarm
thresholds were defined on a per-sensor basis, so they come along for
free.
BUG=chrome-os-partner:25585
BRANCH=rambi
TEST=temps command shows same temp for battery as battery command (other
than rounding error; battery command shows with 0.1C accuracy).
'ectool temps all' shows the battery temp as the last temperature.
Unplug battery and temps command shows error for the battery temp,
as does 'ectool temps all'.
Change-Id: I1bce72f164d9fb1be631e7241a4ea24ddf409d7a
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/185444
Reviewed-by: Dave Parker <dparker@chromium.org>
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This is experimental for now; the capsense chip simply reports its buttons
as the number keys on the keyboard (1-8).
BUG=chrome-os-partner:23382
BRANCH=samus,ToT
TEST=manual
To test, you'll need a reworked and correctly programmed capsense module.
Boot the system, and switch to VT2. Touch the capsense bar and you'll see
the input appear on the console as though you were typing numbers.
Note that the capsense hardware is still buggy. Refer to the bug for
workarounds.
Change-Id: I4c3a8b70b8197ffd538c38c59c9336383365afa7
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/185434
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Dave Parker <dparker@chromium.org>
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Green when charged and ext. power plugged in.
Orange when charging.
Blinking orange if there is a charging/battery related error.
Blinking green if in "charge force idle mode" in the factory.
Off otherwise.
BUG=chrome-os-partner:23634
BRANCH=rambi
TEST=test each of the states above
To fake battery error, unplug battery and wait 30 secs
To force idle, 'ectool chargecontrol idle'
Change-Id: I85fff72d1df85bbbaa1da66572f44f58a960244e
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/185240
Reviewed-by: Dave Parker <dparker@chromium.org>
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BUG=chrome-os-partner:24370
BRANCH=tot
TEST=Run button unit test.
Orig-Change-Id: I61b4a6624d62831ce0bfdf7a0f36a45349b37f96
Signed-off-by: Dave Parker <dparker@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/184544
Reviewed-by: Randall Spangler <rspangler@chromium.org>
(cherry picked from commit f6426cc21c20a4f876cff28b9ce7e3115f0b054a)
Change-Id: I4face9bf0797a91ec8bef390093aab8e3d8f97ab
Reviewed-on: https://chromium-review.googlesource.com/185243
Tested-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Commit-Queue: Randall Spangler <rspangler@chromium.org>
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From DV2 board of pit, we'll use 3 color-LED instead of power LED on keyboard.
So, we have to add the function to control 3 color-LED in pmu driver.
BUG=chrome-os-partner:24855
TEST=Tested on the pi and pit board about all power status.
BRANCH=pit
Change-Id: I7b1df39de8fa56eab73779abfa52cf8f72427b44
Signed-off-by: Jaehoon Kim <jh228.kim@samsung.com>
Reviewed-on: https://chromium-review.googlesource.com/181588
Tested-by: Katie Roberts-Hoffman <katierh@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Queue: Wonjoon Lee <woojoo.lee@samsung.com>
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BUG=chrome-os-partner:24649
BRANCH=baytrail
TEST=Boot target device w/o battery. There should be no 30 second
delay prior to boot.
Change-Id: If7a60919701d1c241670d0b32e04f3e188a643f1
Signed-off-by: Dave Parker <dparker@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/182921
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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This should reduce EC power consumption in S3 and S5.
BUG=chrome-os-partner:25377
BRANCH=baytrail
TEST=make sure jtag is not active (not running openocd via servo)
boot system; suspend system
wait 60 seconds; should see "Disabling console in deep sleep"
type on console; should still allow typing
wait 60 seconds; press spacebar; should still resume from suspend
Change-Id: I47e33e158c1b90077f944a6af4374f39efa68d94
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/184165
Reviewed-by: Alec Berg <alecaberg@chromium.org>
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This adds hibernation support. The chip can be waken by either GPIO or a
timer. The maximum delay allowed is ~2 hours.
BUG=chrome-os-partner:24107
TEST=hibernate and wake by GPIO
TEST=hibernate and wake by timer
BRANCH=None
Change-Id: I1e064638a5008894a002a06a738bf6104f18636d
Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/181202
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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We noticed this on a baytrail board, but the same problem exists in
haswell as well. And while looking there, found that we skipped the
S5G3 state if the 5V rail failed to come up.
Fortunately, these are all rare corner cases; rails will always come
up on a good system. So this only affects systems during bringup and
factory, not devices in the field.
BUG=chrome-os-partner:24915
BRANCH=rambi (and technically haswell, but may not be worth merging)
TEST=Try booting a system with a bad power rail; see that SUSP_VR_EN=0
after the system fails to boot.
Change-Id: Ifd10841d298a0f2510a8b182250b717ea5643c99
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/183733
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Previously, the 5V rail was disabled unconditionally in the S0->S3
transition. Now, the rail is left powered if one or both of the USB
ports are powered.
BUG=chrome-os-partner:25178
BRANCH=rambi
TEST=Modify the OS to leave USB ports powered in S3. Then suspend. On
the EC console, 'gpioget pp5000_en' should be 1.
Change-Id: I3c73f3fe228e940317c0da7330f117c7ab0a6d0c
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/183548
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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BUG=None
BRANCH=None
TEST=Verify ectool i2cwrite, i2cread, i2cxfer commands fail
when EC is write protected.
Signed-off-by: Dave Parker <dparker@chromium.org>
Change-Id: Ie7c3a6ba1985c09f0cf05171eb32320191aebd8a
Original-Change-Id: Ibde29c92a1487932eb273701bdf017b4f92c646d
Reviewed-on: https://chromium-review.googlesource.com/182757
Commit-Queue: Dave Parker <dparker@chromium.org>
Tested-by: Dave Parker <dparker@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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BUG=None
BRANCH=None
TEST=Verify ectool i2cwrite, i2cread, i2cxfer commands fail
when EC is write protected.
Change-Id: I1dc09d77e54928c2e3122f724ce340717c4bf066
Original-Change-Id: I0393ea64c704dfc4ad1f234b39bccf2de1546c60
Signed-off-by: Dave Parker <dparker@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/182638
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/182756
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For the better naming for power/common.h, we rename CONFIG_CHIPSET_X86
to CONFIG_POWER_COMMON (no one is actually using it). But keep
CONFIG_CHIPSER_TEGRA for power/build.mk.
BUG=chrome-os-partner:25068
BRANCH=nyan,falco,link,peppy,rambi,samus,squawks
TEST=build only
Change-Id: Ibf1a4c24088dfddac39b38a95b3b887c195152d5
Signed-off-by: Yung-Chieh Lo <yjlou@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/182732
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Some WiFi devices do not tolerate losing power in suspend
and will not function properly after resume if they have
lost power.
Enable this on the Rambi device.
BUG=chrome-os-partner:24114
BRANCH=baytrail
TEST=complete mutiple successful suspend/resume cycles on rambi
and ensure that wifi continues to function and not cause a crash.
Change-Id: Id421f3138e429b247bfb3f5ffb92a06c0353bb97
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/183047
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Integrate with power/common.c -- a real state machine now. Also remove
duplicate and unused functions/consts.
BUG=chrome-os-partner:24831
BRANCH=nyan
TEST=on nyan rev 3.12.
re-plug AC: PASS, power on 2
reboot: PASS, power on 2
power off (S5), power on: PASS, power off 4, power on 5
power off (G3), power on: PASS, power off 4, power on 5
lid close / power off (S5)/ lid open: PASS, power on 3
lid close / power off (G3)/ lid open: PASS, power on 3
press power button and release: nothing happens after 15s.
button off (S5)/ on: PASS, power off 3, power on 4
button off (G3)/ on: PASS, power off 3, power on 4
power off (S5)/ button on: PASS, power off 4, power on 4
power off (G3)/ button on: PASS, power off 4, power on 4
button off (S5)/ power on: PASS, power off 3, power on 5
button off (G3)/ power on: PASS, power off 3, power on 4
button off (S5)/ lid open: PASS, power off 3, power on 3
button off (G3)/ lid open: PASS, power off 3, power on 3
is off, long press button (60s): power on 4, too long, shutdown, stay off
is on, long press button (60s): power off 3, stay off
apreset cold: entered to S5, power off 3, power on 5
apreset warm: power state is not changed, but reboots to BIOS.
Change-Id: Ie12fa4f79b6156f71f89155b2b01880914809c75
Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/182348
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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BUG=chrome-os-partner:25031
BRANCH=rambi
TEST=Manually
make BOARD=peppy
make BOARD=falco
make BOARD=rambi
make BOARD=squawks
On rambi and squawks, connect charger
ectool chargecontrol discharge
ectool i2cread 16 0 0x16 0x0a
It should return 16-bit negative integer.
Change-Id: I8a8dfa90d2ad82595ac7a420c3c8ffc13b12cde6
Signed-off-by: Justin Chuang <jchuang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/182586
Reviewed-by: Dave Parker <dparker@chromium.org>
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Change rambi LED id to battery and fix led command.
BUG=chrome-os-partner:24980
BRANCH=None
TEST=Manually,
ectool led power query => error
ectool led battery query => success
ectool led red => red
ectool led green => green
ectool led off => off
ectool led auto => default behavior
Change-Id: I151d63a010434ae8cd21b0ae0d935bb9d8c084c7
Signed-off-by: Justin Chuang <jchuang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/182275
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vic Yang <victoryang@chromium.org>
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From DV2 board of pit, we'll use 3 color-LED instead of power LED on keyboard.
So, we have to remove pwm and power_led task from pit branch.
BUG=chrome-os-partner:24855
TEST=Tested on the pi and pit board about all power status.
BRANCH=pit
Change-Id: I875567d8f7d544cb5b9d6057b94c26d1989b0c67
Signed-off-by: Jaehoon Kim <jh228.kim@samsung.com>
Reviewed-on: https://chromium-review.googlesource.com/181607
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Tested-by: Randall Spangler <rspangler@chromium.org>
Commit-Queue: Randall Spangler <rspangler@chromium.org>
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Instead of requiring a GPIO definition, default to using the internal
SCI pin control.
BUG=chrome-os-partner:24550
TEST=Trigger SCI and verify with logic analyzer
BRANCH=None
Change-Id: I13ac3b8f1031d3c56ea0b8f6a6ed0c1aa4e77bb1
Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/182010
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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Vboot hash calculation takes ~350 ms during EC boot. Since the hash
task is higher priority than the hook task, this starves all the hooks
during boot.
We could, in theory, fix that simply by swapping the priority of the
hook and hash tasks. But then watchdog detection (in the hook task)
wouldn't detect hangs in the hash task.
A better fix (implemented here) is to convert the hashing operation to
a series of deferred function calls. This gets rid of the hash task
entirely, and allows all pending hooks and other deferred function
calls to take place between each chunk of hashing.
On STM32-based boards, we need to bump up the hook task stack size,
since hashing is called from several layers deep in the hook task
instead of at the top of its own task, but this is still a net win of
several hundred bytes of SRAM.
BUG=chrome-os-partner:24892
BRANCH=rambi
TEST=Boot EC; look for "hash start" and "hash done" debug output.
'taskinfo' shows at least 32 bytes of unused stack for HOOKS task.
'hash ro' runs properly from EC console.
Change-Id: I9e580dc10fc0bc8e44896d84451218ef67578bbe
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/181954
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The external pull-up resistors are too weak, and cause slow-down on I2C
speed. Let's enable internal pull-up to compensate this.
BUG=chrome-os-partner:24389
TEST=Measure I2C speed with scope, and see better slew rate.
BRANCH=None
Change-Id: Iefb5fca3c88250bbd8cad29d7998d590a7cc7c35
Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/181999
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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Rename x86_* to power_signal_* and X86_* to POWER_*.
BUG=chrome-os-partner:24832
BRANCH=link,falco,samus,rambi,peppy,squawks,snow,spring,nyan
TEST=make -j buildall run_tests
Change-Id: Ifaa06391da5a483851ff56eca91fbf6d038dff0a
Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/181719
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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Initial support for the ITE IT8380 chip with the following peripherals :
- 8250-like UART module.
- HW timer (with a 128-us tick period).
- GPIO with pins initialization and edge interrupt support.
other functions are stubbed.
- Clock : basic fixed frequency setup only.
It also add the dev board configuration as a test vehicle.
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=chrome-os-partner:23575
TEST=make BOARD=it8380dev
on IT8380 dev board, use the EC serial console, use gettime from
console.
Change-Id: Id4bf37d1beb21d1a4bee404c9a0bc500025fe787
Reviewed-on: https://chromium-review.googlesource.com/175481
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Commit-Queue: Alec Berg <alecaberg@chromium.org>
Tested-by: Alec Berg <alecaberg@chromium.org>
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This matches the 33W adapter.
BUG=chrome-os-partner:23833
BRANCH=rambi
TEST=with partially-charged battery, 'charger' command shows I_in < 1700
Change-Id: I9db81757531e16878eccd4081ce82e22e2a7b9f8
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/181764
Reviewed-by: Alec Berg <alecaberg@chromium.org>
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Implement LED color policy (crosbug.com/p/23957)
Update battery vendor information (crosbug.com/p/24684)
BUG=chrome-os-partner:24885
BRANCH=rambi
TEST=manual
system on, lidclose -> power LED off
system on, lidopen -> power LED on
system suspended -> power LED blinks green every 2 sec
system suspended, lid closed -> power LED off
system off -> power LED off
plug AC in, battfake 95 -> charging LED green
plug AC in, battfake 94 -> charging LED orange
unplug AC, battfake 10 -> charging LED off
unplug AC, battfake 9 -> charging LED blinks orange
battcutoff -> after a few sec, system powered down
plug back in AC -> system comes back on
charger -> I_in < 1700
Change-Id: I89161e2c024d85197b8612a40a61dd50c106549e
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/181755
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The SERIRQ signal will now be high-Z on the EC, which removes a
leakage path. This requires the BIOS to use PM3 for its keyboard IRQ.
BUG=chrome-os-partner:24424
BRANCH=rambi
TEST=boot system; keyboard still works
Change-Id: I0acf425125ced11a9ef6da58ee49979b83c92d5c
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/181718
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After this change, only Rambi 2.0 boards will boot properly.
This cleanup is necessary before supporting other Baytrail systems.
BUG=chrome-os-partner:24414
BRANCH=rambi
TEST=as soon as I get a 2.0 board
Change-Id: Ic9e3afcee9dae5c0b7f31a7aa4500b2572ba92c6
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/181754
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Renaming file names is the first step. Please see issue tracker
for more details.
BUG=chrome-os-partner:24832
BRANCH=link,falco,samus,rambi,peppy
TEST=build all x86 boards.
make clean BOARD=link && make -j32 BOARD=link && \
make clean BOARD=falco && make -j32 BOARD=falco && \
make clean BOARD=samus && make -j32 BOARD=samus && \
make clean BOARD=rambi && make -j32 BOARD=rambi && \
make clean BOARD=peppy && make -j32 BOARD=peppy
Change-Id: I3a296a0c14f6bebefa858438b1320061ac71dd38
Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/181400
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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It will be used by all variants of Rambi, so #ifdef BOARD_RAMBI is too
restrictive.
BUG=chrome-os-partner:24864
BRANCH=rambi
TEST=boot rambi 1.5 board; plug in USB mouse
Change-Id: I0ff02077388a6c6621c5746a693dde894cf8ad77
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/181682
Reviewed-by: Alec Berg <alecaberg@chromium.org>
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KBD_IRQ_NEW_L (added for Rambi 2.0) has a pull-up resistor and should be
open drain.
TEST=None
BUG=chrome-os-partner:24760
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Ibf1beff3306c074f9f135b1bee82e299edf2380b
Reviewed-on: https://chromium-review.googlesource.com/181227
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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Old code reset some GPIO configurations with af->flags = 0 while
gpio_config_module(). This is bad because it could lead unexpected
behavior on the bus.
New code accepts GPIO_DEFAULT flag so that it doesn't touch the
GPIO setting while configuring alternate functions. This should not
effect other boards unless the GPIO_DEFAULT is set on that board.
BUG=chrome-os-partner:24607
BRANCH=nyan
TEST=run on nyan rev 3.12. No "SPI rx bad data" at boot. UART and i2c good.
Change-Id: Id451cfae21e1d764452429dc5adfe1317ff5b140
Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/181135
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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Follow up Randall's CL 616e709. Note that the nyan warm reset is in
another CL.
BRANCH=nyan
BUG=chrome-os-partner:24558
TEST=See test procedure and results on comment #7 of issue 24558.
Note that the suspend tests cannot be done because my nyan cannot suspend.
Change-Id: I77c59cab177bc2c6fdf9bb8828937fc7b84e6d76
Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/181177
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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ADC driver for MEC1322 with ADC interrupt support.
BUG=chrome-os-partner:24107
TEST=Read single channel
TEST=Read all channels
BRANCH=None
Change-Id: I89d196c7fd78e736575e2c368b65cfb1ec651004
Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/180832
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This lowers, the WARN, HIGH, and HALT temp thresholds
for x86 boards to below their CONFIG_PECI_TJMAX value.
Also lowers the FAN_MIN and FAN_MAX temps by 5 degrees on
Haswell boards to compensate for lowering TJ_MAX by 5 degrees
in an earlier patch.
BUG=chrome-os-partner:24455
BRANCH=none
TEST=Manual. Run boards without a fan and without any host-side
throttling. Verify that board either reaches a steady state temp
due to throttling or hits SHUTDOWN and turns off before EC reset
is triggered.
Change-Id: I499baa0b4100201525e69752af3465feb592262c
Signed-off-by: Dave Parker <dparker@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179886
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
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AP throttling in the thermal task ends up calling a pretty deep nested
set of calls, and in the worst case can overflow the stack. Bump up
the stack size for the hook task on x86 platforms to compensate.
BUG=chrome-os-partner:24536
BRANCH=peppy/falco
TEST=taskinfo shows hook task increased from 512 to 640 bytes stack
shmem shows at least 4000 bytes free
Change-Id: I63da7c47b993c935d895f91d787844655071da0d
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/180684
Reviewed-by: Bill Richardson <wfrichar@chromium.org>
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So that Tegra wants to drive the PMIC_WARM_RESET_L low it will not be
fighting the EC.
BUG=None
BRANCH=None
TEST=Verified on the board rev 3.12
Change-Id: I5980a3ba096c152a4ccc28ad64e675c53b7cb337
Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/180520
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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This make minor syntactic changes and renames some camel-cased symbols
to keep checkpatch from complaining. The goal is to reduce the
temptation to use 'repo upload --no-verify'.
This is a big furball of find/replace, but no functional changes.
BUG=chromium:322144
BRANCH=none
TEST=build all boards; pass unit tests
Change-Id: I0269b7dd95836ef9a6e33f88c003ab0f24f842a0
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/180495
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