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* g: provide API to disable clock jitterVadim Bendebury2018-11-051-32/+59
| | | | | | | | | | | | | | | | | | | | | | | Sometimes it is necessary to disable clock jitter, this patch introduces a new chip API which would allow to do just that. Actual disable is possible only if the chip is not yet running on lowered security level. BRANCH=cr50, cr50-mp BUG=b:75976718 TEST=with the rest of the patches applied verified that it is possible to disable clock jitter during startup to be able to generate ITE SYNC sequence. Also observed expected console output, like: [0.007225 init_jittery_clock_locking_optional: run level high, \ request to enable] Change-Id: I624d781a961cdc17749de4fa80fad0f682537e01 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1305117 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* g:prevent SOF calibration debug message spewVadim Bendebury2017-10-171-12/+7
| | | | | | | | | | | | | | | | | | | It turns out the code logic is not exactly correct: the range for coarse trim values is 0..0xFF. Use the fixed top of the range value and do not print messages if the value is at the range boundary. BRANCH=cr50 BUG=b:67788437 TEST=Observed occasional messages on the Cr50 console when plugging/unplugging Suzy-Q, but not the constant spew. Change-Id: I94ab581769ba8326346b636b1342136e98d61ff1 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/723981 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* g: add permission level checksMary Ruthven2016-11-041-1/+2
| | | | | | | | | | | | | | | | | | | The jittery clock and trng security features require high permissions to be initialized. In the future these initializations and the permission level drop may be moved to RO. This change adds permission level checks before trying to access any registers that require high permission, so when we update RO to change the permission RW can still function fine. BUG=chrome-os-partner:59107 BRANCH=none TEST=Move the permission drop to the beginning of main and verify the system still boots. Change-Id: I5b7cb856decd0640288ad3476f875ec9edc42635 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/405840
* cleanup: DECLARE_CONSOLE_COMMAND only needs 4 argsBill Richardson2016-08-241-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Since pretty much always, we've declared console commands to take a "longhelp" argument with detailed explanations of what the command does. But since almost as long, we've never actually used that argument for anything - we just silently throw it away in the macro. There's only one command (usbchargemode) that even thinks it defines that argument. We're never going to use this, let's just get rid of it. BUG=none BRANCH=none CQ-DEPEND=CL:*279060 CQ-DEPEND=CL:*279158 CQ-DEPEND=CL:*279037 TEST=make buildall; tested on Cr50 hardware Everything builds. Since we never used this arg anyway, there had better not be any difference in the result. Change-Id: Id3f71a53d02e3dc625cfcc12aa71ecb50e35eb9f Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/374163 Reviewed-by: Myles Watson <mylesgw@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cr50: TEMP: to be researched and removedVadim Bendebury2016-06-291-2/+4
| | | | | | | | | | BRANCH=none BUG=chrome-os-partner:54916 TEST=none Change-Id: Ie7fc68a0ad8f9459558d3af03f942b4accaeebaf Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/356590
* cr50: enable highsec jittery clockMary Ruthven2016-06-271-1/+1
| | | | | | | | | | | | | | | | | The highsec jittery clock was breaking the USB peripheral, because it would use bank values that mapped to frequencies less than 15MHz. This change modifies stepx16 to keep the bankvalues mapped to frequencies above 18MHz to ensure the USB peripheral can work with the high security jittery clock. BUG=chrome-os-partner:53952 BRANCH=none TEST=sudo flashrom -p raiden_debug_spi:target=AP -r test_img.bin Change-Id: If8b45583f2cd9272b6d1e79a06556724c25d6495 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/356192 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* g: Enable SOF calibration after first SOF tokenBill Richardson2016-06-081-4/+14
| | | | | | | | | | | | | | | | | | | | | | | Instead of enabling the SOF calibration at usb_init(), enable it only when the first SOF packet is seen following the usb_init(), as suggested in the recommendations document linked from the bug report. Also fix the code to do the right thing. The original reference code had errors. BUG=chrome-os-partner:50800 BRANCH=none TEST=make buildall; test on Cr50 After adding some instrumentation code, I see the SOF being detected and the calibration started. It only happens once after each usb_init() and only when the USB traffic begins. Change-Id: Id2b9a41d90ce9cc9e467fb759463d69a57bb5540 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/350371 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* Cr50: Enable the USB SOF clock auto-calibrationstabilize-8282.BBill Richardson2016-05-041-1/+161
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The timer clock nominally requires no firmware settings. It is tuned in manufacturing to be centered around 24MHz. However, it will potentially migrate away from 24MHz based upon variations in temperature and voltage. The variation is approximately 0.1-0.5MHz, based upon functional simulations, and backed up with observations in the lab. This CL enables a hardware feature to dynamically tune the timer clock if the device has an active USB port, by monitoring the SOF (start of frame) USB packets that are sent by the USB host every milllsecond with 500ppm accuracy. BUG=chrome-os-partner:50800 BRANCH=none TEST=make buildall; run on Cr50 hardware Verified that deep sleep, USB suspend/resume, etc continue to work with this enabled. Not too surprising, since I've never encountered a problem without it. In addition, I monitored XO_CLK_TIMER_CURRENT to see that the timer adjustments are being made while connecting and disconnecting from USB, entering andleaving sleep and deep sleep, etc. They are. Change-Id: I328b6416bc40ef8718815c5e09cf91ec1c6646f0 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/342145 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* Cr50: Enable jittery clockBill Richardson2016-05-031-0/+51
BUG=chrome-os-partner:52576 BRANCH=none TEST=make buildall; try on Cr50 I manually tested both highsec and highperf variants, as well as forcing the bootrom init to run. All the bank registers were loaded with meaningful values, and none of the SPI or USB functionality showed any problems. Change-Id: Ia91ba98ef4c667aec74195c4a7bbf72a5d1c8b2d Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/342030 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
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