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* g: add missing define for UART register UART_VAL.Marius Schilder2018-03-271-0/+1
| | | | | | | | | | | | | | | Holds most recent 16 oversampled values of rx and cts inputs. Signed-off-by: mschilder@google.com TEST=buildall -j8 BUG=None BRANCH=None Change-Id: I798b8c2ba645712600d7634769f418d81dec5f79 Reviewed-on: https://chromium-review.googlesource.com/981775 Commit-Ready: Marius Schilder <mschilder@chromium.org> Tested-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@google.com>
* g: restore DATA PID after USB suspend/resumeVincent Palatin2017-09-071-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In USB FS on a bulk/interrupt endpoint, the transactions normally toggles between DATA0 and DATA1 PIDs. After a USB suspend/resume cycle, we need to restart from the PID we were at before suspend. In our current code, when going to deep-sleep during USB suspend, we are re-initializing everything when the MCU restarts at each resume. So we set implicitly the PID to DATA0. The USB Hardware IP just silently discards the packet when the PID of an incoming OUT packet is not matching the expectation in the endpoint register. In order to preserve DATA PIDS, record the state of the PID toggling on each endpoint when going to deep-sleep and restore it during the USB initialization. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=b:38160821 TEST=manual, plug a HG proto2 on a Linux host machine and enable 'auto-suspend' for this USB device. Let it go to sleep and wake-it up by sending a U2FHID request. Repeat the process several times and see that the key answers every time (while it was failing after the second cycle before). Change-Id: I75e2cfc39f22483d9e9b32c5f8b887dbafc37108 Reviewed-on: https://chromium-review.googlesource.com/655238 Commit-Ready: Marius Schilder <mschilder@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* CR50: add a hardware backed GCM implementationnagendra modadugu2017-01-271-0/+3
| | | | | | | | | | | | | | | | | | | This change adds hardware support for AES128-GCM along with a subset of NIST test vectors. BRANCH=none BUG=chrome-os-partner:60833 CQ-DEPEND=CL:411535 TEST=tpmtest.py passes Change-Id: I93445684f6a910c35a9117eac6cb19d28067a021 Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/425002 Commit-Ready: Nagendra Modadugu <ngm@google.com> Tested-by: Marius Schilder <mschilder@chromium.org> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* Added additional macros for the TIMEUS module.Dom Rizzo2016-08-291-0/+17
| | | | | | | | | | | | | BUG=none BRANCH=none TEST=make buildall Change-Id: I5a63ae85441d492b7322a98bb05e42d9d236e005 Signed-off-by: Dom Rizzo <domrizzo@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/377150 Commit-Ready: Dominic Rizzo <domrizzo@google.com> Tested-by: Dominic Rizzo <domrizzo@google.com> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* cr50: fix wake pin handling when resuming from sleepMary Ruthven2016-07-281-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Cr50 was not waking up long enough after SPS_CS_L was asserted for the spi slave transactions to start and disable sleep. It also was not handling SYS_RST_L properly when it was asleep. This change sets SPS_CS_L to be an edge triggered wake up source instead of level triggered, because cr50 should just wake up on the edge and disable sleep until the spi transaction is done. It also adds sys_rst_l as a wakeup source. The sys_rst_asserted interrupt cannot be triggered while cr50 is asleep, so the pmu_wakeup_interrupt will call sys_rst_asserted if SYS_RST_L is low at resume. This change relies on the EC extending the delay in chipset_reset to be long enough for SYS_RST_L to still be asserted when cr50 resumes. BUG=chrome-os-partner:54331 BRANCH=none TEST=manual make sure suzyq is disconnected. verify ap boots up to the kernel after running 'gpioset SYS_RST_L 0' then 'gpioset SYS_RST_L 1' on the ec console. Check that cr50 goes to sleep when the AP is not trying to use the TPM. When cr50 is asleep pwrbtn + refresh still resets the system. Disable SYS_RST_L_IN as a wake source and verify the system verification fails and requests a recovery image. Change-Id: I807b1918842d96c9d2922aa33404d87ab28b9906 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/363606 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* g: report proper silicon versionVadim Bendebury2016-07-241-2/+0
| | | | | | | | | | | | | | There are two g chip versions in circulation currently, B1 and B2. Make the 'version' command properly report it. BRANCH=none BUG=none TEST=verified that both B1 and B2 report versions properly Change-Id: I1c5b9f0da0170cda2c636b857e92b9d3de165422 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/362643 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* g: Add GR_KEYMGR_HKEY_FRR to registers.hBill Richardson2016-05-161-4/+4
| | | | | | | | | | | | | | We'll need this shortly. Adding it now to make testing easier. BUG=none BRANCH=none TEST=make buildall Signed-off-by: Bill Richardson <wfrichar@chromium.org> Change-Id: I6a6636ad330bc17765966cee4962d16850a5d32c Reviewed-on: https://chromium-review.googlesource.com/344663 Reviewed-by: Dominic Rizzo <domrizzo@google.com> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* Cr50: Enable jittery clockBill Richardson2016-05-031-0/+6
| | | | | | | | | | | | | | | | BUG=chrome-os-partner:52576 BRANCH=none TEST=make buildall; try on Cr50 I manually tested both highsec and highperf variants, as well as forcing the bootrom init to run. All the bank registers were loaded with meaningful values, and none of the SPI or USB functionality showed any problems. Change-Id: Ia91ba98ef4c667aec74195c4a7bbf72a5d1c8b2d Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/342030 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* Cr50: Add DIO_PULL_UP and DIO_PULL_DOWN flagsBill Richardson2016-04-151-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In board/*/gpio.inc, we can specify pullups and pulldowns on pads connected to GPIOs, like so: GPIO(SOME_BUTTON, PIN(0,0), GPIO_INPUT | GPIO_PULL_UP) This adds flags to do the same thing for pads that connect to internal periperals: PINMUX(FUNC(UART0_RX), A1, DIO_PULL_UP) BUG=chrome-os-partner:51410 BRANCH=none TEST=make buildall; manual test on Cr50 I added these flags to the gpio.inc file and tested the result: PINMUX(FUNC(I2C0_SCL), B0, DIO_INPUT | DIO_PULL_UP) PINMUX(FUNC(I2C0_SDA), B1, DIO_INPUT | DIO_PULL_DOWN) The "pinmux" console command showed that the new flags took effect: Before: 400600a0: DIOB0 0 IN 400600a8: DIOB1 0 IN After: 400600a0: DIOB0 0 IN PU 400600a8: DIOB1 0 IN PD Change-Id: I1d212331431ef67b2f1bcece8729d092b9ad5ba8 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/339254 Reviewed-by: Dominic Rizzo <domrizzo@google.com>
* Cr50: Add console command "usb" for testingBill Richardson2016-04-071-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | This adds a command to connect or disconnect, and to switch the PHY between A or B. BUG=chrome-os-partner:52055 BRANCH=none TEST=make buildall; test on Cr50 Using a test board with both PHYs plugged in, try the various commands: usb off usb on usb a usb b The on/off option connects and disconnects, the a/b option switches between PHYs. You can see the state change on the console, or by running dmesg on the host. Change-Id: I4c77e9c586ce197dc99b0b50af7396c253a1a377 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/337706 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* Cr50: Specify pinmux wake sources in gpio.incBill Richardson2016-04-051-3/+12
| | | | | | | | | | | | | | | | | | | This adds (and uses) some additional flags for gpio.inc's PINMUX() macro, to configure specific pads as wake sources when the SoC is sleeping. BUG=chrome-os-partner:49955 BRANCH=none TEST=make buildall; test on Cr50 The sleep/deep sleep behavior is unchanged. This just replaces hard-coded wake sources with pads configured in gpio.inc and the chip/g/sps.c module. Tests from previous CLs still pass. Change-Id: I6608dc959524f42fd589feb804fa06f29cfd9b9c Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/336838 Reviewed-by: Dominic Rizzo <domrizzo@google.com>
* Cr50: Handle possible resume from deep sleepBill Richardson2016-03-301-0/+1
| | | | | | | | | | | | | | | | | | | | | | | A resume from deep sleep looks a lot like a cold boot, but there are some registers that need updating quickly. We need to disable the settings that triggered deep sleep so that it isn't accidentally invoked again, and we need to unfreeze any modules or pins that were frozen during the deep sleep. BUG=chrome-os-partner:49955 BRANCH=none TEST=make buildall; test on Cr50 Since we aren't yet triggering deep sleep, this doesn't do anything noticeable, which is the point. It shouldn't have any effect unless we are entering deep sleep and DON'T do this when it resumes. FWIW, I have tested that too, but it's coming in a later CL. Change-Id: I4b32fd2e24fe089d3f659154df26d275b41b4c1b Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/336450 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Cr50: Cleanup some of the GPIO handling codeBill Richardson2016-02-251-5/+0
| | | | | | | | | | | | | | | | | Just a bit of refactoring. This cleans up some macro definitions and error checking, and removes a duplicate list of GPIO signal names. BUG=none BRANCH=none TEST=make buildall, test on Cr50 No functional changes, so nothing new to test. Change-Id: Iecacc5a0b7da02aa9d0b94f171c70f0b73e8edd5 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/329303 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* g: Clean up pinmux initializationAnton Staaf2016-02-251-55/+7
| | | | | | | | | | | | | | | | | | | | | | Now that the pinmux information isn't packed into the GPIO alternate function table, we can expand it a bit and give the fields nice names, making the code easier to read and removing a number of bit packing macros defined in registers.h. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Verified on cr50 hardware CQ-DEPEND=CL:*249229 Change-Id: I9984bc37faf69b1ba9f1ba66a49596dd22e3b601 Reviewed-on: https://chromium-review.googlesource.com/328979 Commit-Ready: Bill Richardson <wfrichar@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org> Tested-by: Bill Richardson <wfrichar@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* cr50: adds the ability to configure muxed inout peripheralsEwout van Bekkum2016-01-281-0/+1
| | | | | | | | | | | | | | | | Adds the the code necessary to support muxed inout peripherals on cr50 like SPS and SPI0 by adding a new signnal to pin connection flag. Note these are for direct wired peripherals where no muxing is necessary, the input pads just need to be enabled. BRANCH=none BUG=none TEST=verified pinmux registers through m3 Change-Id: I1a375a3a14fb44fc4f9ced764fd2c54bb2b91e22 Signed-off-by: Ewout van Bekkum <ewout@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/323848 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Cr50: Add a few more symbolic names for constantsBill Richardson2015-12-111-4/+52
| | | | | | | | | | | | | | | | | | | No functional changes, just making the code prettier. BUG=chrome-os-partner:34893 BRANCH=none TEST=make buildall, manual Connect the Cr50 to my workstation via USB: * /bin/dmesg reports no errors * verify EP0 with lsusb -v -d 18d1:5014 * verify EP1 with './extra/usb_console -e 1 -p 5014' (reverses case of input text) * verify EP2 with the 'hid' command on the EC console (types a 'g') Change-Id: I1301c035eafc054567c1f317a80539197fcdeef4 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/317354
* Cr50: Clean up the GINTSTS USB macrosBill Richardson2015-12-011-9/+2
| | | | | | | | | | | | | | | | | This just replaces a few manually created macros in chip/g/registers.h with a more programmatic version based on names in chip/g/hw_regdefs.h. BUG=chrome-os-partner:34893 BRANCH=none TEST=make buildall; run it No new functionality, just refactoring. Change-Id: I73ee2ee1ee3f53a0939000822c552deace46f154 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/314937 Reviewed-by: Dominic Rizzo <domrizzo@google.com>
* Cr50: Replace magic numbers for GGPIO controlBill Richardson2015-12-011-0/+38
| | | | | | | | | | | | | | | | | | Use some meaningful macro names instead of just raw numbers when selecting the correct USB phy port. Also we only need to do this once, since it should be sticky through anything short of a complete power down. BUG=chrome-os-partner:34893 BRANCH=none TEST=make buildall; run it No new functionality, just refactoring. Change-Id: If6ea2b9d9a62bf6ce4adaed1c5aac1f66013ebeb Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/314938 Reviewed-by: Dominic Rizzo <domrizzo@google.com>
* cr50: SHA1 and SHA256 implementation with hardware supportnagendra modadugu2015-11-251-0/+4
| | | | | | | | | | | | | | | | | | | | | | | This change includes hardware and software support for SHA1/256 on CR50. When running in the RO image, only hardware sha256 support is included. When running in the RW image, the code auto-selects between the software and hardware implementation. Software implementation path is taken if the hardware is currently in use by some other context. Refactor the CR50 loader to use this abstraction. The existing software implementation for SHA1 and SHA256 is used for the software path. CQ-DEPEND=CL:*239385 BRANCH=none TEST=EC shell boots fine (implies that SHA256 works) BUG=chrome-os-partner:43025 Change-Id: I7bcefc12fcef869dac2e48793bd0cb5ce8e80d5b Signed-off-by: nagendra modadugu <ngm@google.com> Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/313011
* cr50: rename hw generated register definitions fileVadim Bendebury2015-11-211-1/+1
| | | | | | | | | | | | | | This common for all g based boards file should not be associated with a single board. BRANCH=none BUG=none TEST=the device still builds and boots. Change-Id: I34c49a095abd8e49b492c318823dd8f56609fdc8 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/313631 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Add initial dcrypto AES implementation.nagendra modadugu2015-11-111-0/+4
| | | | | | | | | | | | | BRANCH=none BUG=chrome-os-partner:43025,chrome-os-partner:47524 TEST=none Change-Id: I7c0e8f50fb786d62e4fe13ea19ddce1dba116408 Signed-off-by: nagendra modadugu <ngm@google.com> Reviewed-on: https://chromium-review.googlesource.com/309873 Commit-Ready: Nagendra Modadugu <ngm@google.com> Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Tested-by: Nagendra Modadugu <ngm@google.com> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* cr50: re-generate register descriptionsVadim Bendebury2015-11-101-21/+0
| | | | | | | | | | | | | | New aliases are created automatically, there is no need to include them in registers.h manually any more. BRANCH=none BUG=none TEST=built and ran cr50 successfully Change-Id: I9c12c9a66d231723f8c986dd0c598f1e03aaca3a Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/311372 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Cr50: Support USB on 15MHz FPGA imageBill Richardson2015-10-221-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The latest Cr50 FPGA release runs at 15MHz, but supports USB operations. This CL includes changes to make that work. Specifically: * Enable the security features and select the correct PHY * Adjust the turnaround time for the slower clock speed * Handle the SET ADDRESS command specially for this SoC * Remove all printfs from interrupt handlers (but add #ifdef code to print debug messages later if desired). BUG=chrome-os-partner:34893 BRANCH=none TEST=make buildall, manual test of Cr50 USB: 1. Plug into a USB jack on a Linux host. 2. In src/platform/ec/extra/usb_console, run make ./usb_console -p 5014 -e 1 3. Type something, hit return 4. See whatever you typed come back with swapped case 5. ^D to quit Change-Id: I848e96d19df056a453d30d4b5537481046fe852d Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/308062 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* cr50: remove unused register definitionsVadim Bendebury2015-08-111-9/+0
| | | | | | | | | | | | | Let's just keep one hardware version at a time. BRANCH=none BUG=chrome-os-partner:43791 TEST=make buildall -j Change-Id: I2e8c40e28638d461fa4ff14ad97ca5da55b33dd2 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/291856 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* cr50: add USB supportVincent Palatin2015-04-021-0/+146
| | | | | | | | | | | | | | | | | | | | | Add a USB device driver for the Synopsys DWC USB device controller. The common USB protocol stack code still need to be de-duplicated with the STM32 implementation. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=chrome-os-partner:33919 TEST=plug Cr50 to a Linux workstation and see USB descriptors using "lsusb -v -d 18d1:5014" Change-Id: I4a367241053de2c2d94aa06f82ea4bee51f9f89a Reviewed-on: https://chromium-review.googlesource.com/231160 Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Trybot-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* cr50: Added macros for register read/writeSheng-Liang Song2015-03-201-4/+83
| | | | | | | | | | | | | | | | Added macros for register read/write. BRANCH=none BUG=chrome-os-partner:33815 TEST="make buildall -j; Verified on RevA1 chip" Signed-off-by: Sheng-Liang Song <ssl@chromium.org> Change-Id: I25c6f6b5865c7fdde002b2191b1f2eaaba15f589 Reviewed-on: https://chromium-review.googlesource.com/236402 Reviewed-by: Bill Richardson <wfrichar@chromium.org> Commit-Queue: Sheng-liang Song <ssl@chromium.org> Tested-by: Sheng-liang Song <ssl@chromium.org>
* cr50: added cr50 a1 chipSheng-Liang Song2015-03-201-1/+14
| | | | | | | | | | | | | | cr50_a1 is for cr50 Rev A1 chip. BUG=chrome-os-partner:33432 BRANCH=none TEST=Compile Only Change-Id: I5490d1a5b89fa66c8e8b969cff7538a293a7d053 Signed-off-by: Sheng-Liang Song <ssl@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/259847 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* cr50: Separate ARM core GPIOs from pinmux configurationBill Richardson2015-02-201-30/+82
| | | | | | | | | | | | | | | | | | | | This separates the configuration of the ARM core GPIOs from the routing of internal peripherals to external pins. Both are still described in the gpio.inc file, but are less dependent on each other. BUG=chrome-os-partner:33818 BRANCH=none TEST=manual Before this CL, running "sysjump rw" or trying to use more than 8 GPIOs caused hangs and reboots. Now it doesn't. Change-Id: If962a7c5ad4136837b2ea00ae016a440f07d7e23 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/251015 Reviewed-by: Sheng-liang Song <ssl@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* g: implement GPIOsVincent Palatin2014-12-101-7/+50
| | | | | | | | | | | | | | | | | | Add a driver for the GPIO controller. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=chrome-os-partner:33816 TEST=press the push buttons on the board and see the console text message and the LEDs lighting up. Change-Id: Idb408fe1c341beb8a97f2047ba6740e0d40cedf5 Reviewed-on: https://chromium-review.googlesource.com/233307 Trybot-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
* g: update version stringVincent Palatin2014-12-061-2/+5
| | | | | | | | | | | | | | | | | | | | | Build the hardware version string from the register definitions, so I no longer forget to update it. Check it at runtime against the build version registers. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=none TEST=On the console command line, type "version" and see the following string: "Chip: g cr50 A1 20141203_224409" Change-Id: I6d902780d42f2dd18a57ccc08fd4ba4fee5ebc7c Reviewed-on: https://chromium-review.googlesource.com/233582 Reviewed-by: Bill Richardson <wfrichar@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Trybot-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
* g: update reset codeVincent Palatin2014-12-061-9/+63
| | | | | | | | | | | | | | | | | | | | | | | | - record and display reset cause - add the hard reset option - add the scratchpad to store values across reboots. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=chrome-os-partner:33818 TEST=On the console command line, chech the "[Reset cause: xxx]" string - for the initial reset cause - use "waitms 4000" to trigger a watchdog reset - use "reboot soft" - use "reboot hard" The "utils" test is now building and passing. Change-Id: I68c7096e5b7bfd102be89fd8eef6fe20da37a6f8 Reviewed-on: https://chromium-review.googlesource.com/233581 Reviewed-by: Bill Richardson <wfrichar@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Trybot-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
* g: add watchdog driverVincent Palatin2014-12-061-0/+11
| | | | | | | | | | | | | | | | | | | | | Implement a driver to trigger a watchdog reboot if we are stuck somewhere. Also display a nice warning when we reach half of the watchdog period. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=none TEST=On the console, type "waitms 500" and see nothing, type "waitms 2000" and see the watchdog warning. Type "waitms 4000" and see the warning, the platform rebooting. Change-Id: Iac5d0100febd5eab1ae6cfac5a47ff728ebda3a6 Reviewed-on: https://chromium-review.googlesource.com/233430 Reviewed-by: Bill Richardson <wfrichar@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Trybot-Ready: Vincent Palatin <vpalatin@chromium.org>
* Cr50: Update/refactor for new HW releaseBill Richardson2014-11-181-234/+77
| | | | | | | | | | | | | | | | | | | | | | | This is fairly large change set to accomodate a new hardware release. There are enough differences to require refactoring the registers.h file. Autogenerated constants are now in gc_regdefs.h and all constant names begin with GC_, while register names are defined in registers.h and begin with GR_. Yes, I know the new header files are wider than 80 chars, but we agreed that was okay in some cases if it makes them more readable (see commit 3500c28). BUG=chrome-os-partner:33423 BRANCH=none TEST=make buildall -j Build and run on the development board. Change-Id: I21bd88c490f4f359ad17b5af9d17d8caca8dc9e4 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/230513 Reviewed-by: Sheng-liang Song <ssl@chromium.org>
* cr50: Add support for hwtimerBill Richardson2014-11-141-0/+45
| | | | | | | | | | | | | | | | | Implement the API expected by common/timer.c BUG=chrome-os-partner:33699 BRANCH=none TEST=manual Run the "gettime" and "timerinfo" and "taskinfo" and "waitms" commands. Compare the elapsed time with the real world. They seem to match. Change-Id: Ie5acae76780ee09e7dfb6cc0282de25f8063e96f Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/229642 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Add initial support for cr50 SoCBill Richardson2014-10-311-0/+219
The serial console works. Nothing else is implemented yet. BUG=none BRANCH=ToT TEST=make buildall -j To build, make BOARD=cr50 hex Testing the result requires a development board. I have one. It works with HW revision m3.dist_20140918_094011 Change-Id: I718d93572d315d13e96ef6f296c3c2796e928e66 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/226268 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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