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path: root/chip/g/sps.c
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* use gpio_set_wakepin() to enable or disable wake pinsNamyoon Woo2020-02-131-4/+2
* extend INT_AP_L pulseNamyoon Woo2020-01-161-0/+10
* cr50: fix sps driver sync problemsVadim Bendebury2018-09-041-12/+5
* g:sps: do not stall reset when CS is assertedVadim Bendebury2017-11-301-14/+0
* g: handle delayed processing of the 'wake' pulsesVadim Bendebury2017-11-081-2/+38
* g: sps: at initialization wait for the master to finish SPI cycleVadim Bendebury2017-11-081-0/+14
* g: sps do not invoke rx_handler unless data was receivedVadim Bendebury2017-11-081-4/+7
* tpm: provide means of shutting down comms layer while in resetVadim Bendebury2017-11-071-0/+3
* g: fix sps interrupt assertion logicVadim Bendebury2017-03-101-8/+15
* g: sps: add flow control signalingVadim Bendebury2017-02-231-0/+9
* cr50: keep board properties related code in board.cVadim Bendebury2016-12-201-1/+1
* chip/g to chip/lm4: fix more misspellings in commentsMartin Roth2016-11-151-1/+1
* Fix various misspellings in commentsMartin Roth2016-11-151-6/+6
* tpm: reset communications channels when resetting TPMVadim Bendebury2016-09-261-16/+2
* cleanup: DECLARE_CONSOLE_COMMAND only needs 4 argsBill Richardson2016-08-241-2/+1
* chip/g/sps: Initialize received_data pointer to NULLMartin Roth2016-08-221-1/+1
* Cr50: Sample slave configuration pins at PORScott2016-08-031-0/+8
* cr50: fix wake pin handling when resuming from sleepMary Ruthven2016-07-281-1/+1
* Cr50: Specify pinmux wake sources in gpio.incBill Richardson2016-04-051-5/+10
* cr50: sps: allow receive registration function set FIFO thresholdVadim Bendebury2015-08-131-5/+10
* cr50: code modifications to support FPGA B1Vadim Bendebury2015-08-111-0/+6
* Cr50: Enable TPM-protocol data over the SPI busVadim Bendebury2015-07-251-2/+6
* sps: expose RX FIFO write pointerVadim Bendebury2015-07-251-0/+5
* cr50: Use distinct configuration option for SPI Slave supportVadim Bendebury2015-07-251-2/+2
* cr50: restore SPS driver performanceVadim Bendebury2015-07-171-153/+348
* Cr50: Restore spstest commandBill Richardson2015-07-141-0/+18
* Cr50: Pass SPI and SPS modes to sps_register_rx_handler()Bill Richardson2015-07-131-18/+15
* Cr50: Clear the TX FIFO when the SPS CS deassertsBill Richardson2015-07-111-8/+12
* Cr50: Handle 11-bit SPS FIFO pointers correctlyBill Richardson2015-07-101-30/+52
* Cr50: Simplify the API for the SPS driverBill Richardson2015-07-071-321/+91
* cr50: add SPI Slave driverVadim Bendebury2015-05-071-0/+486
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