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* Cr50: bootloader: display config bits at bootBill Richardson2015-12-011-2/+6
* cr50: SHA1 and SHA256 implementation with hardware supportnagendra modadugu2015-11-2510-122/+435
* cr50: dcrypto code belongs with the chip, not with the boardVadim Bendebury2015-11-234-0/+182
* cr50: move key ladder initialization into its own filesVadim Bendebury2015-11-236-39/+63
* cr50: rename hw generated register definitions fileVadim Bendebury2015-11-214-3/+3
* cr50: Update to the "final final" FPGA image 20151118_11218@80881Vadim Bendebury2015-11-211-170/+225
* add command multiplexer to the TPM driverVadim Bendebury2015-11-181-0/+1
* Add initial dcrypto AES implementation.nagendra modadugu2015-11-111-0/+4
* Cr50: Tweak debug message for clarityBill Richardson2015-11-101-1/+2
* Cr50: Fix uart_tx_flush() to really flushBill Richardson2015-11-101-2/+3
* Cr50: Workaround for watchdog permission problemsBill Richardson2015-11-102-9/+20
* cr50: make customized RO workVadim Bendebury2015-11-102-3/+12
* cr50: allocate signature headers in both RO and RW imagesVadim Bendebury2015-11-101-0/+1
* cr50: RO Loader implementationVadim Bendebury2015-11-1012-5/+858
* cr50: re-generate register descriptionsVadim Bendebury2015-11-102-21/+25
* cleanup: Rename usb.h to usb_descriptor.hShawn Nematbakhsh2015-11-084-4/+4
* Fix soft reboot to handle dropped permissions.nagendra modadugu2015-11-061-7/+31
* Cr50: Update to the "final" FPGA image 20151104_041733@78962Bill Richardson2015-11-062-541/+562
* Cr50: Disable customized RO image by defaultBill Richardson2015-11-062-4/+8
* cr50: introduce RO image skeletonVadim Bendebury2015-11-054-1/+116
* Cr50: Fix bug in print_later, add overflow detectionBill Richardson2015-11-051-9/+18
* cr50: upgrade to the latest FPGA image 20151029_41713@78167Vadim Bendebury2015-10-301-577/+700
* Cr50: Support USB on 15MHz FPGA imageBill Richardson2015-10-222-13/+152
* Cr50: Support FPGA image m3.dist_20151021_054409Bill Richardson2015-10-221-2399/+2559
* Cr50: enable modificaton of flash bank 1Bill Richardson2015-10-171-0/+10
* g: implement support for hardware based TRNGVadim Bendebury2015-10-172-0/+23
* cr50: upgrade to the latest FPGA image (20151012_041715@75660)Vadim Bendebury2015-10-121-350/+525
* cr50: upgrade to the latest FPGA image (20151007_064811)Vadim Bendebury2015-10-071-1147/+1268
* cr50: upgrade to the latest FPGA imageVadim Bendebury2015-10-052-1391/+1591
* cr50: update to the next fpga revisionVadim Bendebury2015-09-292-4758/+7331
* cleanup: Put chip-specific configs in config_chip.hBill Richardson2015-09-211-0/+7
* Cr50: Add support for flash write & eraseBill Richardson2015-09-183-6/+257
* cleanup: Remove redundant FLASH_SIZE CONFIGsShawn Nematbakhsh2015-09-161-1/+1
* cleanup: Rename geometry constantsShawn Nematbakhsh2015-09-161-1/+1
* update case closed debugging partial mode policyVincent Palatin2015-09-081-3/+6
* Update some TODO comments.Bill Richardson2015-09-031-4/+0
* cr50: add plumbing for signing CR50 RO imagesVadim Bendebury2015-08-251-0/+6
* cr50: Move to RevB:20150820 FPGAVadim Bendebury2015-08-251-3147/+3149
* cr50: allocate RO header for signatureVadim Bendebury2015-08-251-0/+1
* Cr50: Fix spshc console commandBill Richardson2015-08-151-2/+2
* cr50: tpm2: pull in the tpm2 library sourcesVadim Bendebury2015-08-141-2/+2
* cr50: introduce tpm task skeletonVadim Bendebury2015-08-141-1/+1
* cr50: sps: allow receive registration function set FIFO thresholdVadim Bendebury2015-08-134-8/+21
* cr50: remove unused register definitionsVadim Bendebury2015-08-112-18372/+0
* cr50: code modifications to support FPGA B1Vadim Bendebury2015-08-117-4780/+10264
* cr50: add polling uart implementationVadim Bendebury2015-08-112-1/+90
* stm32: Enable 3rd SPI interfaceGwendal Grignou2015-07-301-0/+1
* Cr50: Enable TPM-protocol data over the SPI busVadim Bendebury2015-07-254-3/+294
* sps: expose RX FIFO write pointerVadim Bendebury2015-07-252-0/+6
* cr50: Use distinct configuration option for SPI Slave supportVadim Bendebury2015-07-253-7/+7
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