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* cr50: change OWNERS to cr50 team membersMary Ruthven2019-12-101-1/+0
| | | | | | | | | | | | | | Change the OWNERS to cr50 team members and remove OWNERS files from all subdirectories. BUG=none BRANCH=none TEST=none Change-Id: I5ddff7c433a55b6724d92c026e9e64e82e1492ad Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1957850 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* chip/host: Avoid concurrent recipes of libcryptoc.astabilize-12748.B-cr50_stabYicheng Li2019-12-062-16/+3
| | | | | | | | | | | | | | | | | | | | | | | | CONFIG_DCRYPTO compiles and links thirdparty/libcryptoc for cr50. CONFIG_LIBCRYPTOC does similar things for other boards that configures it, including host. This resulted in cr50_fuzz having concurrent recipes for libcryptoc, as it has both configs. This change separates CONFIG_DCRYPTO from the responsibility of building and linking libcryptoc. Libcryptoc is now solely handles by CONFIG_LIBCRYPTOC. BRANCH=none BUG=b:144811298 TEST=make -j buildall > /dev/null Observed no more "warning: overriding recipe for target 'build/host/cr50_fuzz/cryptoc/libcryptoc.a' " Change-Id: I2186cbead773629456da254df5f82b96e9646fc2 Signed-off-by: Yicheng Li <yichengli@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1949554 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> (cherry picked from commit a018043265ecb3466863ff9020ab25d552105c61) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1956404 Tested-by: Vadim Bendebury <vbendeb@chromium.org> Commit-Queue: Vadim Bendebury <vbendeb@chromium.org>
* g: update rollback info map for both RO and RW sectionsVadim Bendebury2019-12-061-10/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Both RO and RW sections have their respective rollback spaces in INFO1, but until now Cr50 code did not honor the RO binaries' headers rollback maps and did not update the appropriate iNFO1 space. With this patch both RO and RW info maps are updated to the lowest level of the two images found in the flash when invoked during board_init() or to match the currently active RO/RW when invoked through vendor command indicating successful OS startup. BRANCH=cr50, cr50-mp BUG=b:136284186 TEST=tried the new image on a chip with freshly erased INFO1 space: first running a DBG image, which does not touch INFO1 maps: > vers ... RO_A: * 0.0.11/bc74f7dc RO_B: 0.0.11/4d655eab RW_A: * 0.4.24/DBG/cr50_v2.0.2744-d79516a9d RW_B: 0.4.24/DBG/cr50_v2.0.2744-d79516a9d .. > sysinfo ... Rollback: 0/1/1 0/128/128 ... Then running an image with debug extensions disabled: > vers ... RO_A: * 0.0.11/bc74f7dc RO_B: 0.0.11/4d655eab RW_A: 0.4.24/DBG/cr50_v2.0.2744-d79516a9d RW_B: * 0.4.24/cr50_v2.0.2744-d79516a9d ... > sysinfo ... Rollback: 1/1/1 2/128/2 ... Change-Id: I259a3f46c03199633ca85389872449d667f172fb Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1949548 Reviewed-by: Mary Ruthven <mruthven@chromium.org> (cherry picked from commit 94cfd7cee548047d8e0f5dee2995c4c03fba665d) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1954342
* g: display both RO and RW info map statusVadim Bendebury2019-12-061-25/+36
| | | | | | | | | | | | | | | | | | | | | | | Cr50 firmware is required to update the rollback prevention map in INFO1 for both RO and RW images. This patch adds code to display the state of the RO map and both RO_A and RO_B headers in addition to previously reported RW information. BRANCH=cr50, cr50-mp BUG=b:136284186 TEST=loaded the new image and observed reported rollback state: > sysinfo ... Rollback: 0/1/1 0/128/128 ... Change-Id: I32206545b6a59a5693e4274e62fcf0627780f61f Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1949546 Reviewed-by: Namyoon Woo <namyoon@chromium.org> (cherry picked from commit 565c54c270bd93ee30e8f8560d3d1691d128e762) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1954341
* g: Add support for 192 and 256 bit AES-GCM in DCRYPTO_gcm_initVadim Sukhomlinov2019-12-062-5/+5
| | | | | | | | | | | | | | | | | | | DCRYPTO_gcm_init hardcoded key length to 128 bit causing preventing testing of 192 and 256 bit functionality for AES-GCM. BUG=b:135623371 BRANCH=cr50 TEST=compile, specific test for issue as described in bug Change-Id: I4fc41f6155661709115c57aa944c8976e17bffac Signed-off-by: Vadim Sukhomlinov <sukhomlinov@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1766098 Reviewed-by: Andrey Pronin <apronin@chromium.org> (cherry picked from commit 24f7511e41c1f8140b19d69d9440a3ea6f91bd89) Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1954339 Tested-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Commit-Queue: Vadim Bendebury <vbendeb@chromium.org>
* cr50: switch to new dev keyVadim Bendebury2019-11-211-1/+1
| | | | | | | | | | | | | | | The new RO has a new dev key, modify the dev manifest to match the new RO expectations. BUG=b:74100307 BRANCH=cr50, cr50-mp TEST=built a node locked image for ro 0.0.11 and observed it boot and run Change-Id: I3ce9ca8d23be6b2d959d4457ea6d08afa05376ac Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1866173 Reviewed-by: Andrey Pronin <apronin@chromium.org>
* cr50: remove flash nonvolatile counter spaceVadim Bendebury2019-11-211-1/+1
| | | | | | | | | | | | | | Counter implementation has been moved to the AP, no need to keep space for it in the flash. BUG=b:65253310 BRANCH=cr50, cr50-mp TEST=generated image uses 2048 bytes less than before this patch. Change-Id: I8225e9923932ce06ca0a4333c06508cf7d7c70d8 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1753677 Reviewed-by: Andrey Pronin <apronin@chromium.org>
* cr50: Add support for ACVP tests of HMAC SHA-256 DRBGVadim Sukhomlinov2019-11-211-0/+117
| | | | | | | | | | | | | | | | | | | HMAC DRBG is used for U2F key generation, and as such is subject for ACVP tests. Expose DRBG Init, Generate and Seed commands for automated testing with externally provided test vectors. BUG=b:138578319 BRANCH=cr50 TEST=make CRYPTO_TEST=1 BOARD=cr50 -j && test/tpm_test/tpmtest.py Change-Id: I50a6750864d3cd9a304a9b8a8524ef29cec04410 Signed-off-by: Vadim Sukhomlinov <sukhomlinov@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1912662 Reviewed-by: Vadim Sukhomlinov <sukhomlinov@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Tested-by: Vadim Sukhomlinov <sukhomlinov@chromium.org> Commit-Queue: Vadim Sukhomlinov <sukhomlinov@chromium.org> Auto-Submit: Vadim Sukhomlinov <sukhomlinov@chromium.org>
* cr50: Add TRNG_TEST command to download entropy samples for NIST testsVadim Sukhomlinov2019-11-191-0/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | NIST 800-90B Entropy assesment tests requires 1M of 8-bit samples for statistical tests. While it's possible to use TPM2_GetRandom command to get entropy on cr50 (there is no software postprocessing), this command is not available when compiled with CRYPTO_TEST=1 due to lack of space in firmware. Adding vendor command which is available with CRYPTO_TEST=1 to get raw entropy from TRNG. Added support script to save entropy in file for further analysis. Since downloading entropy takes a long time, new option'-t' added to tpmtest.py which only invokes download of TRNG samples BUG=b:138577834 BRANCH=cr50 TEST=make BOARD=cr50 CRYPTO_TEST=1 && test/tpm_test/tpmtest.py -t To run NIST tests: nist_entropy.sh Change-Id: I237a4581332a6e2c0332fe6ecf40731ab0be3355 Signed-off-by: Vadim Sukhomlinov <sukhomlinov@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1919640 Reviewed-by: Vadim Sukhomlinov <sukhomlinov@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Tested-by: Vadim Sukhomlinov <sukhomlinov@chromium.org> Commit-Queue: Vadim Bendebury <vbendeb@chromium.org> Auto-Submit: Vadim Sukhomlinov <sukhomlinov@chromium.org>
* Add OWNERS for Cr50 specific directoriesVadim Bendebury2019-11-161-0/+1
| | | | | | | | | | | | | | | Let's make sure any change to files used explicitly in Cr50 are approved by relevant persons. BRANCH=none BUG=none TEST=none Change-Id: If6affd837063311e3215e7596a3a424dc56c7603 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1919649 Reviewed-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Andrey Pronin <apronin@chromium.org>
* g: board_id: allow setting bid type if only flags are setMary Ruthven2019-11-071-13/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It's ok to set the board id type if it's blank. It doesn't matter if the flags are set. Use the given flags if the flags are empty or use the existing flags if they're already set. BUG=b:143649068 BRANCH=cr50 TEST=manual eraseflashinfo gsctool -i ZZAF:0x7f7f - SUCCEEDS. Board ID: 5a5a4146:a5a5beb9, flags 00007f7f gsctool -i ZZAF:0x7f7f - FAILS Board ID: 5a5a4146:a5a5beb9, flags 00007f7f eraseflashinfo gsctool -i 0xffffffff:0x3f80 - SUCCEEDS. Board ID: ffffffff:ffffffff, flags 00003f80 gsctool -i ZZAF:0x7f7f - SUCCEEDS. Board ID: 5a5a4146:a5a5beb9, flags 00003f80 eraseflashinfo bid 0xffffffff 0x3f80 Board ID: ffffffff:00000000, flags 00003f80 gsctool -i ZZST:0x3f80 - FAILS. Board ID: ffffffff:00000000, flags 00003f80 update to image with BID TEST:ffff:10 eraseflashinfo gsctool -i 0xffffffff:0x3f80 - FAILS Board ID: ffffffff:ffffffff, flags ffffffff gsctool -i ZZAF:0x7f7f - FAILS Board ID: ffffffff:ffffffff, flags ffffffff gsctool -i ZZST:0x7f7f - SUCCEEDS. Board ID: 5a5a5354:a5a5acab, flags 00007f7f update to image with BID TEST:0:100 eraseflashinfo gsctool -i whitelabel - SUCCEEDS. Board ID: ffffffff:ffffffff, flags 00003f80 gsctool -i ZZST:0 - SUCCEEDS. Board ID: 5a5a5354:a5a5acab, flags 00003f80 Change-Id: I07de4721cb9cc9ad6e74a51e1794a49cb70f70fb Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1892122 Reviewed-by: Namyoon Woo <namyoon@chromium.org>
* g: bid: show type is empty instead of an errorMary Ruthven2019-11-071-1/+1
| | | | | | | | | | | | | | | It's ok if type and type_inv are both empty. Only show an error if the board ID type isn't empty and the inversion is incorrect. BUG=none BRANCH=cr50 TEST=set whitelabel rlz and run 'bid' command. Make sure the warning isn't shown. Change-Id: I12b1e4b34559bc8b6ad482d9694c9dd143bfcd1c Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1892121 Reviewed-by: Namyoon Woo <namyoon@chromium.org>
* sn_bits: allow setting serial number if BID type is blankMary Ruthven2019-11-073-3/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | BUG=b:143649068 BRANCH=cr50 TEST=manual eraseflashinfo Board ID: ffffffff:ffffffff, flags ffffffff gsctool -S AAAAAAAAAAAAAAAAAAAAAAA1 succeeds eraseflashinfo gsctool -i 0xffffffff:0x3f80 Board ID: ffffffff:ffffffff, flags 0x3f80 gsctool -S AAAAAAAAAAAAAAAAAAAAAAA1 succeeds eraseflashinfo gsctool -i ZZAF:0x7f7f Board ID: 5a5a4146:a5a5beb9, flags 0x3f80 gsctool -S AAAAAAAAAAAAAAAAAAAAAAA1 fails Change-Id: I5d2a3f35c5c7e4e79cadbb3a6737e5db00f8ca5a Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1892120 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* board_id: change the vc to allow setting only flagsMary Ruthven2019-11-071-1/+4
| | | | | | | | | | | | | | | If the board id type is 0xffffffff, hold off on erasing any type_inv bits until we get a type that isn't empty. BUG=b:143649068 BRANCH=cr50 TEST=Use gsctool -i 0xffffffff:0x3f80 to set flags to 0x3f80. Get the board id and make sure the rlz and rlz_inv fields are still 0xffffffff. Change-Id: I8243cb59f2560dc232bb982e1615271136d60f24 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1892118 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* board_id: ignore erased bid type when checking headersMary Ruthven2019-11-072-12/+28
| | | | | | | | | | | | | | | | | We will be able to set the board id flags without setting the type. If only flags are set, then check the flags. If the type is set, also check the type. BUG=b:143649068 BRANCH=cr50 TEST=set flags to 0x3f80. Try to update to a ZZAF:0:0:0 image. Make sure it isn't rejected with board id type mismatch. Try to update to a prepvt image. Make sure it's rejected. Change-Id: Ie0efdd7b1b6d76f385688f75c0765c08cab3755c Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1892117 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* board_id: clean up/enhancementsMary Ruthven2019-11-071-5/+6
| | | | | | | | | | | | | | | | | Add type_inv to the bid command output. In the bid output you can't tell the difference between a board with type 0xffffffff and a empty type. Change the command output to show type and type_inv, so we can tell the difference. Remove unused clear_flag parameter BUG=b:143649068 BRANCH=cr50 TEST=run 'bid' Change-Id: I13b6ba472010fdf85f94cb4015a9bbc48531973d Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1892115 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* sn_bits: use board_id_is_blankMary Ruthven2019-11-071-1/+1
| | | | | | | | | | | | | | Use the standard board_id_is_blank function to check if the board id is blank. BUG=b:143649068 BRANCH=cr50 TEST=set the serialnumber Change-Id: If4e50a548ec2a4747b7bc291f93f170e28eea949 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1892114 Reviewed-by: Namyoon Woo <namyoon@chromium.org>
* Cleanup: Correct GPIO alternate function parameterVijay Hiremath2019-11-011-1/+2
| | | | | | | | | | | | | | | Added code to correct the GPIO alternate function parameter at Chipset level. Optionally board level functions can cleanup the code in additional change lists. BUG=b:139427854 BRANCH=none TEST=make buildall -j Change-Id: I1171ca36a703291070fc89f972f84414adcf04fc Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1880974 Reviewed-by: Keith Short <keithshort@chromium.org>
* main: Initialize I2C pretty earlyAlexandru M Stan2019-10-241-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Some devices (like the keyboard, CBI) need I2C access pretty early. Until now I2C would get initialized pretty late in a hook, which was far too late for some stuff. As a result from this change, CONFIG_I2C_MASTER now implies the i2c_init() function will be called at board boot. Some chips (cr50, host tests) needed a stub i2c_init in order to compile cleanly. BUG=b/138384267 TEST=EFS doesn't happen significantly later than it used to TEST=Recovery keys now work with I2C keyboard on jacuzzi TEST=make buildall TEST=Sanity check i2c behavior (booting, "i2scan", "battery") on a variety of ECs: * ampton (ite EC, x86 AP) * bobba (npcx EC, x86 AP) * jacuzzi (stm32f0 EC, ARM AP) * cheza (npcx EC, ARM AP) BRANCH=master Change-Id: Ifa830e8e509ff16b36b4dcc86617869b1cb86ac3 Signed-off-by: Alexandru M Stan <amstan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1772490 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* Delay uart_init() done to after pinhold is disengaged.Pai Peng2019-10-211-4/+17
| | | | | | | | | | | | | | | | | | | | | Since pinhold will hold UART pin, UART won't work correctly. In this case, we want to delay uart_init() done until pinhold is disengaged. The messages to UART are still kept in the UART buffer and can be correctly printed through UART after pinhold is released. BUG=b:138327854 BRANCH=none TEST=manual Testing: verified that after cold or warm reset, messages from RW image can be correctly printed to UART. Without this change, we might see incomplete messages or garbage characters. Change-Id: I00934aa16178b995d996f6ba773abab80f329124 Signed-off-by: Pai Peng <paipeng@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1717547 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* cr50: Fix building with CRYPTO_TEST=1Vadim Sukhomlinov2019-10-171-1/+1
| | | | | | | | | | | | | | | | | | | | 1. Recent change https://crrev/1730605 introduced syntax error which is only affecting build with CRYPTO_TEST=1. This patch fixes it. 2. -Wformat which was turned on for /platform/ec caught another issue with CPRINTF() not receiving right number of parameters. BUG=none BRANCH=cr50 TEST=make BOARD=cr50 CRYPTO_TEST=1 Change-Id: Id5e61f7633d6e93aff761771c22b888aebd87265 Signed-off-by: Vadim Sukhomlinov <sukhomlinov@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1863813 Tested-by: Andrey Pronin <apronin@chromium.org> Commit-Queue: Andrey Pronin <apronin@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Andrey Pronin <apronin@chromium.org>
* Zero data toggles on endpointis when appropriate.Barry Twycross2019-10-091-15/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The data toggle should be reset on an endpoint in two circumstances when the device is configured (with a SET_CONFIGURATION), or whent the endpoint is "cleared" (with a CLEAR_FEATURE(endpoint_halt). The endpoint reset code is deficient, in that the data toggle is not reset when appropriate. The upshot of this is that if the device and host ever get out of sync, the transfer will be ACKed, but the data thrown away (which is correct behaviour per spec). This causes all sorts of head scratching. In this particular case, the data which is discarded is a mailbox command to a Haven (root of trust) chip. Thus the host hangs forever waiting for a response that never comes, because the device never got the command. This behaviour is seen in testing for reasons which are not clear, but can be provoked by sending resets to the device, while sending resets to the device. The device will hang as the following SET_CONFIGURATION is supposed to clear the toggles (but doesn't) After implementing this fix, the device no longer hangs after a reset in this test. This issue is doubly bad for the device, as the recovery should be to time out the bulk transfer, and reset the endpoint, or if that doesn't work, reset the device. With the deficient code it is impossible to use standard recovery mechanisms when running across this issue. Note: The Synopsis data book notes under the register (Device Endpoint-n Control Register: DIEPCTLn/DOEPCTLn), DPID "The application must program the PID of the first packet to be received or transmitted on this endpoint, after the endpoint is activated." This is what this change is fixing, the code does not currently do this. BUG=b:141140341 BRANCH=cr50, cr51, cr52 TEST=(cr51) Problem can be reproduced by sending a reset to the haven, while it is being access by USB EC commands. 50% of the time, the next transfer will hang as the toggle is now incorrect. With this fix, the device can be reset and no hang. TEST=(cr51) A similar test is done by sending CLEAR_FEATURE(endpoint_halt) commands to the device while processing USB EC commands. On a USB analyser you can see the toggle has been reset, as the device continues to work, even if the PIDs before and after the CLEAR_FEATURE were both DATA0. TEST=(cr50) Ran flash_ec on fleex through CCD. Ran uart_stress_test on fleex as well. Signed-off-by: barryt@google.com Change-Id: Id621cfaa422d3589187db7be8a188ed411bb4c98 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1804065 Tested-by: Namyoon Woo <namyoon@chromium.org> Reviewed-by: Namyoon Woo <namyoon@chromium.org> Commit-Queue: Namyoon Woo <namyoon@chromium.org>
* Remove uses of %lEvan Green2019-10-053-4/+4
| | | | | | | | | | | | | | | | | | | | | | | This change removes uses of %l from the EC side of the EC codebase. This is done because the semantics of %l within printf have changed, and there are concerns that new calls to printf will be cherry-picked into old firmware branches without the printf changes. So, in preparation for disallowing %l in master, remove occurrences of %l. This change was done by manually fixing up anything found under the EC directory with the following regex: %[0-9*.-]*l[^l] Remember that anything on the host machine is fine as-is, since the host printf never changed. BUG=chromium:984041 TEST=make -j buildall BRANCH=None Change-Id: I2a97433ddab5bfb8a6031ca4ff1d3905289444e2 Signed-off-by: Evan Green <evgreen@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1834603 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* printf: Enable compile-time format checkingEvan Green2019-10-051-0/+1
| | | | | | | | | | | | | | | Add annotations to allow the compiler to check printf-style format strings in the EC. BUG=chromium:984041 TEST=make -j buildall BRANCH=None Change-Id: Ic39f37f8362372de7d289becea684d9da535599a Signed-off-by: Evan Green <evgreen@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1733101 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* printf: Fix formatting errorsEvan Green2019-10-052-3/+4
| | | | | | | | | | | | | | | | | | | This change fixes the printf formatting errors found by the compile-time prinf format checker. The errors fall into a few categories: 1. Incorrect size specifier (missing or extra l). 2. Missing or extra arguments. 3. Bad line splitting. BUG=chromium:984041 TEST=make -j buildall BRANCH=none Change-Id: I5618097a581210b9fcbfc81560dec050ae30b61c Signed-off-by: Evan Green <evgreen@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1819653 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* printf: Convert %h to %phEvan Green2019-10-055-12/+12
| | | | | | | | | | | | | | | | | | | | | In order to make printf more standard, use %ph. Pass a pointer to a struct describing the buffer, including its size. Add a convenience macro so that conversion between the old style and new style is purely mechanical. The old style of %h cannot be converted directly to %ph as-is because the C standard doesn't allow flags, precision, or field width on %p. Ultimately the goal is to enable compile-time printf format checking. This gets us one step closer to that. BUG=chromium:984041 TEST=make -j buildall BRANCH=None Cq-Depend:chrome-internal:1559798,chrome-internal:1560598 Change-Id: I9c0ca124a048314c9b62d64bd55b36be55034e0e Signed-off-by: Evan Green <evgreen@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1730605
* printf: Fix up %p to %pPEvan Green2019-10-053-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | In order to avoid landmines later with future extensions to %p, disallow %p by itself. The danger is that we'll have something like: printf("%pFOO", myptr), and then later will add a %pF extension, but miss this printf (maybe the string is split, maybe it's just missed). Missing a conversion during extension is worse than just seeing a print like <ptr_val>OO, since %pF likely reaches through the pointer and interprets its contents according to whatever F means. Convert existing uses of %p to %pP, so they're explicitly printing a pointer value, giving us flexibility to extend in the future. BUG=chromium:984041 TEST=make -j buildall BRANCH=None Cq-Depend:chrome-internal:1560879 Change-Id: I36a4bee8d41cb9a6139171f8de0d8f2f19468132 Signed-off-by: Evan Green <evgreen@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1730604 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* g: avoid locked up flash after denied operationVadim Bendebury2019-09-271-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | It looks like the flash controller requires the user to explicitly clear the command field if the command fails. Not clearing the command field prevents error status from clearing on read. BRANCH=cr50, cr50-mp BUG=b:141203977 TEST=with the latest RO locking out INFO1 erases, it is possible to keep accessing flash after failing 'eraseflashinfo' invocation: > eraseflashinfo do_flash_op:274 errors 1000 fsh_pe_control 40720004 do_flash_op:265 Failed to erase info space! Unknown error Usage: eraseflashinfo > bid Board ID: 0001e240, flags 00000000 > Change-Id: I4dd14e1e5f974bb30e2ca5beb9e43e2974ace179 Signed-off-by: Marius Schilder <mschilder@chromium.org> Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1812175 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* g: re-implement usb console with usb-stream configuration.Namyoon Woo2019-09-192-1/+11
| | | | | | | | | | | | | | | | | | | | This patch introduces CONFIG_USB_CONSOLE_STREAM, which implements usb-console with usb-stream configuration, intending to remove code redundancy between the previous implementation (usb_console.c) and usb_stream.c. Flash usage decreases by 224 bytes, and RAM usage by 40 bytes. BUG=b:138447451 BRANCH=cr50 TEST=Checked cr50 USB console and cr50 UART console respectively. Key-in response and output are working well: ./util/uart_stress_tester.py /dev/ttyUSB0 -t 300 --debug Change-Id: I305038e1db83dc49bb12a8afdbfcc2a8135d50f5 Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1741302 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* g: fix typoMarius Schilder2019-09-181-1/+1
| | | | | | | | | | | | | | | Signed-off-by: mschilder@google.com BRANCH=none BUG=none TEST=buildall -j Change-Id: I4a70828bc6e9af2acc91de501ffa853e23395353 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1809108 Reviewed-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Commit-Queue: Marius Schilder <mschilder@chromium.org> Commit-Queue: Vadim Bendebury <vbendeb@chromium.org> Tested-by: Marius Schilder <mschilder@chromium.org> Auto-Submit: Marius Schilder <mschilder@chromium.org>
* g: allow I2CS operate without hardware resetsVadim Bendebury2019-09-051-15/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It is not always possible to rely on PMU for resetting the I2CS controller. Most of the AP firmware versions deploy the 'I2C unwedge' cycle when coming out of reset, but not all of them, this is why Cr50 needs to be able to recover on its own in case there was a crash and the I2C bus was left mid transaction with the H1 holding down the SDA line. A GPIO is dedicated to monitor the I2CS_SDA line during reset. If the line is kept low, it could be a sign of a 'wedged' controller. The g I2CS FSM will reset any time the I2C 'stop' condition is detected. The create the 'stop' condition the I2C_SCL input is disconnected from the bus and connected to an internal GPIO, then I2C_SCL level is set to 'high' and register inverting the I2C_SDA value is toggled, which looks like a transition from zero to one to the controller. thus creating the 'stop' condition. BRANCH=cr50, cr50-mp BUG=b:135772657 TEST=the test was ran on a Pyro device, which uses I2C for communication with H1 and which AP firmware does not deploy the 'I2C unwedge' cycle. Test instrumentation involved setting a Chrome OS startup file such that once booted, the AP starts continuously polling TPM for value of an NVMEM index, creating I2C traffic. The host workstation sends the 'apreset cold' command to the EC within a few seconds of Chrome OS coming up. First run a special Cr50 image which is not resetting I2CS using PMU on TPM restarts, is was not trying to unwedge the stuck I2C bus. On five experiments, it takes on average 32 reboots for until I2C bus is locked up and the DUT falls into recovery. Then loaded the Cr50 image with this patch and ran the test again, it survived for 150 cycles without a problem. Change-Id: Iffec33f97557e3acfd1cd5fb76ba158f8c23b608 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1730143 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* g: fix UART TX done logicVadim Bendebury2019-09-031-15/+3
| | | | | | | | | | | | | | | | | | | TX is done when both TX_IDLE and TX_EMPTY conditions are true. Fixing the check makes unnecessary the code which waited for another character time before proceeding when flushing the UART TX FIFO. BRANCH=cr50, cr50-mp BUG=b:140305442 TEST=added code to print a really long string before reset in the 'reboot' command, observed that the entire string is reliably printed before the reset. Change-Id: I0882d96ba9ca5412deb704ccdbc43e8cebeeeab5 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1779587 Reviewed-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Andrey Pronin <apronin@chromium.org>
* cr50: added references to FIPS / NIST standards to cryptographic functionsVadim Sukhomlinov2019-08-294-22/+109
| | | | | | | | | | | | | Clarified standards compliance status for cryptographic functions. BRANCH=cr50 BUG=b:138574542 TEST=code compiles, unit tests pass Change-Id: I75ce155b53d1ce049e5063d2aaa1464b75f7d678 Signed-off-by: Vadim Sukhomlinov <sukhomlinov@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1769420 Reviewed-by: Andrey Pronin <apronin@chromium.org>
* include: Move RESET_FLAG_* into ec_commands.h as EC_RESET_FLAG_*You-Cheng Syu2019-08-265-17/+19
| | | | | | | | | | | | | | | | | | | | | | | RESET_FLAGS_* are used when setting/reading the field ec_reset_flags of struct ec_response_uptime_info, which is defined in ec_commands.h. So it might be better to put those macros there. To be consistent with the other macros in the file, add "EC_" prefixes to them. BUG=b:109900671,b:118654976 BRANCH=none TEST=make buildall -j Cq-Depend: chrome-internal:1054910, chrome-internal:1054911, chrome-internal:1045539 Change-Id: If72ec25f1b34d8d46b74479fb4cd09252102aafa Signed-off-by: You-Cheng Syu <youcheng@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1520574 Tested-by: Yu-Ping Wu <yupingso@chromium.org> Commit-Ready: Yu-Ping Wu <yupingso@chromium.org> Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org> Reviewed-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* g: corrected division algorithm in DCRYPTO_bn_divVadim Sukhomlinov2019-08-231-0/+1
| | | | | | | | | | | | | | | Long division algorithm computes incorrect answer in rare cases causing valid RSA signatures to be rejected. BRANCH=cr50 BUG=b:137973895 TEST=tpm_test passes Change-Id: Ie8f39eed21443978734adbbf60b72d7701154c18 Signed-off-by: Vadim Sukhomlinov <sukhomlinov@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1766088 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Andrey Pronin <apronin@chromium.org>
* g: add vendor cmd to get/set the endorsement seedMary Ruthven2019-08-131-1/+64
| | | | | | | | | | | | | | | | We've had some eraseflashinfo issues that cause the endorsement key seed to get lost. Add a vendor command, so we can set the endorsement key seed if it's erased. BUG=b:138943966 BRANCH=none TEST=get/set endorsement key seed. Change-Id: Iee7d78e22f44786efd86b3ec68780a53e567705d Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1740075 Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* cr50: use dedicated region for info1 accessesVadim Bendebury2019-08-105-103/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The INFO1 flash space is used for various purposes (endorsement key seed, Board ID and flags, serial number, etc.). Accessing these spaces in INFO1 is accompanied by managing the flash region registers, each time opening a window of the appropriate size, with appropriate permissions, etc, In fact none of these spaces contain a secret, to simplify things and preventing situations when concurrent accesses change the flash range window settings lets dedicate previously unused Region 7 register file to providing always open read access to INFO1. Write access will be enabled/disabled as required. In prod images write accesses will always happen from the vendor command context. In DBG images CLI commands will also have write access to INFO1. INFO1 window is accessed by other H1 based devices as well, this is why it is necessary to enable the window in the common chip code. BRANCH=cr50, cr50-mp BUG=b:138256149 TEST=the firmware_Cr50SetBoardId test now passes on Mistral. Cq-Depend: chrome-internal:1577866, chrome-internal:1581327 Change-Id: Id27348f3b04191f1b3b60fd838d06009f756baa2 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1730147 Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* g: Make DMEM word writes explicitLouis Collard2019-08-091-85/+104
| | | | | | | | | | | | | | | | | | This change refactors access to DMEM during ECC operations to make all writes explicitly word writes. This is effectively a no-op, but should prevent against any future regressions. BUG=b:131807777 TEST=build and flash on soraka locally, ensure signature of known blob matches signature generated prior to this CL BRANCH=none Signed-off-by: Louis Collard <louiscollard@chromium.org> Change-Id: Ie24712c3f4a5dc15c8ad08cd50b9e8b9cdab2822 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1595928 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* g: refactor pinmux state printing functionVadim Bendebury2019-08-021-10/+20
| | | | | | | | | | | | | | | | | | This refactoring improves optional parameter alignment, includes virtual pads in the output and shaves 44 bytes from the image size. BRANCH=cr50, cr50-mp BUG=none TEST=saved pinmux command output in files pm.before and pm.after, then verified that the following command produced no output $ diff -w <(sort pm.before) <(sort pm.after) Change-Id: I81c2fad8c9e87e05dd39c588340a82f83e3ab488 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1731138 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* g: add flash log entry for dcrypto failuresstabilize-12386.BVadim Bendebury2019-07-311-5/+13
| | | | | | | | | | | | | | | | We want to keep an eye on the dcrypto failures (which are never supposed to happen of course). Let's add logging a flash event so that the failures are visible through UMA. BRANCH=cr50, cr50-mp BUG=b:135772657 TEST=using additional code simulated a single failure, observed new flash log entry by running 'gsctool -a -L' on the DUT. Change-Id: Ib675bb1928166cadc069bf4be3b053a9cf837077 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1723097 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* common/system: refactor some confusing ifdefsJack Rosenthal2019-07-311-0/+3
| | | | | | | | | | | | | | | | | I had a hard time reading this section, so figured I may as well rewrite it to use IS_ENABLED while I was here. Gave CONFIG_{RO,RW}_HEAD_ROOM a default value of zero here, which makes the math work out for boards without it anyway. BUG=none BRANCH=none TEST=buildall Change-Id: I87dc2d73838c350088916b57aa51d5f368c5592f Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1727570 Reviewed-by: Denis Brockus <dbrockus@chromium.org>
* g: Force word writes for k during ECDSA signLouis Collard2019-07-311-4/+13
| | | | | | | | | | | | | | | | | | Functions that take p256_int* parameters may use byte writes when writing to those parameters. When writing to DMEM_ecc, we must use word writes; this change ensures that happens. BUG=b:131807777 TEST=build and flash to soraka locally, ensure k is populated successfully BRANCH=none Change-Id: I49462b10aa1203fe875417e9526f06b2efc068fb Signed-off-by: Louis Collard <louiscollard@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1592990 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Andrey Pronin <apronin@chromium.org>
* g: reset and wipe dcrypto engine after timeout.Marius Schilder2019-07-291-22/+203
| | | | | | | | | | | | | | | | | | | In case of a timeout, we need to clean up state and make sure engine is ready for a subsequent call. Added dcrypto_test console command to test the various scenarios: stack overflow, infinite loop and cfi failure recovery. Signed-off-by: mschilder@google.com BUG=b:135772657 BRANCH=none TEST=run console command dcrypto_test; build and run cr53 Change-Id: I531a59de6f2cf6941c797aeeeabb10eb10f02c9b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1677229 Reviewed-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Tested-by: Marius Schilder <mschilder@chromium.org> Commit-Queue: Marius Schilder <mschilder@chromium.org>
* Remove __7b, __8b and __7bfDenis Brockus2019-07-201-7/+7
| | | | | | | | | | | | | | | | | | | The extentions were added to make the compiler perform most of the verification that the conversion was being done correctly to remove 8bit addressing as the standard I2C/SPI address type. Now that the compiler has verified the code, the extra extentions are being removed BUG=chromium:971296 BRANCH=none TEST=make buildall -j TEST=verify sensor functionality on arcada_ish Change-Id: I36894f8bb9daefb5b31b5e91577708f6f9af2a4f Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1704792 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* Use 7bit I2C/SPI slave addresses in ECDenis Brockus2019-07-191-13/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Opt for 7bit slave addresses in EC code. If 8bit is expected by a driver, make it local and show this in the naming. Use __7b, __7bf and __8b as name extensions for i2c/spi addresses used in the EC codebase. __7b indicates a 7bit address by itself. __7bf indicates a 7bit address with optional flags attached. __8b indicates a 8bit address by itself. Allow space for 10bit addresses, even though this is not currently being used by any of our attached devices. These extensions are for verification purposes only and will be removed in the last pass of this ticket. I want to make sure the variable names reflect the type to help eliminate future 7/8/7-flags confusion. BUG=chromium:971296 BRANCH=none TEST=make buildall -j Change-Id: I2fc3d1b52ce76184492b2aaff3060f486ca45f45 Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1699893 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* cr50: provide separate environment variable to enable crypto testsVadim Bendebury2019-07-171-4/+0
| | | | | | | | | | | | | | | | | | | | Presently the CR50_DEV environment variable is overloaded, if its value is a number exceeding 1, it enables inclusion in the image of the dcrypto tests. To make things cleaner let's use a separate environment variable to add dcrypto tests to the image. Note that the tests still can not be enabled, as they do not fit into the flash code space. BRANCH=cr50, cr50-mp BUG=b:137659935 TEST=verified that image building with CRYPTO_TEST=1 fails due to exceeded code size. Change-Id: I550c219c1eefe01fbe035b85a1d5aae88ea439de Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1704607 Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* g: avoid CERT_28Marius Schilder2019-06-271-19/+1
| | | | | | | | | | | | | | | | | | | | | | | chip/g has a hardware KI with executing CERT_28 more than 512 times after reset. Current use of CERT_28 makes little sense so we address the issue with deletion. While at it, delete a bunch of other useless code in this function. Ultimately we're left with just pulling bits from TRNG and mixing them with entropy from the keyladder as mild hedge. Signed-off-by: mschilder@google.com BUG=b:127343845 BRANCH=none TEST=b:127343845 Change-Id: I84218f644aa2508c45101464512019754647f229 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1646533 Tested-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Marius Schilder <mschilder@chromium.org> Reviewed-by: Andrey Pronin <apronin@chromium.org> Commit-Queue: Marius Schilder <mschilder@chromium.org> Auto-Submit: Marius Schilder <mschilder@chromium.org>
* g: try batching USB stream data under heavy loadVadim Bendebury2019-06-272-55/+143
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | USB TX data rate is much higher than UART RX, this results in USB driver streaming data received from UART in smaller than max size chunks, which in turn means that per byte overhead of shipping USB packets to the host is not as low as it could have been. This patch detects attempt to ship less than full chunk over USB stream and instead of processing data immediately posts a deferred function, which is supposed to triggers another send attempt in a few milliseconds. If there is a high traffic on the stream, the queue would have much more data after deferred interval ends. The problem with the posted deferred function is the fact that it is not guaranteed to run soon enough in case there are other deferred functions waiting. To address this issue an additional check is being introduced to make sure that the USB buffer does not overflow: if the deferred function is posted, and the buffer is half full or more, let's cancel the deferred function and process the stream right away. If the deferred function gets to execute - there is a chance that a UART and or USB interrupt comes while the deferred function is running, which is likely to mess up USB controller settings by tx_stream_handler(). To avoid these issues, interrupts are disabled before the kicker function calls the handler. Note that this optimization applies only to AP and EC console streams. BRANCH=cr50, cr50-mp BUG=b:38448364 TEST=two full chargen streams on an octopus device run indefinitely and don't seem to be interrupting even when some CLI command is ran on the Cr50 console or when an update is uploaded over USB or TPM Change-Id: Id151c494967d1eb15d2af42acf8f2282966b5147 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1672209 Reviewed-by: Namyoon Woo <namyoon@chromium.org>
* g: set up USB TX in USB endpoint interrupt handlerNamyoon Woo2019-06-272-25/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | USB TX used to be set up in a deferred function. This patch makes USB endpoint interrupt handler to setup USB TX to speed up sending data to host USB. It reduces Flash usage by 100 bytes, and RAM usage by 40 bytes. BUG=b:38448364 BRANCH=cr50, cr50-mp TEST=(1) Flashed EC FW on fleex (uut), atlas (npcx_int_spi), ampton (it83xx), bob (npcx_spi), coral (npcx_spi), and scarlet(stm32). (2) Flashed AP FW on fleex. (3) Ran firmware_Cr50DeviceState on Coral. (4) Uart Stress Tester on fleex. [ before applying this CL ] $ uart_stress_tester.sh --pty="/dev/ttyUSB2 /dev/ttyUSB1" --min_char 200000 ........................... ERROR : /dev/ttyUSB2: 1953 lost / 330330 : .5 % ERROR : /dev/ttyUSB1: 451 lost / 200655 : .2 % [ after applying this CL ] $ uart_stress_tester.sh --pty="/dev/ttyUSB2 /dev/ttyUSB1" --min_char 200000 ........................... INFO : /dev/ttyUSB2: 0 lost / 334425 : 0 % INFO : /dev/ttyUSB1: 0 lost / 200655 : 0 % Change-Id: Ic966486f034a199b601ca002f6ed76a73b2b9dd8 Signed-off-by: Namyoon Woo <namyoon@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1574661 Tested-by: Vadim Bendebury <vbendeb@chromium.org> Commit-Queue: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* g: make uart run fasterVadim Bendebury2019-06-241-14/+17
| | | | | | | | | | | | | | | | | | The EC queue library wrappers are very heavy, let's bypass them and use direct queue access where performance matters the most, in the UART RX driver used by USB streams. BUG=b:38448364 BRANCH=cr50, cr50-mp TEST=with the rest of the patches in place observed a much more reliable streaming of two consoles (ec and ap), both pumping chargen streams into their respective UARTs on an Octopus device. Change-Id: I45dc8f1c0841b43e17ef67e96820669053fba831 Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1672208 Reviewed-by: Namyoon Woo <namyoon@chromium.org>
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