| Commit message (Collapse) | Author | Age | Files | Lines |
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Normally we don't do this, but enough changes have accumulated that
we're doing a tree-wide one-off update of the name & style.
BRANCH=none
BUG=chromium:1098010
TEST=`repo upload` works
Change-Id: I5b357b85ae9473a192b80983871bef4ae0d4b16f
Signed-off-by: Mike Frysinger <vapier@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3893394
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Enable handling reset in AON code for ish 5.4 on tgl rvp.
BUG=b:176689775
BRANCH=none
TEST=ish reset properly when host reboot.
Signed-off-by: Leifu Zhao <leifu.zhao@intel.com>
Change-Id: I9d53d668bf5b459e21519cab4fcaa28c753ff266
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2607954
Reviewed-by: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Tested-by: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com>
Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
Auto-Submit: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Google is working to change its source code to use more inclusive
language. To that end, replace the terms "sane", "sanity check", and
similar with inclusive/non-stigmatizing alternatives.
BUG=b:161832469
BRANCH=None
TEST=`make buildall -j` succeeds. `grep -Eir "sane|sanity" .` shows
results only in third-party code or documentation.
Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org>
Change-Id: I29e78ab27f84f17b1ded75cfa10868fa4e5ae88c
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2311169
Reviewed-by: Jett Rink <jettrink@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Enable ip accessible power gating for ish 5.4 on tgl rvp platform.
BUG=b:154891699
BRANCH=none
TEST=ISH can successfully enter into IPAPG on tgl rvp.
Change-Id: Iee30124a0928389f4c75dffff065fab7a5a2d970
Signed-off-by: Leifu Zhao <leifu.zhao@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2164091
Reviewed-by: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Tested-by: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com>
Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
Auto-Submit: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Chip level power management enablement for ish5.4.
BUG=b:149238813
BRANCH=none
TEST=ISH can successfully enter into D0i1/D0i2/D0i3 on tgl rvp.
Signed-off-by: Leifu Zhao <leifu.zhao@intel.com>
Change-Id: Icc554a68fe57970bcaa7be457f56db34067858d9
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2055895
Reviewed-by: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Tested-by: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com>
Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
Auto-Submit: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
The following bug
https://buganizer.corp.google.com/issues/136002955
indicates after my initial move of snowball to use the
linker map instead of hard defined addresses that
0xFF801E80 was reading back as all zeroes.
The change that was made for this is
https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1664593
I double checked the map files and everything looked
good. For some reason using the linker to map the location
of this structure, the system does not run properly.
If I remove the link map placement of this structure
then the issue goes away. I looked at how aon_share
was placed at the specific address in AON memory and
this CL is doing the same thing and it is working.
I think this is the way we should keep this fix and not
try to get the linker map to place this structure where
we want it.
BUG=b:136002955
BRANCH=none
TEST=make buildall -j
TEST=verify soft reboot does not indicate power reset
Change-Id: Ibb6dbd3a4414b5c546e99f5ad7e0409250de6256
Signed-off-by: Denis Brockus <dbrockus@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1707998
Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
aon task image build rules are lack of dependent rules of source code,
so can't track the source code changes and trigger auto build.
Refactor build rules for aon task to make sure always auto rebuild when
aon task's source code and dependent header files update
BUG=b:136691893
BRANCH=none
TEST= ish aon task should always rebuild when it's code and dependent
header files update
Change-Id: I0d8c7c6a4a2b7e99d724b88b233e09a29b8facea
Signed-off-by: Hu, Hebo <hebo.hu@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1688701
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Hebo Hu <hebo.hu@intel.corp-partner.google.com>
Tested-by: Hebo Hu <hebo.hu@intel.corp-partner.google.com>
Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Before switch to aon task, cache and ROM will be power gated
(PMU_RF_ROM_PWR_CTRL control register) in ecos, and resume after
switched back to ecos.
But for reset_prep/D3 process, aon task will reset minute ia to ROM
finally but forget to resume the power of ROM. This keeps ROM still
power gated and make ROM code can't run correctly.
The fix is simple, just disable power gating of ROM before reset to ROM
in aon task.
BUG=b:136265450
BRANCH=none
TEST=ISH fw should always load
Change-Id: Ib26678bbfdd5dbb17389154478f2565c44d392ab
Signed-off-by: Hu, Hebo <hebo.hu@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1684825
Reviewed-by: Hebo Hu <hebo.hu@intel.corp-partner.google.com>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Tested-by: Yangzhong Ge <yangzhong.ge@intel.corp-partner.google.com>
Tested-by: Jack Rosenthal <jrosenth@chromium.org>
Commit-Queue: Jett Rink <jettrink@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Refactor D3 entry to use ish_pm_reset, as it performs the same
operations modulo the pm_state, save persistent data when entering D3.
BUG=b:134089952
BRANCH=none
TEST=rmmod ish modules, insmod again on arcada
Change-Id: Ifed49d49d42b55cd220ff5d8e8d98843d28dfa22
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1674470
Reviewed-by: Hebo Hu <hebo.hu@intel.corp-partner.google.com>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Change AON_ROM references to be AON_PERSISTENT, these are not readonly
Use the linker to set a snowball structure in the right place so we do
not have to maintain hardcoded addresses in the register file
BUG=b:132690500
BRANCH=none
TEST=make buildall -j and check map location of snowball to be correct
Change-Id: I4983a078fbd067b9c7ec9f0c49f962a4cb1581b7
Signed-off-by: Denis Brockus <dbrockus@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1664593
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Removed many of the #if conditions and replaced them with IS_ENABLED
BUG=b:132178013
BRANCH=none
TEST=make buildall -j
TEST=verify basic ish ec functionality
Change-Id: I39c1d2dfdb39baa06e53746789d0b6a648275ed9
Signed-off-by: Denis Brockus <dbrockus@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1660021
Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Removed some unneeded definitions and made sure those needed were
undefined in include/config.h
Removed some of the #ifdef and used IS_ENABLED instead
2019-06-13 07:36:00 > idlestats
2019-06-13 07:36:05 Aontask exists: Yes
2019-06-13 07:36:05 Total time on: 367.111999s
2019-06-13 07:36:05 Idle sleep:
2019-06-13 07:36:05 D0i0:
2019-06-13 07:36:05 counts: 13716
2019-06-13 07:36:05 time: 108.238220s
2019-06-13 07:36:05 Deep sleep:
2019-06-13 07:36:05 D0i1:
2019-06-13 07:36:05 counts: 6798
2019-06-13 07:36:05 time: 17.980105s
2019-06-13 07:36:05 D0i2:
2019-06-13 07:36:05 counts: 5852
2019-06-13 07:36:05 time: 236.773953s
2019-06-13 07:36:05 D0i3:
2019-06-13 07:36:05 counts: 16
2019-06-13 07:36:05 time: 1.092285s
2019-06-13 07:36:05 Aontask status:
2019-06-13 07:36:05 last error: 0
2019-06-13 07:36:05 error counts: 0
BUG=b:131749055,b:132178013
BRANCH=none
TEST=make buildall -j
TEST=verified basic operation on arcada_ish
Change-Id: Ib2d96f35b9f4f92208cd05dfdf2580bb27e5df90
Signed-off-by: Denis Brockus <dbrockus@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1656152
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Move persistent data definitions to a structure and have linker script
define the address of the symbol into the AON ROM (persistent data
storage). Use the magic number "ISHd" to verify persistent data
storage and copy to static memory when valid. Commit changes from the
local copy during reset.
BUG=b:133779707,b:133647823,b:132059981
BRANCH=none
TEST=power-on is only reset flag under cold reset, panic data
persists, watchdog reset produces correct reset flags, UART always
printing system info on boot
Change-Id: I65a458cc2656f8fe26361ef2117ceb5439edff6c
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1636293
Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
We need to reserve some space in AON persistent memory not to be used
by the shim loader. This memory will be used for panic data, reset
flags, and watchdog reset counter. We can reduce the size of the panic
data for further soft-registers, as needed.
Each of these things will be moved into the reserved section in a
child CL.
BUG=b:132457636
BRANCH=none
TEST=entered d0i0, d0i1, d0i2, d0i3, and rebooted to test aontaskfw is
working
Change-Id: I41f39d28a6b5a3424f1c89b0e0884e72df04225f
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1610997
Reviewed-by: Jett Rink <jettrink@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
BRANCH=none
BUG=none
TEST=ISH still reset properly on arcada
Change-Id: I08a5935c5e8d1728e2984cbc70d75e380eb66f55
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1601349
Reviewed-by: Hebo Hu <hebo.hu@intel.corp-partner.google.com>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
ISH PMU does not support both-edge interrupt triggered gpio configuration.
If both edges are configured, then the ISH can't stay in low power mode
because it will exit immediately.
As a W/A, we scan all gpio pins which have been configured as both-edge
triggered, and then temporarily set each gpio pin to the single edge
trigger that is opposite of its value, then restore the both-edge
trigger configuration immediately after exiting low power mode.
BUG=b:132001235
BRANCH=none
TEST= tested on arcada platform, console should freeze after entered low
power mode
Change-Id: I83a43d9fbee6cfd1a6820bdb44c1446f109ffb32
Signed-off-by: Hu, Hebo <hebo.hu@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/1600310
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Hebo Hu <hebo.hu@intel.corp-partner.google.com>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
ECOS will reload watchdog in hook task for every HOOK_TICK_INTERVAL
time, and this will make HPET timer 1 wakeup ish. Therefore, we do not
need to disable watchdog during D0ix.
D3 and reset prep flow still need disable watchdog.
BUG=b:132112137
BRANCH=none
TEST='waitms 10500' console command can trigger watchdog timeout and
ish reboot
Change-Id: I11aad5ece0ce96bc53738512290c1e42bf175479
Signed-off-by: Hu, Hebo <hebo.hu@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/1598713
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Hebo Hu <hebo.hu@intel.corp-partner.google.com>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Some people have been bypassing the pre-submit checks:
confs=($(grep -Eor "\bCONFIG_[A-Z_]*" chip/ish/config_chip.h
| sort | uniq))
for opt in "${confs[@]}"; do
grep "$opt" include/config.h >/dev/null ||
echo "$opt is not defined in include/config.h!"
done
>>>
CONFIG_ISH_AON_SRAM_BASE_END is not defined in include/config.h!
CONFIG_ISH_AON_SRAM_BASE_START is not defined in include/config.h!
CONFIG_ISH_AON_SRAM_ROM_SIZE is not defined in include/config.h!
CONFIG_ISH_AON_SRAM_ROM_START is not defined in include/config.h!
CONFIG_ISH_AON_SRAM_SIZE is not defined in include/config.h!
CONFIG_ISH_SRAM_BANKS is not defined in include/config.h!
CONFIG_ISH_SRAM_BANK_SIZE is not defined in include/config.h!
CONFIG_ISH_SRAM_BASE_END is not defined in include/config.h!
CONFIG_ISH_SRAM_BASE_START is not defined in include/config.h!
CONFIG_ISH_SRAM_SIZE is not defined in include/config.h!
This is not good! This commit renames each of these to an existing
option defined in include/config.h, or undefs the relevant option in
include/config.h.
BUG=b:131749055
BRANCH=none
TEST=make buildall -j
TEST=script above reports no options which weren't defined
TEST=arcada_ish, (specifically power management, which was greatly
affected by this commit) functions as normal
Change-Id: Idfbd1105880174b5e160c47c4ec1d88c352d6bc6
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1592420
Reviewed-by: Jett Rink <jettrink@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
This is the final CL needed to resolve b:130573158.
BUG=b:130573158
BRANCH=none
TEST=arcada_ish functions as normal after changes
Change-Id: Ia4cc9bfa95938b9f57fc1cd241cd6821b42a3ce6
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1578435
Reviewed-by: Jett Rink <jettrink@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
This is a good portion of the fixes needed for b:130573158, but we
still have the HECI registers to deal with. I have those in a separate
CL as they were giving me a significant amount of trouble.
BUG=b:130573158
BRANCH=none
TEST=arcada_ish is functioning as normal after changes
Change-Id: I9c209a329d61f7f55c260006cdffbfc705521195
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1586458
Reviewed-by: Jett Rink <jettrink@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
We should be using the BIT(n) macro rather than (1 << n), as it
prevents errors, and makes the intended purpose a little bit easier to
read.
BRANCH=none
BUG=none
TEST=make buildall -j
Change-Id: Ia727ac2f8e5abfb852ba78d5cba19d7c8af72839
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1567688
Reviewed-by: Jett Rink <jettrink@chromium.org>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
1: reset and reset_prep implemented
2: D3 flow implemented
BUG=b:122364080
BRANCH=none
TEST=tested on arcada
Change-Id: Ie6bacd89e2363578d85157dfb1dd8b56e2828d05
Signed-off-by: Hu, Hebo <hebo.hu@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/1536486
Commit-Ready: Hebo Hu <hebo.hu@intel.corp-partner.google.com>
Tested-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Hebo Hu <hebo.hu@intel.corp-partner.google.com>
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
1: D0i1(TCG) and D0i2(TCG + SRAM retention) implemented
2: D0i3 (TCG + SRAM power off) implemented
BUG=b:122364080
BRANCH=none
TEST=tested on arcada
Change-Id: I851d7c138b056a92d1616622e7cbfdfb94d86e5c
Signed-off-by: Hu, Hebo <hebo.hu@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/1531772
Commit-Ready: Hebo Hu <hebo.hu@intel.corp-partner.google.com>
Tested-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Hebo Hu <hebo.hu@intel.corp-partner.google.com>
|
|
AON PM framework including:
1: AON task skeleton
2: task switching between main FW and AON task
3: 'idlestats' console command for D0ix statistic information
4: D0ix entrance in idle task
BUG=b:122364080
BRANCH=none
TEST=tested on arcada
Change-Id: Iefa9e067892d5c42d9f0c795275fe88e5a36115b
Signed-off-by: Hu, Hebo <hebo.hu@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/1510518
Commit-Ready: Rushikesh S Kadam <rushikesh.s.kadam@intel.com>
Commit-Ready: Hebo Hu <hebo.hu@intel.corp-partner.google.com>
Tested-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Hebo Hu <hebo.hu@intel.corp-partner.google.com>
|