| Commit message (Collapse) | Author | Age | Files | Lines |
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Normally we don't do this, but enough changes have accumulated that
we're doing a tree-wide one-off update of the name & style.
BRANCH=none
BUG=chromium:1098010
TEST=`repo upload` works
Change-Id: I5b357b85ae9473a192b80983871bef4ae0d4b16f
Signed-off-by: Mike Frysinger <vapier@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3893394
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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Infrastructure related changes to support enabling power management
for ish5.4 on tgl rvp platform.
BUG=b:149238813
BRANCH=none
TEST=ISH can successfully enter into D0i1/D0i2/D0i3 on tgl rvp.
Signed-off-by: Leifu Zhao <leifu.zhao@intel.com>
Change-Id: I50b6f1a4fe9c14f9479af2a2a438ec7395ec27a1
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2056149
Reviewed-by: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Tested-by: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com>
Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
Auto-Submit: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com>
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Chip level enablement of ish5.4 on tgl rvp platform.
BUG=b:141519691
BRANCH=none
TEST=tested on tgl rvp
Signed-off-by: Leifu Zhao <leifu.zhao@intel.com>
Change-Id: I3f6249e1816d81deec0420a12b093918ee7fbddc
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1846788
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com>
Commit-Queue: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com>
Tested-by: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com>
Auto-Submit: Leifu Zhao <leifu.zhao@intel.corp-partner.google.com>
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ISH has native support for storing the hardware ticks in a 64-bit
integer. With CONFIG_HWTIMER_64BIT, we can use this instead of relying
on the periodic rollover interrupt.
BUG=b:133190570,chromium:976804
BRANCH=none
TEST=ran arcada_ish for more than 2³² μs, observed timer worked as
normal
Change-Id: I3b608c49081842f28d2ef8c16279992af1cb4fad
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1668056
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
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For interrupt vectors (as opposed to exception handlers), the eip
value is on top of the stack (referentially the return address by C
calling convention). Use separate code for WDT vector.
BUG=b:129983997
BRANCH=none
TEST='crash watchdog' showing correct EIP, CS values
Change-Id: I7efb2c71aba63eefd89fc71af089bc14034b7d08
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1663188
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
Reviewed-by: Yuval Peress <peress@chromium.org>
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Change AON_ROM references to be AON_PERSISTENT, these are not readonly
Use the linker to set a snowball structure in the right place so we do
not have to maintain hardcoded addresses in the register file
BUG=b:132690500
BRANCH=none
TEST=make buildall -j and check map location of snowball to be correct
Change-Id: I4983a078fbd067b9c7ec9f0c49f962a4cb1581b7
Signed-off-by: Denis Brockus <dbrockus@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1664593
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
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Move persistent data definitions to a structure and have linker script
define the address of the symbol into the AON ROM (persistent data
storage). Use the magic number "ISHd" to verify persistent data
storage and copy to static memory when valid. Commit changes from the
local copy during reset.
BUG=b:133779707,b:133647823,b:132059981
BRANCH=none
TEST=power-on is only reset flag under cold reset, panic data
persists, watchdog reset produces correct reset flags, UART always
printing system info on boot
Change-Id: I65a458cc2656f8fe26361ef2117ceb5439edff6c
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1636293
Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org>
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Currently the panic data is placed in a region that conflicts with the
aontaskfw stack. With the extended ROM space, we can put the panic
data in a safer location.
BUG=b:132457636
BRANCH=none
TEST=ran 'crash divzero', observed the panic data copy across reset
without any issues
Change-Id: I876f3f071e000017c8f2ee744838711da928857c
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1610998
Reviewed-by: Jett Rink <jettrink@chromium.org>
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We need to reserve some space in AON persistent memory not to be used
by the shim loader. This memory will be used for panic data, reset
flags, and watchdog reset counter. We can reduce the size of the panic
data for further soft-registers, as needed.
Each of these things will be moved into the reserved section in a
child CL.
BUG=b:132457636
BRANCH=none
TEST=entered d0i0, d0i1, d0i2, d0i3, and rebooted to test aontaskfw is
working
Change-Id: I41f39d28a6b5a3424f1c89b0e0884e72df04225f
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1610997
Reviewed-by: Jett Rink <jettrink@chromium.org>
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This commit stores panic data across reset by storing panic data in
the last 256 bytes of AON memory (before AON ROM).
> crash divzero
========== PANIC ==========
Reason: Divide By Zero
Error Code = 0xFF00B60C
EIP = 0xFF010008
CS = 0x00010202
EFLAGS = 0x00103085
EAX = 0x00000001
EBX = 0xFF01B118
ECX = 0x00000000
EDX = 0x00000000
ESI = 0x00000000
EDI = 0xFF017E0E
Resetting system...
===========================
... ISH reset ...
> panicinfo
Saved panic data: (NEW)
Reason: Divide By Zero
Error Code = 0xFF00B60C
EIP = 0xFF010008
CS = 0x00010202
EFLAGS = 0x00103085
EAX = 0x00000001
EBX = 0xFF01B118
ECX = 0x00000000
EDX = 0x00000000
ESI = 0x00000000
EDI = 0xFF017E0E
BUG=b:129425206
BRANCH=none
TEST=see console output above (on arcada_ish)
Change-Id: I5c9e458b53076eafe7fa50ba851f2c6e863f2247
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1593418
Reviewed-by: Jett Rink <jettrink@chromium.org>
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Some people have been bypassing the pre-submit checks:
confs=($(grep -Eor "\bCONFIG_[A-Z_]*" chip/ish/config_chip.h
| sort | uniq))
for opt in "${confs[@]}"; do
grep "$opt" include/config.h >/dev/null ||
echo "$opt is not defined in include/config.h!"
done
>>>
CONFIG_ISH_AON_SRAM_BASE_END is not defined in include/config.h!
CONFIG_ISH_AON_SRAM_BASE_START is not defined in include/config.h!
CONFIG_ISH_AON_SRAM_ROM_SIZE is not defined in include/config.h!
CONFIG_ISH_AON_SRAM_ROM_START is not defined in include/config.h!
CONFIG_ISH_AON_SRAM_SIZE is not defined in include/config.h!
CONFIG_ISH_SRAM_BANKS is not defined in include/config.h!
CONFIG_ISH_SRAM_BANK_SIZE is not defined in include/config.h!
CONFIG_ISH_SRAM_BASE_END is not defined in include/config.h!
CONFIG_ISH_SRAM_BASE_START is not defined in include/config.h!
CONFIG_ISH_SRAM_SIZE is not defined in include/config.h!
This is not good! This commit renames each of these to an existing
option defined in include/config.h, or undefs the relevant option in
include/config.h.
BUG=b:131749055
BRANCH=none
TEST=make buildall -j
TEST=script above reports no options which weren't defined
TEST=arcada_ish, (specifically power management, which was greatly
affected by this commit) functions as normal
Change-Id: Idfbd1105880174b5e160c47c4ec1d88c352d6bc6
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1592420
Reviewed-by: Jett Rink <jettrink@chromium.org>
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1: D0i1(TCG) and D0i2(TCG + SRAM retention) implemented
2: D0i3 (TCG + SRAM power off) implemented
BUG=b:122364080
BRANCH=none
TEST=tested on arcada
Change-Id: I851d7c138b056a92d1616622e7cbfdfb94d86e5c
Signed-off-by: Hu, Hebo <hebo.hu@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/1531772
Commit-Ready: Hebo Hu <hebo.hu@intel.corp-partner.google.com>
Tested-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Hebo Hu <hebo.hu@intel.corp-partner.google.com>
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AON PM framework including:
1: AON task skeleton
2: task switching between main FW and AON task
3: 'idlestats' console command for D0ix statistic information
4: D0ix entrance in idle task
BUG=b:122364080
BRANCH=none
TEST=tested on arcada
Change-Id: Iefa9e067892d5c42d9f0c795275fe88e5a36115b
Signed-off-by: Hu, Hebo <hebo.hu@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/1510518
Commit-Ready: Rushikesh S Kadam <rushikesh.s.kadam@intel.com>
Commit-Ready: Hebo Hu <hebo.hu@intel.corp-partner.google.com>
Tested-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Hebo Hu <hebo.hu@intel.corp-partner.google.com>
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This adds support for the watchdog timer (WDT) available on Intel Sensor
Hub (ISH). The ISH will reset after T1 expires; see the comments at the
top of watchdog.c for further information on this design decision.
Originally, we had planned to implement a counter that would disable the
WDT after N failures. This was abandoned, since the register used to
store the counter was not able to maintain a value across reset on a
reliable basis (see b:128679825).
BUG=b:127980538,b:128679825
BRANCH=none
TEST=Used waitms command on arcada to verify WDT triggered a warning
IRQ after T1 and reset the system.
Change-Id: I4bd16c253110d60c57eb24cda2abc0facee20748
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1526316
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Reviewed-by: Jett Rink <jettrink@chromium.org>
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Remove all ISH related CONFIG_* options except for:
CONFIG_HOSTCMD_HECI: This will be used to enable the host command
interface using HECI. Similar to CONFIG_HOSTCMD_LPC or
CONFIG_HOSTCMD_ESPI. arcada_ish uses this config.
CONFIG_HID_HECI: This will be used to enable a HID interface using
HECI. It is compatible with the intel-ish-hid kernel driver. atlas_ish
uses this config.
Also remove ipc.c the functionality it has been superceded by
ipc_heci.c.
BUG=b:123634700
TEST=Built and tested on a arcada device
Verified that atlas_ish builds
BRANCH=none
Change-Id: I9d97693e2beca1c9fec8c4f17bd3706b0ea8e795
Signed-off-by: Mathew King <mathewk@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1490551
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Reviewed-by: Jett Rink <jettrink@chromium.org>
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Previously when performing 'taskinfo' command on ISH5, the time spend in
exception was very high. The time spent in each task was also negative.
The task profiling was broken in many ways. This CL fixes the following:
- Added correct exception start and end times through out
- Updated exception (isr) start and end time to 32-bit so we don't
have issues with 32-bit time rollover
- Fixed time spending in task, exception, and IRQ distribution
- Fixed code that determines which vector is being serviced. Calculation
before was backwards previously.
- The IRQ_COUNT for ish was too small so we couldn't correctly
profile the IRQ distribution
BRANCH=none
BUG=b:121343650,b:112750896
TEST='taskinfo' behaves correctly on aracada (ISH5)
Change-Id: I643d3133a608865a1862a70585cfeced4d24649d
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1389058
Reviewed-by: Hyungwoo Yang <hyungwoo.yang@intel.com>
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- Support for 2 or more bytes size of command register
in slave device.
- Adjust parameters for FAST and FAST+ modes.
- added Restart and SCL stretch
BUG=b:113238573
TEST=test with FAST/FAST+ mode Elan TrackPad slave device.
Use i2c_xfer() API inside a test task which GPIO interrupt
(Elan device's INT line) wakes.
Change-Id: I1ebcef90d85d6ede90bb8687e20058bdf31bf4e8
Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/996799
Commit-Ready: Caveh Jalali <caveh@google.com>
Commit-Ready: Kyoung Il Kim <kyoung.il.kim@intel.com>
Tested-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
Reviewed-by: Caveh Jalali <caveh@google.com>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
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Remove flag related to IPC interface & Host command protocol
to add new IPC & HECI protocol
BUG=b:79676054
TEST=none
Change-Id: I4707e2845c38a4d86ab8bffad93f7024fa9e5eb5
Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/1263896
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
Reviewed-by: Caveh Jalali <caveh@google.com>
Reviewed-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
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BUG=b:116451255
BRANCH=none
TEST=Tested on Atlas board with ISH.
Change-Id: I6b3913d2374e68e9522927ad5609f2867cc56f34
Signed-off-by: li feng <li1.feng@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/885007
Commit-Ready: Li1 Feng <li1.feng@intel.com>
Tested-by: Li1 Feng <li1.feng@intel.com>
Reviewed-by: Caveh Jalali <caveh@google.com>
Reviewed-by: Li1 Feng <li1.feng@intel.com>
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Widen the flags field from 16-bit to 32-bit to fit all of the
current GPIO_flags. Also reorder fields within struct to allow arm
compiler to use 16-bit instructions instead of 32-bit instructions when
accessing fields (which is important for kevin board, otherwise
it runs out of space)
Lastly, re-tool macros to all reordering of gpio_alt_func struct fields.
BRANCH=none
BUG=b:109884927
TEST=builds on all boards
Change-Id: I20b136c94a607c19031a88bddd255cc34cc57bbd
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1096018
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
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Break the ec chip code up with the more granular
CONFIG_HOSTCMD_(X86|LPC|ESPI) options.
BRANCH=none
BUG=chromium:818804
TEST=Full stack builds and works on yorp (espi) and grunt (lpc)
Change-Id: Ie272787b2425175fe36b06fcdeeee90ec5ccbe95
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1067502
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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This patch adds the initial support for ISH chip to enable the EC
firmware to boot on Intel Integrated Sensor Hub (ISH). The following are
enabled:
1. Inter-Processor Communication (IPC) driver that enables the ISH to
communicate with the host Operating system via shared registers.
2. High Precision Event Timer (HPET) driver that provides configurable
timers for the FW to use in task scheduling.
3. I2C bus driver for accessing sensors.
4. UART console driver with TX support only.
BUG=chrome-os-partner:51851
BRANCH=None
TEST=`make buildall -j`
Change-Id: I15d4c201b799cfa79bed220ee573b75f5cd7b1f7
Signed-off-by: Jaiber John <jaiber.j.john@intel.com>
Signed-off-by: Alex Brill <alexander.brill@intel.com>
Signed-off-by: Gomathi Kumar <gomathi.kumar@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/336710
Commit-Ready: Raj Mojumder <raj.mojumder@intel.com>
Tested-by: Jaiber J John <jaiber.j.john@intel.com>
Tested-by: Raj Mojumder <raj.mojumder@intel.com>
Reviewed-by: Jaiber J John <jaiber.j.john@intel.com>
Reviewed-by: Raj Mojumder <raj.mojumder@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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