| Commit message (Collapse) | Author | Age | Files | Lines |
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In the interest of making long-term branch maintenance incur as little
technical debt on us as possible, we should not maintain any files on
the branch we are not actually using.
This has the added effect of making it extremely clear when merging CLs
from the main branch when changes have the possibility to affect us.
The follow-on CL adds a convenience script to actually pull updates from
the main branch and generate a CL for the update.
BUG=b:204206272
BRANCH=ish
TEST=make BOARD=arcada_ish && make BOARD=drallion_ish
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I17e4694c38219b5a0823e0a3e55a28d1348f4b18
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3262038
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Tom Hughes <tomhughes@chromium.org>
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This renames the ITE chip specific SPI IRQ config from
IT83XX_IRQ_SPI_SLAVE to IT83XX_IRQ_SPI_PERIPHERAL.
BRANCH=none
BUG=b:181607131
TEST=compare_build.sh matches
Change-Id: Ib7a7674e6cf4f0bf81ee47b5f60225f77236f578
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3061913
Commit-Queue: Harry Cutts <hcutts@chromium.org>
Reviewed-by: Harry Cutts <hcutts@chromium.org>
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Separate pd interrupt functions to ite_pd_intc for
easier maintenance on cros_ec and zephyr.
And enable PD interrupt functions for zephyr.
BRANCH=none
BUG=none
TEST=1.can zmake hayato and make asurada
2.PD port functions work on board hayato
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Change-Id: I67082bb442da7dfb669e23d8315d81f4abe7ba76
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2999358
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
Reviewed-by: Keith Short <keithshort@chromium.org>
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This header file is used from quite a few files, relying on the EC
build system to find includes in the driver/tcpm directory. For Zephyr
we don't want to add that as an include.
It makes more sense for header files to be in an include directory, so
move it and fix up the users.
BUG=b:175434113
BRANCH=none
TEST=build Zephyr and ECOS on volteer
Signed-off-by: Simon Glass <sjg@chromium.org>
Change-Id: I5851914b1a7d3fdc1ba911c0fbe9046afbaf6f5d
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2597985
Reviewed-by: Keith Short <keithshort@chromium.org>
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Rename function name from it83xx_* to it8xxx2_* for it8xxx2 driver.
Rename function name from *_tcpm_sw_reset to *_tcpm_hook_disconnect.
BUG=none
BRANCH=none
TEST=make BOARD=drawcia -j
make BOARD=asurada -j
Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw>
Change-Id: I8111ec5b9972d1badae625e87248c62e99eabbf6
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2598298
Tested-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
Commit-Queue: Ruibin Chang <Ruibin.Chang@ite.com.tw>
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There is an option in the task_set_event function which force
the calling task to wait for an event. However, the option is never
used thus remove it.
This also will help in the Zephyr migration process.
BUG=b:172360521
BRANCH=none
TEST=make buildall
Signed-off-by: Dawid Niedzwiecki <dn@semihalf.com>
Change-Id: Ic152fd3d6862d487bcc0024c48d136556c0b81bc
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2521599
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Tom Hughes <tomhughes@chromium.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
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BUG=none
TEST=validate volteer build (i2c_peripheral.c is not used by any boards)
BRANCH=none
Signed-off-by: dossym@chromium.org
Change-Id: Ib2d78dc3fc9f4f189f84409cf43ab96788c429be
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2587227
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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Rename CONFIG_I2C_PERIPHERAL and related comments.
BRANCH=None
BUG=None
TEST=make -j buildall
Signed-off-by: Diana Z <dzigterman@chromium.org>
Change-Id: I3f148e976f3a4d6a1dc6c58686368c056290d5d4
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2518660
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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Rename CONFIG_I2C_CONTROLLER and related comments.
BRANCH=None
BUG=None
TEST=make -j buildall
Signed-off-by: Diana Z <dzigterman@chromium.org>
Change-Id: Ied6a1829bf54a5c9a32e6772982a4b8aa31aaf23
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2518659
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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Implement detect cc disconnection interrupt for source. When TCPC
detect SNK/audio/debug device plug out (cc lines open), TCPC can
interrupt pd task to update cc state.
BUG=b:160548079
BRANCH=none
TEST=test on board reef_it8320, it81202_pdevb with TCPMv1, TCPMv2.
Connect to dongle, adapter and DRP, check
1.Plug in/out interrupt fire correctly.
2.Power role swap can state to SRC_READY and SNK_READY.
3.When partner disconnect, we discharge Vconn within
tVconnOFF(35ms).
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Change-Id: I58bc8a5a9289df4ea4e8b3efec000d3a9ab1cb5d
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2294626
Reviewed-by: Jett Rink <jettrink@chromium.org>
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Implement fast role swap function from initial SNK to new SRC
for chip it8320 and it81202.
BUG=none
BRANCH=none
TEST=1.When we detect FRS cc low signal, we can output properly
GPIO signal.
2.FRS false-positives test: PD traffic(ex.power nego,
data and power swap, soft and hard reset) on the CC line
after FRS is enabled.
Change-Id: I3a7bc6a684e57fb19e50c41305751b2fca1ffe2d
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1786462
Reviewed-by: Diana Z <dzigterman@chromium.org>
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When we receive hard reset, we should do Vbus on-off cycle
and should keep cc connection. So I change the event setting
from PD_EVENT_TCPC_RESET to PD_EVENT_RX_HARD_RESET for ITE TCPC.
Stand alone TCPCs also use hard reset event instead of calling
pd_execute_hard_reset(), because waked up pd_task() may have chance
setting to other state.
BRANCH=None
BUG=b:159394180
TEST=On board reef_it8320, and it81202_pdevb:
1.TCPMv1: Rx Hard reset -> done Vbus cycle, and keep cc connection,
When we're SRC and SNK.
2.TCPMv2: Rx Hard reset -> done Vbus cycle, and keep cc connection,
When we're SRC and SNK.
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Change-Id: Ie94757580e8fed4fb33896f9c1e071def49ff03d
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2284504
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
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Getting source interrupt number is chip specific. Moves the details to
chip implementation.
BRANCH=none
BUG=b:151897847
TEST=1. make BOARD=asurada
2. flash_ec --board=asurada --image build/asurada/ec.bin
3. (EC console)> version
Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org>
Change-Id: Ia72acf8ec9c09cb329f8d7c92d22476512ffa669
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2114951
Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
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Add voltage comparator feature.
BUG=b:149094481
BRANCH=none
TEST=on board it83xx_evb,
1.set VCMP1 threshold 2.8v: external input 3v,
the INT would be triggered and ADC5 read the correctly voltage.
2.set VCMP0 threshold 0.2v: external input 0v,
the INT would be triggered and ADC5 read the correctly voltage.
Change-Id: I59510b1c6bd38004ff06e0fcbd2a671e895d59e3
Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2062110
Tested-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Reviewed-by: Diana Z <dzigterman@chromium.org>
Commit-Queue: Ruibin Chang <Ruibin.Chang@ite.com.tw>
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Add PD driver for chip it8xxx1/8xxx2 series.
BRANCH=none
BUG=none
TEST=test below functions on PDEVB port0, 1, 2 with TCPMv1
(set cc toggle by console cmd):
1.pin configuration
console cmd "gpioget" check gpio settings.
memory dump check cc pin alternate settings.
2.Tx data error handle
Message discard, No GoodCRC, Tx not enable, Timeout
errors happen, corresponding INT will be triggered
then do properly handle.
3.basic pd connection
SNK:connect with adaptor, request max power (15V,3A),
state SNK_READY.
SRC:enable DRP role,
connect with dongle, provide power (5V,1.5A),
source Vconn 5v, get ack of cable discover id,
state SRC_READY.
4.pd module disable
SNK:connect with adapter.
console cmd "hibernate sec", driver disable pd module,
check still connection with adapter via dead battery rd.
And when resume from hibernate, pd init can re-enable
pd module, re-connect with adapter.
SRC:connect with dongle.
console cmd "hibernate sec", driver disable pd module,
check cc pin (not Vconn source pin) volt power down
to ~0v. And when resume from hibernate, pd init can
re-enable pd module, re-connect with dongle.
5.Tx hard reset
console cmd "pd port hard", check hard reset message by
lecroy analyzer.
6.Tx cable reset
check cable reset message by lecroy analyzer.
7.SOP' enable
SRC:connects to SNK via E-mark cable.
Source Vconn successfully, and receives cable's ack
of discover id request.
Not source Vconn to cable, and receives nothing
of discover id request (this isn't effect on
request SNK flow).
8.power role swap
console cmd "pd port swap power", check pd protocol
by lecroy.
Change-Id: I687e0e65e2687ebbb790eb1e1c8c459305f4dbc1
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2009538
Reviewed-by: Jett Rink <jettrink@chromium.org>
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Add the spi slave function which is required to
communicate with the EC when the CPU is the ARM
processor.
BUG=none
BRANCH=none
TEST=Replaced board elm's EC with it83202 and
boot kernel and keyboard work.
Change-Id: I7ce3bb56450276997b58e84b1c6de3f8e45bb4b7
Signed-off-by: tim <tim2.lin@ite.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1918991
Reviewed-by: Jett Rink <jettrink@chromium.org>
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This reverts commit bd19b03b128db664dfb5e6582810bd177b635408.
With https://crrev.com/c/1757596/ merged, one doesn't need to
handle repeated MessageID in TCPC.
TEST=make buildall
BUG=b:134556286
BRANCH=none
Change-Id: I0f97e4e574b94ecbc23e5ee97ade7cc4da7f9020
Signed-off-by: Yilun Lin <yllin@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1763895
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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The I2C function of IT8320 is used as the slave.
The slave channel A can support 16-byte FIFO for
read and write data. The enhanced I2C channel D,
E and F can support read and write 256-byte data
by DMA mode.
When master transmits data to slave, the interrupt
signal will generate, and the data will be saved
to buffer.
BUG=none
BRANCH=none
TEST=none
Change-Id: I167215352119ec11dfd96eb1f33abc1e2111dead
Signed-off-by: tim <tim2.lin@ite.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/1488273
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: Tim2 Lin <tim2.lin@ite.corp-partner.google.com>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
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When tcpc detect type-c plug in (cc lines voltage change),
it will interrupt fw to wake pd task, so task can react
immediately.
BRANCH=None
BUG=None
TEST=GRL USBPD test
Change-Id: I194b2fcad1d0c62dde2d3296753abd47af8feea6
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/1333207
Reviewed-by: Jett Rink <jettrink@chromium.org>
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According USB-PD spec ch.6.7.1, if transmitter sends
the repetitive message id packet, receiver does not respond
subsequent message(except softreset).
BRANCH=None
BUG=None
TEST=GRL USB-PD test
Change-Id: Ideea31cdf2e2d24dc70ac66f5cb830b4cb4b7d46
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/1309564
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Reviewed-by: Jett Rink <jettrink@chromium.org>
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The alert line for TCPC will stay asserted as long as there are RX
messages for the TCPM (i.e. EC) to pull from the TCPC. We should clear
all of the RX messages we know about during a single alert handling
session.
This CL can stand on its own, but it is a part of a CL stack that will
tighten the critical section of time between received messages from the
TCPC and sending follow up message out through the TCPC.
See go/usb-pd-slow-response-time for more details.
BRANCH=none
BUG=b:112088135,b:112344286,b:111909282,b:112848644,b:113124761
BUG=b:113057273,b:112825261
TEST=Reduces reset issue in most cases for phaser, bobba. Does not seem to
adversely affect state machine negotiation. Full CL stack consistently
sends a REQUEST at 18ms after a SRC_CAP GoodCRC, which is well below the
24 ms threshold we need to be under for USB PD spec compliance.
Also testing pd_suspend scenario manually and EC was responsive after
port 1 suspend because of "bad behavior"
Change-Id: I1654b46400e9881f2927a5f6d6ace589edd182de
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1185727
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Break the ec chip code up with the more granular
CONFIG_HOSTCMD_(X86|LPC|ESPI) options.
BRANCH=none
BUG=chromium:818804
TEST=Full stack builds and works on yorp (espi) and grunt (lpc)
Change-Id: Ie272787b2425175fe36b06fcdeeee90ec5ccbe95
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1067502
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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When building the `tests` target for a specific board that uses the
ite EC chip, it will fail to find the lpc_kbc_obe_interrupt function.
Adding #define around code similar to npcx set up.
This is needed because the unibuild system uses the tests target when
compiling chromeos-ec.
BRANCH=none
BUG=b:77274422
TEST=Can now successfully `make BOARD=bip tests`
Change-Id: I971aebe1667eb90e8ccccbe6047c5aa959c76c4b
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/986634
Reviewed-by: Scott Collyer <scollyer@chromium.org>
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Add espi control module for it83xx.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=1. it8390+Intel SKL-Y RVP3 and boot to shell.
2. console command "kbpress 1 4" to test keyboard data.
(board code for espi module test on CL:392587)
Change-Id: I1b32bd16f7e01abf07b9c9a68ebef2399cc9828d
Reviewed-on: https://chromium-review.googlesource.com/394471
Commit-Ready: Dino Li <Dino.Li@ite.com.tw>
Tested-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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We don't need to loop and waiting ADC's data valid flag
after the change was made.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=1. We build a EC binary for PD EVB (declared two ADC channels
for VBUS measurement of PD task and priority is highest)
2. Use console command "adc" continually to read ADC channels
and check if any error.
Change-Id: I1379e0b4c9ef721c29cb053d7d85e1a8ece9471b
Reviewed-on: https://chromium-review.googlesource.com/421307
Commit-Ready: Dino Li <Dino.Li@ite.com.tw>
Tested-by: Dino Li <Dino.Li@ite.com.tw>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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Add USBPD module for it8320 emulation board
BRANCH=none
BUG=none
TEST=manual
plug zinger adapter, connect uart console and type commands:
pd 1 dev [20|12|5]
pd 1 charger
pd 1 swap power
and check PD states
Change-Id: I9ca1822deeb4b4dce1279a09490ed4175890cf3a
Signed-off-by: Leon-Lee <leon.lee@ite.com.tw>
Signed-off-by: Dino Li <dino.li@ite.com.tw>
Reviewed-on: https://chromium-review.googlesource.com/326230
Reviewed-by: Shawn N <shawnn@chromium.org>
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[board]
1. Add i2c channel d/e/f setting.
2. Add i2c channel d/e/f pin definition.
[chip]
3. change i2c port number.
4. Add i2c channel d/e/f function.
5. Add i2c channel d/e/f interrupt.
6. Add i2c channel d/e/f registers.
Signed-off-by: Eli Hsu <eli.hsu@ite.com.tw>
BRANCH=none
BUG=none
TEST=Test by console command "i2cscan","i2cxfer" and "battery"
Change-Id: I928f333ec129924795c3b594ad6a2bfdd0b3d220
Reviewed-on: https://chromium-review.googlesource.com/336560
Commit-Ready: Eli Hsu <eli.hsu@ite.com.tw>
Tested-by: Eli Hsu <eli.hsu@ite.com.tw>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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1. Always use wake-up control interrupt for keyboard KSI. This can also
wake-up EC from deep doze / sleep mode.
2. In keyboard ISR, we just clear interrupt status to prevent keyboard
interrupt can't be re-enabled.
(for example, a KSI interrupt wakes up keyboard scan task,
but keyboard_raw_read_rows() got 0.)
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=keyboard function is normally.
Change-Id: If8c292189c6133b179a63dedcb7a18abbc091312
Reviewed-on: https://chromium-review.googlesource.com/333865
Commit-Ready: Dino Li <dino.li@ite.com.tw>
Tested-by: Dino Li <dino.li@ite.com.tw>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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We have a limitation for EC interrupt vector registers.
System may read incorrect interrupt number in ISR so we need to add
a workaround to prevent it.
The following is a example that got incorrect interrupt number:
1. REG IVCTx = 0x10. (no interrupt pending)
2. EC INT6 interrupt occurs (IVCTx = 0x16) and jump to ISR.
3. Read interrupt vector register to determine interrupt number.
4. Higher priority interrupt of same interrupt group occurs
(for example: INT134, IVCTx = 0x96) while the system is reading the
interrupt vector register for EC INT6, we may end up with an incorrect
interrupt number between 0x16 and 0x96.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=1. EC interrupts work normally: WUI (GPIO interrupt), timer, uart,
LPC, I2C, and PECI.
2. Console command 'taskinfo'.
Change-Id: I54e61f417ad506eb3b4cd5d0652f64eed9a28a17
Reviewed-on: https://chromium-review.googlesource.com/322097
Commit-Ready: Dino Li <dino.li@ite.com.tw>
Tested-by: Dino Li <dino.li@ite.com.tw>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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1. i2c interrupts are used.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=1. console command 'i2cscan' found devices correctly.
2. console command 'i2cxfer' and 'battery' OK.
Change-Id: I4d40488d482318128bc8c549f5c8d3c27abe4a04
Reviewed-on: https://chromium-review.googlesource.com/303001
Commit-Ready: Dino Li <dino.li@ite.com.tw>
Tested-by: Dino Li <dino.li@ite.com.tw>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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Add i2c control module for emulation board.
To rename CONFIG_ to CONFIG_IT83XX_ for IT83XX series configuration.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=1. console command "i2cscan" found devices correctly.
2. console command "i2cxfer".
2-a. port2 + battery, i2cxfer r, r16, and rlen OK.
2-b. port1 + slave evb, i2cxfer r, r16, rlen, w, and w16 OK.
Change-Id: I67165f7dcdef538ba6dd03b47f1621a73cc68379
Reviewed-on: https://chromium-review.googlesource.com/263678
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Commit-Queue: Dino Li <dino.li@ite.com.tw>
Tested-by: Dino Li <dino.li@ite.com.tw>
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Add peci control module for emulation board.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=1. console command "pecitemp" get CPU temperature normally.
2. console command "peci" manual test peci commands.
(GetDIB, GetTemp, RdPkgConfig, and WrPkgConfig)
Change-Id: I48b63a391adf04f159adca401acb369a6acc3799
Reviewed-on: https://chromium-review.googlesource.com/265171
Reviewed-by: Alec Berg <alecaberg@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Queue: Dino Li <dino.li@ite.com.tw>
Tested-by: Dino Li <dino.li@ite.com.tw>
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Add pmc(LPC ACPI) control module for emulation board.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=1. 62h/66h port.
1-a. out 66h 80h, out 62h 00h, in 62h 02h
1-b. out 66h 81h, out 62h 01h, out 62h 55h
1-c. out 66h 80h, out 62h 01h, in 62h 55h
1-d. out 66h 80h, out 62h 02h, in 62h aah
2. H2RAM LPC I/O cycle 900h ~ 9FFh = DLM 0x8D900 ~ 0x8D9FF
and host read only.
3. 80h port, console command port80.
4. host command.
4-a. host request (LPC I/O 800h ~ 807h)
03 FD 00 00, 00 00 00 00
out 204h DAh, in 200h 00h
host response (LPC I/O 800h ~ 80Bh)
03 F7 00 00, 04 00 00 00, 02 00 00 00
4-b. host request
03 EE 01 00, 00 00 04 00, 01 02 03 04
out 204h DAh, in 200h 00h
host response
03 E5 00 00, 04 00 00 00, 05 05 05 05
Change-Id: I5c3bac66306dfba380548a74a64536ea606ddd3e
Reviewed-on: https://chromium-review.googlesource.com/269271
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Dino Li <dino.li@ite.com.tw>
Commit-Queue: Dino Li <dino.li@ite.com.tw>
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1. DLM 16KB.
2. Add KBC/KMSC module for emulation board.
Signed-off-by: Dino Li <dino.li@ite.com.tw>
BRANCH=none
BUG=none
TEST=EVB + x86 MB can boot into DOS and keyboard works.
Change-Id: Ia5cc2d4f1733ce07879d410b0447b2d48e50cd95
Reviewed-on: https://chromium-review.googlesource.com/259923
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Dino Li <dino.li@ite.com.tw>
Commit-Queue: Dino Li <dino.li@ite.com.tw>
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