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* it83xx: IT8320 DX version compatibilityDino Li2018-07-111-42/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [espi]: The supported maximum frequency of slave is adjustable and we set it at 66MHz at initialization (the same as Bx version). [gpio]: All GPIOs support interrupt on rising, falling, and either edge. More GPIOs support 1.8v input. [irq]: Enable newly added interrupts. [registers]: Remove unused declaration. [system]: Watchdog reset supports resetting the full EC domain function (include write protect setting). BUG=none BRANCH=none TEST=[espi]: Ensure the eSPI frequency is able to work at 50 MHz on small core CPU. [gpio]: The settings of input voltage 1.8v selection and both edge interrupt registers are matched to the declarations of GPIO signal in gpio.inc. [system]: The console command "reboot hard" is able to unprotected the flash. (testing failed) Change-Id: I053d8a59a9e90d28e2f2c9b79675ea84425f4959 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/1113166 Reviewed-by: Jett Rink <jettrink@chromium.org>
* it83xx: gpio: set input voltage 1.8v by pinDino Li2018-06-211-0/+1
| | | | | | | | | | | | | | | At the original implementation, we would miss 1.8V configuration if the param 'mask' includes two or more bits. So we fix it. BRANCH=none BUG=none TEST=on bip, the settings of input voltage 1.8v selection register and the declarations of GPIO signal in gpio.inc are matched. Change-Id: Ife199a3150d29714ddcda2aa15b7a64ed9d130c9 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/1107677 Reviewed-by: Jett Rink <jettrink@chromium.org>
* it83xx: gpio: disable default pull-down of USB controllerDino Li2018-06-211-1/+6
| | | | | | | | | | | | | | | | | | At default, there is a 15K pull-down resistor on both D-/D+ pins(GPH5/GPH6). We disable these two pull-down resistors so these two pins will work properly in GPIO mode. BRANCH=none BUG=b:110237505 TEST=on EVB, add a 100K pull-up resistor on GPH5 and measuring the voltage is around 3.3V if this pin is configured as input. Change-Id: I5fe3599eff3ea458cd964c95386f922cf2d3bcee Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/1105689 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
* it83xx: espi: enable eSPI interruptDino Li2018-06-061-0/+7
| | | | | | | | | | | | | | | This patch reconfigure virtual wire outputs for each eSPI boot flow. BUG=b:80250980 BRANCH=none TEST=boot to kernel on bip. Change-Id: Ia36cf3e582982f8d7c2fd7179e56909f0f80efd8 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/1078827 Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* it83xx: espi: workaround for changing PLLDino Li2017-12-121-0/+2
| | | | | | | | | | | | | | | We need to change PLL settings if host apply eSPI operating frequency higher than 50MHz, because FND clock is required to be higher than half of operating frequency. BRANCH=none BUG=b:70537592 TEST=Change PLL succeed with chip select is low. Change-Id: Ieba62f33ed024aed7a8e7f4cc48b1398ed781170 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/817717 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* it83xx: adc: add support ADC13-16Dino Li2017-12-121-0/+18
| | | | | | | | | | | | | IT8320 can support extra four ADC channels (ADC13-16). BRANCH=none BUG=none TEST=Run console command 'adc' and check the results. Change-Id: Ia9a259f54fa28d43dc0050c6e20885c0b3914f9c Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/808125 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* it83xx: add espi moduleDino Li2017-11-141-0/+70
| | | | | | | | | | | | | | | | | | Add espi control module for it83xx. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=1. it8390+Intel SKL-Y RVP3 and boot to shell. 2. console command "kbpress 1 4" to test keyboard data. (board code for espi module test on CL:392587) Change-Id: I1b32bd16f7e01abf07b9c9a68ebef2399cc9828d Reviewed-on: https://chromium-review.googlesource.com/394471 Commit-Ready: Dino Li <Dino.Li@ite.com.tw> Tested-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* it83xx: i2c: remove instructions that aren't necessaryDino Li2017-09-261-29/+0
| | | | | | | | | | | | | | | | | | | | | | - To i2c channel(d/e/f), we remove instructions that aren't necessary. - Changes of i2c_reset(): Before the change, we try to send a START/STOP bit if we get a reset. But i2c_unwedge() already done it, so we just need reset i2c module in i2c_reset(). - Add enhanced_i2c_start() to channel(d/e/f) for each transaction start: We prepare transaction start by calling i2c_reset(), but this doesn't match the definition of i2c_reset(), so we correct it. BRANCH=none BUG=none TEST=1. console commands: "i2cscan", "charger" and "battery". 2. sensors, battery, charger and mux work on reef_it8320. Change-Id: I4e3595479e04a5994a5b19409cfc4e9a46f63d4f Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/674467 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* tcpm: it83xx: Use pd common code macro to analyze message headerDino Li2017-06-291-5/+3
| | | | | | | | | | | | | Use existed macro instead of creating new one. BRANCH=none BUG=none TEST=plug USB-C power adapter and USB-C to hdmi adapter, both work. Change-Id: I133142232ac6abfa7f285c289eb03c4d65e84d5f Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/554655 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* tcpm: it83xx: reload cc parameter setting during initializationDino Li2017-05-251-0/+1
| | | | | | | | | | | | | | | | The trimmed value of CC parameter setting registers (port0: ff3760h ~ ff3763h, port1: ff3860h ~ ff3863h) will be reset to default after a soft reset (system_reset()). BRANCH=none BUG=none TEST=Console command 'reboot' and checking if the value of cc parameter setting registers are correct (trimmed). Change-Id: Ibf9c72e8aeef36701d72bcb64529735295295cdf Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/513744 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* tcpm: it83xx: added chip infoDino Li2017-05-011-0/+2
| | | | | | | | | | | | | | | We can get the correct chip info after the change was made. BRANCH=none BUG=none TEST=console message: [0.013915 TCPC p1 VID:0x48d PID:0x8320 DID:0x1 FWV:0xec] [0.018054 TCPC p0 VID:0x48d PID:0x8320 DID:0x1 FWV:0xec] Change-Id: I4eb94967acb351559e745ed1c4e34a4c58f41e14 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/487767 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* pd: Store PD active state in battery-backed memoryShawn Nematbakhsh2017-02-251-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | Our previous idea to cut Rd for many reset cases cannot work if cr50 consistently resets the EC by asserting the reset pin shortly after power-on. Therefore, make a decision based upon whether battery-backed memory indicates we previously negotiated a PD power contract as a sink. If we previously did not negotiate a contract, or if power was removed from the device (causing battery-backed memory to wipe) then we can assume that we don't have an active power contract. BUG=chrome-os-partner:62952 BRANCH=reef TEST=On reef, run "cutoff" on the console, reattach AC, and verify device successfully wakes. Also verify Rp is dropped on console 'reboot' and F3 + power from RW. Change-Id: Ie300b9589cac6be7a69b77678bea6b1b6b25578c Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/443356 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* it83xx: adc: interrupt is usedDino Li2017-01-101-0/+3
| | | | | | | | | | | | | | | | | | | | We don't need to loop and waiting ADC's data valid flag after the change was made. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=1. We build a EC binary for PD EVB (declared two ADC channels for VBUS measurement of PD task and priority is highest) 2. Use console command "adc" continually to read ADC channels and check if any error. Change-Id: I1379e0b4c9ef721c29cb053d7d85e1a8ece9471b Reviewed-on: https://chromium-review.googlesource.com/421307 Commit-Ready: Dino Li <Dino.Li@ite.com.tw> Tested-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* it83xx: EC sleep mode for system hibernateDino Li2016-09-211-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The typical power consumption in sleep mode is 65uA. IT83xx uses deep doze mode for low power idle task. The typical power consumption in this state is 280uA (depends on EC tasks, it should be more) and the wake up time is in microsecond. We are using deep doze mode for low power idle task instead of sleep mode is because the wake up time will be 6ms more. While in system hibernate (EC sleep mode), EC won't wake up frequently so we can keep the power consumption at 65uA. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=- hibernate 0 [1|999999] - hibernate [1|5|10|600] - hibernate then press power button. - hibernate then lid open. Change-Id: I94884c010264f01ede4950c6bb1b0a444d7b1e6d Reviewed-on: https://chromium-review.googlesource.com/383332 Commit-Ready: Dino Li <dino0303@gmail.com> Tested-by: Dino Li <dino0303@gmail.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* it83xx: Support different PLL frequencies setting (24/48/96 MHz)Dino Li2016-06-141-0/+2
| | | | | | | | | | | | | | | | | | | | | | | Default setting is at 48MHz. For PLL frequency at 24MHz: 1. USB module can't work, it requires 48MHz to work. 2. SSPI clock frequency is divide by two. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=1. uart, i2c, timer, and pd modules are function normally at different PLL frequency settings. 2. use 'flashrom' utility to flash EC binary with different PLL settings. Change-Id: Iabce4726baff493a6136136af18732b58df45d7f Reviewed-on: https://chromium-review.googlesource.com/347551 Commit-Ready: Dino Li <Dino.Li@ite.com.tw> Tested-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* it83xx: Add GPIO group K and LDino Li2016-05-241-2/+4
| | | | | | | | | | | | | | | | | | | The 144-pins package IC(IT8320) supports these two GPIO groups. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=1. Declare GPIO groups K/L in gpio.inc and using console commands 'gpioget'/'gpioset' to read/set GPIOs. 2. Choose four GPIO pins(GPIOK.0/1 and GPIOL.0/1) and test interrupt functionally. Change-Id: Ia618c314eeca1d061ffe172da762865f5df9b5c6 Reviewed-on: https://chromium-review.googlesource.com/345776 Commit-Ready: Dino Li <Dino.Li@ite.com.tw> Tested-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-by: Randall Spangler <rspangler@google.com>
* it83xx: Complete EC interrupt liststabilize-8337.BDino Li2016-05-161-10/+61
| | | | | | | | | | | | | | | | | | There are more EC interrupts available. Also, update interrupts that should be reserved. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=Use 'task_enable_irq()' to enable new-added interrupts and corresponding bit of interrupt enable register are set properly. Change-Id: If1aecec7e208782b4580e33efb968095f30794fe Reviewed-on: https://chromium-review.googlesource.com/344822 Commit-Ready: Dino Li <Dino.Li@ite.com.tw> Tested-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* chip: it83xx: add USBPD moduleDino Li2016-04-181-1/+83
| | | | | | | | | | | | | | | | | | | Add USBPD module for it8320 emulation board BRANCH=none BUG=none TEST=manual plug zinger adapter, connect uart console and type commands: pd 1 dev [20|12|5] pd 1 charger pd 1 swap power and check PD states Change-Id: I9ca1822deeb4b4dce1279a09490ed4175890cf3a Signed-off-by: Leon-Lee <leon.lee@ite.com.tw> Signed-off-by: Dino Li <dino.li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/326230 Reviewed-by: Shawn N <shawnn@chromium.org>
* chip: it83xx: Add i2c channel d/e/f functionEli Hsu2016-04-141-9/+83
| | | | | | | | | | | | | | | | | | | | | | | [board] 1. Add i2c channel d/e/f setting. 2. Add i2c channel d/e/f pin definition. [chip] 3. change i2c port number. 4. Add i2c channel d/e/f function. 5. Add i2c channel d/e/f interrupt. 6. Add i2c channel d/e/f registers. Signed-off-by: Eli Hsu <eli.hsu@ite.com.tw> BRANCH=none BUG=none TEST=Test by console command "i2cscan","i2cxfer" and "battery" Change-Id: I928f333ec129924795c3b594ad6a2bfdd0b3d220 Reviewed-on: https://chromium-review.googlesource.com/336560 Commit-Ready: Eli Hsu <eli.hsu@ite.com.tw> Tested-by: Eli Hsu <eli.hsu@ite.com.tw> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* chip: it83xx: it8320 compatibilityDino Li2016-02-181-0/+1
| | | | | | | | | | | | | | | | | | To ensure it8320's compatibility on the LPC platform, we need to disable SPI slave interface (default enabled) so that LPC module will function normally. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=LPC module of it8320 works normally. Change-Id: I259651b32f41ebae498e13bf07ebb68e5e520058 Reviewed-on: https://chromium-review.googlesource.com/328142 Commit-Ready: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* chip: it83xx: fix EC interrupt vector registers issueDino Li2016-01-281-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | We have a limitation for EC interrupt vector registers. System may read incorrect interrupt number in ISR so we need to add a workaround to prevent it. The following is a example that got incorrect interrupt number: 1. REG IVCTx = 0x10. (no interrupt pending) 2. EC INT6 interrupt occurs (IVCTx = 0x16) and jump to ISR. 3. Read interrupt vector register to determine interrupt number. 4. Higher priority interrupt of same interrupt group occurs (for example: INT134, IVCTx = 0x96) while the system is reading the interrupt vector register for EC INT6, we may end up with an incorrect interrupt number between 0x16 and 0x96. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=1. EC interrupts work normally: WUI (GPIO interrupt), timer, uart, LPC, I2C, and PECI. 2. Console command 'taskinfo'. Change-Id: I54e61f417ad506eb3b4cd5d0652f64eed9a28a17 Reviewed-on: https://chromium-review.googlesource.com/322097 Commit-Ready: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* it8380dev: Implement GPIO mode for KBS pins and fix gpio_set_level()Dino Li2015-12-141-0/+9
| | | | | | | | | | | | | | | | | | 1. KSO[0-15] and KSI[0-7] can be used as GPIO input if they are not set for keyboard scan function. 2. Critical section for gpio_set_level(). Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=console commands: gpioset, gpioget, and version. Change-Id: I8edae122525e6dcebaa3489116642d8e48520569 Reviewed-on: https://chromium-review.googlesource.com/318112 Commit-Ready: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* it8380dev: improve power consumptionDino Li2015-11-171-0/+8
| | | | | | | | | | | | | | | | In doze mode, these improvements help reduce EC power consumption. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=Power consumption has reduced. Change-Id: I8b0fe3301e408134284b4ac5778656ba9b92b0f1 Reviewed-on: https://chromium-review.googlesource.com/312632 Commit-Ready: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* it8380dev: modify hwtimer and LPC wake upDino Li2015-11-051-5/+1
| | | | | | | | | | | | | | | | | | | | | | | | | 1. In combinational mode and clock source is 8MHz, if timer 3 counter register always equals to 7, then timer 4 will be a 32-bit MHz free-running counter. 2. Fix TIMER_32P768K_CNT_TO_US(), each count should be 30.5175 us, not 32.768us. 3. Fix TIMER_CNT_8M_32P768K(). 4. Make sure LPC wake up interrupt is enabled before entering doze / deep doze mode. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=1. Console commands: 'gettime', 'timerinfo', 'waitms', and 'forcetime'. 2. Enabled Hook debug, no warning message received (48hrs). 3. Tested ectool command 'version' x 2000. Change-Id: I796d985361d3c18bc5813c58705b41923e28c5b1 Reviewed-on: https://chromium-review.googlesource.com/310039 Commit-Ready: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* it8380dev: fix irq, jtag and systemDino Li2015-11-011-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | [irq] 1. The chip_init_irqs() function clears all IERx and EXT_IERx registers. [jtag] 2. Enable debug mode through SMBus. [system] 3. remove console_force_enabled functions. 4. implement __no_hibernate, scratchpad and nvcontext functions. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=chrome-os-partner:23575 TEST=1. IERx and EXT_IERx registers are all cleared after chip_init_irqs(). 2. console command "scratchpad" and "hibernate". 3. bram bank0 index 0x10 ~ 0x1F (16 bytes) for system_get_vbnvcontext() and system_set_vbnvcontext functions. Change-Id: If044d50c69ae80b013ab646a3a6931cec7560ec4 Reviewed-on: https://chromium-review.googlesource.com/309390 Commit-Ready: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* it8380dev: fix clock moduleDino Li2015-10-251-0/+6
| | | | | | | | | | | | | | | | | | | | 1. Implement deep doze mode for CONFIG_LOW_POWER_IDLE. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=test the following items in deep doze mode. 1. WUI interrupts wake-up OK. (For example, power button, lid, uart rx, keyboard ksi, and so on) 2. LPC access interrupt wake-up OK. 3. Enabled Hook debug, no warning message received (48hrs). Change-Id: I8702a112632cb6c1c0fa75d682badf272130a7d4 Reviewed-on: https://chromium-review.googlesource.com/307060 Commit-Ready: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* it8380dev: fix i2c moduleDino Li2015-10-051-0/+3
| | | | | | | | | | | | | | | | | 1. i2c interrupts are used. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=1. console command 'i2cscan' found devices correctly. 2. console command 'i2cxfer' and 'battery' OK. Change-Id: I4d40488d482318128bc8c549f5c8d3c27abe4a04 Reviewed-on: https://chromium-review.googlesource.com/303001 Commit-Ready: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* it8380dev: fix hw timer and related function.Dino Li2015-10-011-8/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [chip config] 1. No hardware specific udelay(). 2. Enable watchdog. [watchdog] 3. Watchdog period is "CONFIG_WATCHDOG_PERIOD_MS" of config.h. 4. Watchdog auxiliary timer period is "CONFIG_AUX_TIMER_PERIOD_MS". [task and irq] 5. Write 1 to clear interrupt pending status, no |. 6. A global variable for store interrupt number of software interrupt. [uart] 7. Always reset UART module before config it. [hwtimer] 8. Use more external timers for HW timer module. [task] 9. Fix task profiling. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=[watchdog] 1. console "waitms 1100", only pre-watchdog warning message. 2. console "waitms 1600", warning message and watchdog reset. [hwtimer] 3. console commands "gettime", "timerinfo", and "forcetime". 4. enable hook debug and there is no delayed by more than 10% warning message over 48 hours. 5. There is no watchdog reset too. [task] 6. console 'taskinfo' Task Ready Name Events Time (s) StkUsed 0 R << idle >> 00000000 32.927724 308/512 1 HOOKS 00000000 0.034267 372/768 2 R CONSOLE 00000000 0.116763 468/768 3 HOSTCMD 00000000 0.000641 372/512 4 KEYPROTO 00000000 0.000042 212/512 5 KEYSCAN 00000000 0.000908 356/512 IRQ counts by type: 38 2932 155 1 158 261 160 67 Service calls: 87 Total exceptions: 3348 Task switches: 167 Task switching started: 0.001999 s Time in tasks: 33.282819 s Time in exceptions: 0.164717 s Change-Id: I234085cec231cd855d2a5e639ea1b0966c61d796 Reviewed-on: https://chromium-review.googlesource.com/296939 Commit-Ready: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* it8380dev: fix idle task and chip idDino Li2015-09-181-1/+27
| | | | | | | | | | | | | | | | | | | | | 1. Fix system_get_chip_name() and system_get_chip_revision(). 2. Fix EC doze mode. 3. Enable LPC cycle wake-up EC from doze / deep doze function. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=1. console "version". Chip: ite it8390 cx 2. EC doze mode is normally. 3. ectool "version" command x 2000. Change-Id: I167dbfb965e557eb86ed83f45a945e4315f5fa9f Reviewed-on: https://chromium-review.googlesource.com/299110 Commit-Ready: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* it8380dev: fix lpc moduleDino Li2015-09-161-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | 1. add lpc_keyboard_clear_buffer() function. 2. Enable P80L function, that LPC I/O port 80h data can be mapped to BRAM bank1 (offset 0x80 ~ 0xBF). Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=1. The lpc_keyboard_clear_buffer() function can clear OBF. 2. 80h port, console command port80. 3. 62h/66h port. 3-a. out 66h 80h, out 62h 00h, in 62h 02h 3-b. out 66h 81h, out 62h 01h, out 62h 55h 3-c. out 66h 80h, out 62h 01h, in 62h 55h 3-d. out 66h 80h, out 62h 02h, in 62h aah 4. Host command "version". Change-Id: Id2b5a5813cbe8edfc4ecc7b153874b819d460f43 Reviewed-on: https://chromium-review.googlesource.com/298421 Commit-Ready: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* it8380dev: add flash module and fix system jumpDino Li2015-07-081-5/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. Add flash control module for emulation board. 2. Fix system jump for Andes core. 3. Change the physical size of the flash on the chip to 256KB. note: 1. Only IT839x series supports flash write protect by registers. 2. Static DMA method of flash code only for IT839x series and IT838x Dx. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=1. console command flashwp and flashinfo 1-a. flashwp enable 1-b. WP asserted and reboot 1-c. flashinfo RO protected now 1-d. WP deasserted and reboot 1-e. No protected 1-f. flashwp disable 1-g. WP asserted and reboot 1-h. No protected 2. console sysjump and sysinfo 2-a. sysjump rw 2-b. jumping to image RW 2-c. sysinfo, Copy : RW, Jumped : yes 2-d. sysjump ro 2-e. jumping to image RO 2-f. sysinfo, Copy : RO, Jumped : yes 3. RO/RW firmware image test 3-a. sysjump rw 3-b. use console command "eflash" to erase RO region, erase OK and system still work. 3-c. reflash firmware 3-d. sysjump rw, sysjump ro 3-e. use console command "eflash" to erase RW region, erase OK and system still work. Change-Id: I7666a095e73026a02fb812e5143bc5172ab713e8 Reviewed-on: https://chromium-review.googlesource.com/271390 Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw>
* it8380dev: add pin 3.3v/1.8v selectionDino Li2015-06-301-0/+6
| | | | | | | | | | | | | | | | | | | add GPIO_SEL_1P8V flag for 1.8v/3.3v selection. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=1. To configure 1.8V/3.3V pin to 1.8V, set GPIO_SEL_1P8V flag in gpio.inc. 2. The corresponding bit will be set as default value if the pin is not listed in gpio.inc. Change-Id: Ica02aabe40b83fcb4d33bd28d717a0633bdef5f3 Reviewed-on: https://chromium-review.googlesource.com/281842 Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw>
* it8380dev: add i2c control moduleDino Li2015-06-301-1/+58
| | | | | | | | | | | | | | | | | | | | Add i2c control module for emulation board. To rename CONFIG_ to CONFIG_IT83XX_ for IT83XX series configuration. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=1. console command "i2cscan" found devices correctly. 2. console command "i2cxfer". 2-a. port2 + battery, i2cxfer r, r16, and rlen OK. 2-b. port1 + slave evb, i2cxfer r, r16, rlen, w, and w16 OK. Change-Id: I67165f7dcdef538ba6dd03b47f1621a73cc68379 Reviewed-on: https://chromium-review.googlesource.com/263678 Reviewed-by: Alec Berg <alecaberg@chromium.org> Commit-Queue: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw>
* it8380dev: add fan control moduleDino Li2015-06-251-13/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. pwm, add frequency select function for pwm channels. 2. timer, add external timer 3~8 apis. 3. add fan control module for emulation board. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=console command "faninfo, fanset, fanduty, and fanauto" fanset 3333 Setting fan 0 rpm target to 3333 faninfo Actual: 3390 rpm Target: 3333 rpm Duty: 35% Status: 1 (changing) Mode: rpm Auto: no Enable: yes faninfo Actual: 3301 rpm Target: 3333 rpm Duty: 34% Status: 2 (locked) Mode: rpm Auto: no Enable: yes fanduty 80 Setting fan 0 duty cycle to 80% faninfo Actual: 5952 rpm Target: 3333 rpm Duty: 80% Status: 2 (locked) Mode: duty Auto: no Enable: yes faninfo Actual: 5971 rpm Target: 3333 rpm Duty: 80% Status: 2 (locked) Mode: duty Auto: no Enable: yes fanauto faninfo Actual: 3330 rpm Target: 3333 rpm Duty: 36% Status: 2 (locked) Mode: rpm Auto: yes Enable: yes fanset 8000 Setting fan 0 rpm target to 8000 faninfo Actual: 6793 rpm Target: 8000 rpm Duty: 100% Status: 3 (frustrated) Mode: rpm Auto: no Enable: yes fanset 3456 Setting fan 0 rpm target to 3456 faninfo Actual: 5053 rpm Target: 3456 rpm Duty: 56% Status: 1 (changing) Mode: rpm Auto: no Enable: yes faninfo Actual: 3440 rpm Target: 3456 rpm Duty: 34% Status: 2 (locked) Mode: rpm Auto: no Enable: yes /* force stop the fan */ [87.035136 Fan 0 stalled!] [87.035520 event set 0x00000400] [88.035712 Fan 0 stalled!] [89.036288 Fan 0 stalled!] [90.036864 Fan 0 stalled!] [91.037440 Fan 0 stalled!] [92.038016 Fan 0 stalled!] [93.038592 Fan 0 stalled!] [94.039168 Fan 0 stalled!] /* release */ faninfo Actual: 3427 rpm Target: 3456 rpm Duty: 35% Status: 2 (locked) Mode: rpm Auto: no Enable: yes Change-Id: Icbe1917902d033a8be42b8d834ffc6045d08b985 Reviewed-on: https://chromium-review.googlesource.com/266625 Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw>
* it8380dev: add peci control modulestabilize-7204.BDino Li2015-06-241-2/+38
| | | | | | | | | | | | | | | | | | | Add peci control module for emulation board. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=1. console command "pecitemp" get CPU temperature normally. 2. console command "peci" manual test peci commands. (GetDIB, GetTemp, RdPkgConfig, and WrPkgConfig) Change-Id: I48b63a391adf04f159adca401acb369a6acc3799 Reviewed-on: https://chromium-review.googlesource.com/265171 Reviewed-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw>
* it8380dev: add sspi control moduleDino Li2015-06-231-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | Add sspi control module for emulation board. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=EVB + Winbond W25Q80 SPI ROM To define CONFIG_SPI_FLASH, CONFIG_SPI_FLASH_SIZE, and CONFIG_SPI_FLASH_W25X40 console "spi_flashinfo" can get SPI information > spi_flashinfo Manufacturer ID: ef Device ID: 40 14 Unique ID: c8 60 84 a1 1f 6a 7f 2f Capacity: 1024 MB Change-Id: I6c4d4d977536484d47a2207ed80dd0ea08a7c8fd Reviewed-on: https://chromium-review.googlesource.com/267403 Reviewed-by: Alec Berg <alecaberg@chromium.org> Commit-Queue: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw>
* it8380dev: add pmc control moduleDino Li2015-06-171-1/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add pmc(LPC ACPI) control module for emulation board. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=1. 62h/66h port. 1-a. out 66h 80h, out 62h 00h, in 62h 02h 1-b. out 66h 81h, out 62h 01h, out 62h 55h 1-c. out 66h 80h, out 62h 01h, in 62h 55h 1-d. out 66h 80h, out 62h 02h, in 62h aah 2. H2RAM LPC I/O cycle 900h ~ 9FFh = DLM 0x8D900 ~ 0x8D9FF and host read only. 3. 80h port, console command port80. 4. host command. 4-a. host request (LPC I/O 800h ~ 807h) 03 FD 00 00, 00 00 00 00 out 204h DAh, in 200h 00h host response (LPC I/O 800h ~ 80Bh) 03 F7 00 00, 04 00 00 00, 02 00 00 00 4-b. host request 03 EE 01 00, 00 00 04 00, 01 02 03 04 out 204h DAh, in 200h 00h host response 03 E5 00 00, 04 00 00 00, 05 05 05 05 Change-Id: I5c3bac66306dfba380548a74a64536ea606ddd3e Reviewed-on: https://chromium-review.googlesource.com/269271 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Tested-by: Dino Li <dino.li@ite.com.tw> Commit-Queue: Dino Li <dino.li@ite.com.tw>
* it8380dev: add KBC/KMSC moduleDino Li2015-03-221-31/+147
| | | | | | | | | | | | | | | | | 1. DLM 16KB. 2. Add KBC/KMSC module for emulation board. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=EVB + x86 MB can boot into DOS and keyboard works. Change-Id: Ia5cc2d4f1733ce07879d410b0447b2d48e50cd95 Reviewed-on: https://chromium-review.googlesource.com/259923 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Tested-by: Dino Li <dino.li@ite.com.tw> Commit-Queue: Dino Li <dino.li@ite.com.tw>
* it8380dev: add ec2i control moduleDino Li2014-12-231-2/+14
| | | | | | | | | | | | | | | | | | | Add EC2I control module for emulation board. The EC2I bridge enables the EC to access the host controlled module registers (e.g., host configuration module(PNPCFG) and SWUC) Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=EC2I read: Read a logical device page, the results are correctly. EC2I write: Initialize PNPCFG success. Change-Id: I900450d4a8c49182c438b69b5e738c12dc437fe4 Reviewed-on: https://chromium-review.googlesource.com/230410 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw>
* it8380dev: add adc control moduleDino Li2014-12-191-2/+59
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add adc control module for emulation board. The ADC converts the input voltage signal ranging from 0v to 3v into a 10-bit unsigned integer. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=manual test. 1 - adc channel 1, 3, 5, and 7 to ground. 2 - adc channel 0 and 2 to 1.26v. 3 - adc channel 4 and 6 to 1.72v. 4 - condition, factor_mul = 3000, factor_div = 1024, and shift = 0. 5 - console "adc", result as following. adc_ch0 = 1256 adc_ch1 = 0 adc_ch2 = 1256 adc_ch3 = 0 adc_ch4 = 1722 adc_ch5 = 0 adc_ch6 = 1725 adc_ch7 = 0 Change-Id: I72efd09c9f7dbff25c4f6fd4846c9b1c1e5637ca Reviewed-on: https://chromium-review.googlesource.com/228092 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw>
* it8380dev: add pwm control moduleDino Li2014-10-291-1/+52
| | | | | | | | | | | | | | | | Add pwm control module for emulation board. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=console manual test, pwm channels output correctly. Change-Id: I6eb1a9e4fdcb9279e9d0cbd67f7a92afed21c889 Reviewed-on: https://chromium-review.googlesource.com/223921 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw>
* ite: Added system reset and reset causesAlec Berg2014-01-141-0/+1
| | | | | | | | | | | | | | | Added system reset and reset causes for ITE chip. The only reset causes available on this chip are watchdog reset or power on reset. BRANCH=none BUG=none TEST=Used reboot console command with various args and verified reset cause was recorded correctly on next boot. Change-Id: Ie65f1e8f2b98c1e614b5c1d8bcbe9b3000ed9590 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179539 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* ite: Add initial support for ITE IT8380 chipVincent Palatin2014-01-081-0/+558
Initial support for the ITE IT8380 chip with the following peripherals : - 8250-like UART module. - HW timer (with a 128-us tick period). - GPIO with pins initialization and edge interrupt support. other functions are stubbed. - Clock : basic fixed frequency setup only. It also add the dev board configuration as a test vehicle. Signed-off-by: Alec Berg <alecaberg@chromium.org> Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=chrome-os-partner:23575 TEST=make BOARD=it8380dev on IT8380 dev board, use the EC serial console, use gettime from console. Change-Id: Id4bf37d1beb21d1a4bee404c9a0bc500025fe787 Reviewed-on: https://chromium-review.googlesource.com/175481 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: Alec Berg <alecaberg@chromium.org> Tested-by: Alec Berg <alecaberg@chromium.org>
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