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* ish: Trim down the release branchstabilize-wristpin-14469.59.B-ishstabilize-voshyr-14637.B-ishstabilize-quickfix-14695.187.B-ishstabilize-quickfix-14695.124.B-ishstabilize-quickfix-14526.91.B-ishstabilize-14695.85.B-ishstabilize-14695.107.B-ishstabilize-14682.B-ishstabilize-14633.B-ishstabilize-14616.B-ishstabilize-14589.B-ishstabilize-14588.98.B-ishstabilize-14588.14.B-ishstabilize-14588.123.B-ishstabilize-14536.B-ishstabilize-14532.B-ishstabilize-14528.B-ishstabilize-14526.89.B-ishstabilize-14526.84.B-ishstabilize-14526.73.B-ishstabilize-14526.67.B-ishstabilize-14526.57.B-ishstabilize-14498.B-ishstabilize-14496.B-ishstabilize-14477.B-ishstabilize-14469.9.B-ishstabilize-14469.8.B-ishstabilize-14469.58.B-ishstabilize-14469.41.B-ishstabilize-14442.B-ishstabilize-14438.B-ishstabilize-14411.B-ishstabilize-14396.B-ishstabilize-14395.B-ishstabilize-14388.62.B-ishstabilize-14388.61.B-ishstabilize-14388.52.B-ishstabilize-14385.B-ishstabilize-14345.B-ishstabilize-14336.B-ishstabilize-14333.B-ishrelease-R99-14469.B-ishrelease-R98-14388.B-ishrelease-R102-14695.B-ishrelease-R101-14588.B-ishrelease-R100-14526.B-ishfirmware-cherry-14454.B-ishfirmware-brya-14505.B-ishfirmware-brya-14505.71.B-ishfactory-kukui-14374.B-ishfactory-guybrush-14600.B-ishfactory-cherry-14455.B-ishfactory-brya-14517.B-ishJack Rosenthal2021-11-051-1678/+0
| | | | | | | | | | | | | | | | | | | | | | In the interest of making long-term branch maintenance incur as little technical debt on us as possible, we should not maintain any files on the branch we are not actually using. This has the added effect of making it extremely clear when merging CLs from the main branch when changes have the possibility to affect us. The follow-on CL adds a convenience script to actually pull updates from the main branch and generate a CL for the update. BUG=b:204206272 BRANCH=ish TEST=make BOARD=arcada_ish && make BOARD=drallion_ish Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I17e4694c38219b5a0823e0a3e55a28d1348f4b18 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3262038 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Tom Hughes <tomhughes@chromium.org>
* COIL: chip/it83xx: Rename SPI IRQ configCaveh Jalali2021-08-021-1/+1
| | | | | | | | | | | | | | | This renames the ITE chip specific SPI IRQ config from IT83XX_IRQ_SPI_SLAVE to IT83XX_IRQ_SPI_PERIPHERAL. BRANCH=none BUG=b:181607131 TEST=compare_build.sh matches Change-Id: Ib7a7674e6cf4f0bf81ee47b5f60225f77236f578 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3061913 Commit-Queue: Harry Cutts <hcutts@chromium.org> Reviewed-by: Harry Cutts <hcutts@chromium.org>
* it83xx: disable pre-defined command at defaultDino Li2021-04-081-0/+1
| | | | | | | | | | | | | | | | With this change, no master is able to see the slave device of pre-defined command on port 0. BUG=b:184804044 BRANCH=none TEST=run i2cscan command on icarus, verified that the slave address isn't present on port 0. Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Change-Id: I6df72132d08a3be6ff97fb501eefc4a9fa8d6f08 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2813878 Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* it8xxx2: add support option CONFIG_PRESERVE_LOGSDino Li2021-04-071-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On it8xxx2 chips, assert WRST# to reset itself will clear memory content to default value, this is a HW mechanism. So if CONFIG_PRESERVE_LOGS and CONFIG_IT83XX_HARD_RESET_BY_GPG1 are enabled at the same time, we have to save EC logs into flash before reset. We will restore logs from flash on the next initialization before jumping to main routine. BUG=b:183899510, b:183466169 BRANCH=none TEST=1) __image_size is same as ec.RW.bin size. 2) buildall. 3) manually verify reboot, poweroff, and sysjump from AP console: localhost ~ # ectool uptimeinfo EC uptime: 64.755 seconds AP resets since EC boot: 0 Most recent AP reset causes: EC reset flags at last EC boot: reset-pin | power-on localhost ~ # reboot ... localhost ~ # ectool uptimeinfo EC uptime: 19.334 seconds AP resets since EC boot: 0 Most recent AP reset causes: 71.609: reset: at AP's request EC reset flags at last EC boot: reset-pin | power-on | hard localhost ~ # poweroff ... localhost ~ # ectool uptimeinfo EC uptime: 20.627 seconds AP resets since EC boot: 0 Most recent AP reset causes: 71.609: reset: at AP's request 32.149: reset: at AP's request EC reset flags at last EC boot: reset-pin | power-on | hard localhost ~ # ectool reboot_ec RW localhost ~ # ectool uptimeinfo EC uptime: 37.998 seconds AP resets since EC boot: 0 Most recent AP reset causes: 71.609: reset: at AP's request 32.149: reset: at AP's request EC reset flags at last EC boot: reset-pin | power-on | sysjump | hard localhost ~ # Change-Id: I76b5f172b7728dc5ce9bf3a965cb7b2d638f8fc3 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2794322 Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* it83xx/adc: Enable keeping ADC data bufferDino Li2021-03-171-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | IT83xx's ADC data is 10-bit and saving in two registers (VCHxDATL/bit7-0 and VCHxDATM/bit9-8). The CL enables the function of keeping ADC data buffer to prevent reporting incorrect ADC raw data due to the following race condition: 1) adc data valided: 0 0xf8 (voltage is 3x248/1024=0.72v) 2) ec read VCHxDATM(0x0) 3) next adc conversion done: 0x1 0x08 (voltage is 3x264/1024=0.77v) 4) ec read VCHxDATL(0x8) EC will return incorrect voltage (3x8/1024=0.02v) to caller for above conditions. BUG=b:175044329 BRANCH=none TEST=No thermal shutdown on stress test. Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Change-Id: I64d913a2b5d03ca51afcb31ffda6c6ee915338f6 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2759449 Tested-by: rasheed.hsueh <rasheed.hsueh@lcfc.corp-partner.google.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* chip/it83xx: Fix narrowing type warning when included from C++Tom Hughes2021-03-081-3/+3
| | | | | | | | | | | | | | | | | | chip/it83xx/registers.h:861:63: error: constant expression evaluates to -1 which cannot be narrowed to type 'uint32_t' (aka 'unsigned int') [-Wc++11-narrowing] [GPIO_KSI] = { 0x00F01D08, 0x00F01D09, 0x00F01D26, -1 }, BRANCH=none BUG=b:144959033 TEST=make buildall Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: I029cb79e132ce18158440812b26aa57e770ce423 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2740561 Commit-Queue: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Denis Brockus <dbrockus@chromium.org>
* it83xx/gpg1 reset EC: save panic data to bramDino Li2021-02-231-1/+30
| | | | | | | | | | | | | | | | | This change saves panic data to bram before EC reset is triggered if GPG1 reset mechanism is enabled. Because the reset will also clear RAM contents. With this change, we can restore panic data from bram after panic reboot. BUG=b:173075595 BRANCH=none TEST=crash EC and then run the panicinfo command to check if panic data is saved. Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Change-Id: I08f006c7969bce711695459b9f595ccc2fd6900b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2632123 Reviewed-by: Ting Shen <phoenixshen@chromium.org>
* it83xx: deprecate BRAM_IDX_NVCONTEXTJack Rosenthal2021-02-021-6/+1
| | | | | | | | | | | | | | | Unused, as VBNV storage in EC bbram is gone. This makes inxedexs 0x10 to 0x1F in bbram available for future use. BUG=b:178689388 BRANCH=none TEST=buildall Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I013bc2885f06aa853b1fbdabe98d9e5658811e44 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2668689 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* it83xx/spi: add support emmc boot modeDino Li2020-12-291-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | IT81202 bx version can configure SPI module to work as eMMC boot mode to catch CMD0. Once this mode is enabled, SPI's CS# pin isn't required. HW will drop data until CMD goes low (CMD0 starts with 01b) and saving 128 bytes in RX FIFO. FW need to parse the data of FIFO and handle argument of CMD0 (GO_IDLE_STATE, GO_PRE_IDLE_STATE, and BOOT_INITIATION). Pinmux of eMMC boot mode are as following: GPM2->CLK GPM3->CMD GPM6->DATA0 BUG=b:170795623 BRANCH=none TEST=boot to kernel on Juniper (replace EC with it81202 bx). Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Change-Id: I1dac1848bfd79f4a7dc02e1d90905e0cd6b8af3f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2604802 Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* it8xxx2: enable ILM0Dino Li2020-12-171-0/+4
| | | | | | | | | | | | | | | | | | This change enable ILM0 for it8xxx2 series, so we can pull more code into static cache to save latency of fetching code from flash. BUG=b:171172053 BRANCH=none TEST=Check timestamp of "Inits done" on asurada: Before the change was made, we got the timestamp is: [0.004408 Inits done] With this change, the timestamp is changed to: [0.003843 Inits done] Change-Id: Ie7a241bed2f926fd0034cecaf5d8e8183ca16d2e Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2563056 Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* chip/it83xx: move __RAM_CODE_SECTION_NAMETzung-Bi Shih2020-11-201-1/+0
| | | | | | | | | | | | | | | | Moves __RAM_CODE_SECTION_NAME from registers.h to config_chip.h. Or switch.S cannot see the macro. BRANCH=none BUG=none TEST=1. make BOARD=asurada 2. grep __switch_task build/asurada/RW/ec.RW.smap Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Change-Id: I1ef272c2e2181a88e4f53dc3024330a1a26c0688 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2549342 Reviewed-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-by: Diana Z <dzigterman@chromium.org>
* core/riscv-rv32i: move essential code to ram_code only if supportsTzung-Bi Shih2020-11-191-1/+2
| | | | | | | | | | | | | | | | | | Commit "it83xx: pull more functions into __ram_code section" (https://crrev.com/c/2535899) breaks Asurada SCP. It moves some essential code to .ram_code section but only IT8XXX2 family includes .ram_code in linker script. Moves the context switch code to ram_code only if it supports. BRANCH=none BUG=none TEST=make BOARD=asurada_scp && make BOARD=asurada Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Change-Id: I8602f7ef0103282feeddbfe1757f7cf7fb5512dc Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2546722 Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* it83xx/KB/GPIO: support keyboard GPIO output modeRuibin Chang2020-10-141-7/+19
| | | | | | | | | | | | | | | | | | | | | | | These pins could be used as GPIO input, and they can be configured as GPIO output as well. So we made this patch to support it. BRANCH=none BUG=b:170699805 TEST=On board it8xxx2_evb 1.GPIO only: set/get level properly at GPIO mode. 2.GPIO and alternate mix: KSI input low and KSO GPIO level not change On board reef_it8320 1.keyboard scan function still work fine. Change-Id: I2098812649f2e3ee9a8718d0d75e541ce3f14338 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2182128 Tested-by: Ruibin Chang <Ruibin.Chang@ite.com.tw> Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Ruibin Chang <Ruibin.Chang@ite.com.tw>
* it83xx: enable selecting EC's VCCDino Li2020-10-081-0/+1
| | | | | | | | | | | | | | | | | | | The VCC is the power source of EC's GPM0~6, will connect to 1.8v or 3.3v depended on platform design. This change was made to ensure voltage level setting of GPM0~6 matches the corresponded VCC level. So we can enable internal pull-up no matter VCC is connected to 1.8v or 3.3v BUG=b:168783892 BRANCH=none TEST=- buildall. - The level setting is correct on these boards: asurada, drawcia, and reef_it8320 Change-Id: I4eae368e569987381a0437494262d588436bb011 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2397931 Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* it83xx/flash: the configuration only used by N8 coretim2020-09-301-0/+1
| | | | | | | | | | | | | | | | | We need to set the 56k~60k region to DLM on N8 core only. After copying data into it, we will disable the region and be the ram code section. BUG=none BRANCH=none TEST=use console commands of #flasherase and #flashwrite to erase and write are normal on the board of reef_it8320(N8) it8xxx2_evb(risc-v). Signed-off-by: tim <tim2.lin@ite.corp-partner.google.com> Change-Id: I9e42329d2e9d614640b668a0b75606f45268b83e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2428348 Reviewed-by: Jett Rink <jettrink@chromium.org>
* it83xx/system: Don't disable DBGR in system resetDino Li2020-08-271-0/+2
| | | | | | | | | | | | | | | | | | | | | | | Our current implementation will disable DBGR (debug mode) in system reset, but this will break flashing sequence. So we make a change to ensure flashing won't be broken under the above situation. Note: DBGR is only applied to flashing sequence, a HW reset after flashing will disable DBGR and allow normal system reset. We also enable wait flashing sequence in this CL, so EC can check if there’s a DBGR flag during initialization and proceed afterwards. BUG=b:118584434, b:165515400 BRANCH=none TEST=- The soft reset still works after flashing. - EC can be flashed even if it is in continuous reboot loop. Change-Id: I9cea2c4fef74de7afcffb203e02f79cb18a4c5bf Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1243878 Reviewed-by: Jett Rink <jettrink@chromium.org> Commit-Queue: Jett Rink <jettrink@chromium.org>
* it83xx/spi: enable rx valid length interruptDino Li2020-08-141-0/+6
| | | | | | | | | | | | | | | | | | | | | Enable IT83XX_SPI_RX_VALID_INT which can obtain data length field of host requested. When received data to reach, Rx valid interrupt will be fired then start to parse. Instead of waiting for Rx 256 bytes reach interrupt method, this is effectively saving time to complete once transaction. BUG=b:160662061; b:161509047 BRANCH=none TEST=Boot to kernel with it81202 on asurada. No error on the command of get EC protocol info with 1MHz clock frequency. Change-Id: Ib56e3034d3ee39fa64818b95747eb7e9e5821294 Signed-off-by: tim <tim2.lin@ite.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2076826 Reviewed-by: Ting Shen <phoenixshen@chromium.org> Tested-by: Hung-Te Lin <hungte@chromium.org> Commit-Queue: Hung-Te Lin <hungte@chromium.org>
* it83xx/adc: Enable automatic hardware calibrationDino Li2020-08-141-0/+1
| | | | | | | | | | | | | | We missed it when ADC accuracy initialization, let's fix it. BUG=b:164011390 BRANCH=none TEST=ADC accuracy is in +/- 4LSB. Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Change-Id: Id40adbdc6823fbf3db506681ce4bff6a2f32b843 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2355166 Reviewed-by: Ting Shen <phoenixshen@chromium.org> Tested-by: Parker Lin <parkerlin@google.com>
* chip: support dynamic hibernate_wake_pins configTing Shen2020-08-061-0/+5
| | | | | | | | | | | | | | | | Add CONFIG_HIBERNATE_WAKE_PINS_DYNAMIC to let board config their wake pins at runtime. BUG=b:162814191 TEST=make BRANCH=master Signed-off-by: Ting Shen <phoenixshen@google.com> Change-Id: Iae2072ec7239a0daa84222c23733b90153e732f1 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2340730 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Commit-Queue: Ting Shen <phoenixshen@chromium.org> Tested-by: Ting Shen <phoenixshen@chromium.org>
* ec: change usage of dummySam Hurst2020-08-051-1/+1
| | | | | | | | | | | | | | | | | | Google is working to change its source code to use more inclusive language. To that end, replace the term "dummy" with inclusive alternatives. BUG=b:162781382 BRANCH=None TEST=make -j buildall `grep -ir dummy *` The only results are in "private/nordic_keyboard/sdk8.0.0" which is not our code. Signed-off-by: Sam Hurst <shurst@google.com> Change-Id: I6a42183d998e4db4bb61625f962867fda10722e2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2335737 Reviewed-by: Tom Hughes <tomhughes@chromium.org>
* it83xx: Add support for interrupt and 1.8v selection of GPJ7Dino Li2020-08-041-0/+3
| | | | | | | | | | | | BUG=b:162805450 BRANCH=none TEST=not yet Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Change-Id: Ie1525b8a0f67a4700649163b536d09bef9a9671a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2335518 Reviewed-by: Ting Shen <phoenixshen@chromium.org> Tested-by: Ting Shen <phoenixshen@chromium.org>
* it83xx/spi: Reset SPI module before sysjumpDino Li2020-07-211-0/+1
| | | | | | | | | | | | | | | | | BUG=b:161327069 BRANCH=none TEST=No complaining bad data from SPI continuously after sysjump. NOTE: We might get one bad data message after sysjump (eg: "sysjump rw" command). Because EC isn't ready to receive data but request from AP might be already started. Change-Id: Ibe83c0b54c234022338a30c35b1b0564f7e5f266 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2301323 Tested-by: Eric Yilun Lin <yllin@chromium.org> Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* it83xx/spi: enable Rx byte reach(256 bytes) interrupttim2020-07-101-2/+1
| | | | | | | | | | | | | | | When Rx received data reaches FIFO target count, the status of Rx byte reach interrupt bit is set then start to parse transaction. BUG=b:160662061 BRANCH=none TEST=EC can receive more than 128 bytes(up to 256 bytes) from host. Signed-off-by: tim <tim2.lin@ite.corp-partner.google.com> Change-Id: I3e922265e35f5bc46e794e92adb1bede20f73498 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2284513 Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* chip/it83xx: read GPIO level from data mirror registerRuibin Chang2020-06-021-21/+25
| | | | | | | | | | | | | | | | | | | | | In GPIO output mode, the data register is the level what we set, not the actually measured. The data mirror register shows the real level same as we measured, so we change reading the gpio level to data mirror register. BRANCH=none BUG=none TEST=on it81202 evb, GPIO setting open drain, data high, and internal pullup, manully external pulldown, verify that reads "0" in console "gpioget" Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw> Change-Id: I3afb19daf24d1eda98c503ce7de3527353e88a9e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2224676 Tested-by: Ruibin Chang <Ruibin.Chang@ite.com.tw> Commit-Queue: Ruibin Chang <Ruibin.Chang@ite.com.tw> Reviewed-by: Diana Z <dzigterman@chromium.org>
* it8xxx2: lpc/espi: mapping host I/O cycle to h2ram sectionDino Li2020-04-281-0/+1
| | | | | | | | | | | | | | | | | | On it8xxx2 series, host I/O cycles are mapped to the first block (0x80080000~0x80080fff) at default, and it is adjustable. We should set the correct offset depends on the base address of H2RAM section, so EC will be able to receive/handle commands from host. BUG=b:133460224 BRANCH=none TEST=not yet. just check the register setting is correct (I/O cycles are mapped to 0x80081000~0x80081fff) after EC initialization. Change-Id: Ib9085181917712bf735b83487720f12c8cd7ca31 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2038223 Reviewed-by: Jett Rink <jettrink@chromium.org>
* it83xx/pwm: clear cycle timer1 high byte for using as 8-bitRuibin Chang2020-04-161-0/+1
| | | | | | | | | | | | | | | | | | | | | | The cycle timer1 of chip 8320 later series was enhanced from 8bits to 10bits resolution, and others are still 8bit resolution. Because the cycle timer1 high byte default value is not zero, we clear cycle timer1 high byte at init and use it as 8-bit resolution like others. BUG=none BRANCH=none TEST=on board it8xxx2_evb 1) console check: the register CTR1M value 2) oscilloscope check: the pwm output frequency same as our setting on board level via prescaler c4. Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw> Change-Id: I5b2f249bbf56d3fbded88401779715973434e5d9 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2142850 Commit-Queue: Ruibin Chang <Ruibin.Chang@ite.com.tw> Tested-by: Ruibin Chang <Ruibin.Chang@ite.com.tw> Reviewed-by: Jett Rink <jettrink@chromium.org>
* it83xx/spi: enable auto reset rx fifo functiontim2020-04-021-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | In this change, we enable IT83XX_SPI_AUTO_RESET_RX_FIFO. When CS# deasserted, the rx fifo and fifo count can auto reset in time by the hardware way to avoid the time delay caused. And we removed the spi_chipset_startup and shutdown. we don't need to disable the interrupt of GPIO_SPI0_CS via hook during chipset suspend and enable it during chipset resume. Instead, when the interrupt of GPIO_SPI0_CS occurs, we judge whether the chipset state is enabled and then to disable deep sleep. BUG=none BRANCH=none TEST=boot to kernel with it81202 on elm board. Press the button to shutdown and resume testing 10 times are normal. Signed-off-by: tim <tim2.lin@ite.corp-partner.google.com> Change-Id: I263d63fa5c22ef430d8f807c694317b7496f238f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2100372 Reviewed-by: Jett Rink <jettrink@chromium.org> Commit-Queue: Dino Li <Dino.Li@ite.com.tw>
* it8xxx2: wake up CPU if an interrupt is pending in idle taskDino Li2020-03-241-0/+1
| | | | | | | | | | | BUG=b:142029177 BRANCH=none TEST=In idle task, EC does not get stuck. Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Change-Id: I9f3c0e3b58e68d60b1218338603a5f2a4bc5eb5d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2100055 Reviewed-by: Jett Rink <jettrink@chromium.org>
* chip/it8xxx2: add support IT81302 and IT81202Dino Li2020-03-211-0/+4
| | | | | | | | | | | | | | | | | | | | | | | IT81302 (144-pins package) and IT81202 (128-pins package) chips belong to it8xxx2 family. So we apply the same chip options of it83202bx (except ADC pin order config option) and setup the correct flash size, ram size, and ram base. With this change, we are able to build FW image with IT81202 or IT81302 chip variant. BUG=none BRANCH=none TEST=EC boots and test console commands (version, sysinfo, sysjump, flasherase, flashwrite, and flashread) on IT81202 EVB. Hibernate EC and then press servo board's COLD_RST_L to reset EC. EC reboots. Change-Id: If351d561c61f635ebdb1e4e444e73e061a494c9a Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2072562 Reviewed-by: Jett Rink <jettrink@chromium.org>
* it83xx/adc: add voltage comparator featureRuibin Chang2020-03-111-0/+22
| | | | | | | | | | | | | | | | | | | | Add voltage comparator feature. BUG=b:149094481 BRANCH=none TEST=on board it83xx_evb, 1.set VCMP1 threshold 2.8v: external input 3v, the INT would be triggered and ADC5 read the correctly voltage. 2.set VCMP0 threshold 0.2v: external input 0v, the INT would be triggered and ADC5 read the correctly voltage. Change-Id: I59510b1c6bd38004ff06e0fcbd2a671e895d59e3 Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2062110 Tested-by: Ruibin Chang <Ruibin.Chang@ite.com.tw> Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Ruibin Chang <Ruibin.Chang@ite.com.tw>
* it83xx/dac: add DAC moduletim2020-02-211-1/+7
| | | | | | | | | | | | | | | | | | The DAC module has four channels. We can set output voltage when DAC channel is enabled by this driver. BUG=b:149094279 BRANCH=none TEST=The console command #dac set as follows: read: dac [ch] write: dac [ch] [voltage] [ch]:2-5, [voltage]:0(disable)-3300 Change-Id: I8e815cb5bc749467581d5f771fd6f9e0995fca3b Signed-off-by: tim <tim2.lin@ite.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2046685 Reviewed-by: Diana Z <dzigterman@chromium.org>
* driver/tcpm/it8xxx2: PD driver for chip it8xxx1/8xxx2Ruibin Chang2020-02-191-93/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add PD driver for chip it8xxx1/8xxx2 series. BRANCH=none BUG=none TEST=test below functions on PDEVB port0, 1, 2 with TCPMv1 (set cc toggle by console cmd): 1.pin configuration console cmd "gpioget" check gpio settings. memory dump check cc pin alternate settings. 2.Tx data error handle Message discard, No GoodCRC, Tx not enable, Timeout errors happen, corresponding INT will be triggered then do properly handle. 3.basic pd connection SNK:connect with adaptor, request max power (15V,3A), state SNK_READY. SRC:enable DRP role, connect with dongle, provide power (5V,1.5A), source Vconn 5v, get ack of cable discover id, state SRC_READY. 4.pd module disable SNK:connect with adapter. console cmd "hibernate sec", driver disable pd module, check still connection with adapter via dead battery rd. And when resume from hibernate, pd init can re-enable pd module, re-connect with adapter. SRC:connect with dongle. console cmd "hibernate sec", driver disable pd module, check cc pin (not Vconn source pin) volt power down to ~0v. And when resume from hibernate, pd init can re-enable pd module, re-connect with dongle. 5.Tx hard reset console cmd "pd port hard", check hard reset message by lecroy analyzer. 6.Tx cable reset check cable reset message by lecroy analyzer. 7.SOP' enable SRC:connects to SNK via E-mark cable. Source Vconn successfully, and receives cable's ack of discover id request. Not source Vconn to cable, and receives nothing of discover id request (this isn't effect on request SNK flow). 8.power role swap console cmd "pd port swap power", check pd protocol by lecroy. Change-Id: I687e0e65e2687ebbb790eb1e1c8c459305f4dbc1 Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2009538 Reviewed-by: Jett Rink <jettrink@chromium.org>
* Cleanup: Add chip support pd physical port count configurationRuibin Chang2020-01-221-1/+0
| | | | | | | | | | | | | | | Add chip support pd physical port count configuration. BUG=none BRANCH=none TEST=build all -j Change-Id: Ic473e53af44b5360aad6d2db74cf09ce5a3fa3e8 Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2009537 Tested-by: Ruibin Chang <Ruibin.Chang@ite.com.tw> Reviewed-by: Jett Rink <jettrink@chromium.org> Commit-Queue: Ruibin Chang <Ruibin.Chang@ite.com.tw>
* chip/it8xxx2: Don't let internal flash go into deep power down modeDino Li2019-12-231-0/+2
| | | | | | | | | | | | | | | | | We got an issue on IT83202BX that flash won't be able to wake up correctly in EC low power mode when WRST# is asserted. This issue might cause cold reset failure so we made this change to fix it. BUG=none BRANCH=none TEST=hibernate EC and then press servo board's COLD_RST_L to reset EC. EC reboots. Change-Id: Ide3a240e1fe62d712536c69d8f390241e67144f6 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1973974 Reviewed-by: Jett Rink <jettrink@chromium.org>
* it83xx/spi: add spi slave functiontim2019-12-111-0/+36
| | | | | | | | | | | | | | | | Add the spi slave function which is required to communicate with the EC when the CPU is the ARM processor. BUG=none BRANCH=none TEST=Replaced board elm's EC with it83202 and boot kernel and keyboard work. Change-Id: I7ce3bb56450276997b58e84b1c6de3f8e45bb4b7 Signed-off-by: tim <tim2.lin@ite.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1918991 Reviewed-by: Jett Rink <jettrink@chromium.org>
* chip/it8xxx1, chip/it8xxx2: GPIO, WUC and IRQ for chip it83201/it83202Ruibin Chang2019-11-221-10/+189
| | | | | | | | | | | | | | | | | | | | GPIO, WUC and IRQ changes for chip it83201/it83202. BRANCH=None BUG=b:133460224 TEST=test GPIO group O, P, Q, R 1.Input: external input 3.3v, GPDR of corresponding pin is 1. (GCR31, GCR32 select 1.8v, validate again for O and P group) 2.Output: GPDR of corresponding pin set 1, measure 3.3v. 3.INT: GPIO_INT input trigger => WU INT (select high, low, rising, falling, both edge trigger mode) => INT => CPU INT 4.Test power-up and down with this CL on ampton. Change-Id: Ifae081c87b3dafcf3f7da84f637ceaf64a5ed536 Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1675704 Reviewed-by: Jett Rink <jettrink@chromium.org>
* it83xx/flash: add support for KGD flashDino Li2019-10-211-0/+3
| | | | | | | | | | | | | | | Embedded flash of it8xxx2 is KGD, so we made this change to support it. BUG=b:133460224 BRANCH=none TEST=On both it83202 and it8320 EVBs, verify flasherase and flashwrite console commands. Change-Id: Idde0846eb8c59a330ccf69d7f6b7aa352c623caa Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1844657 Reviewed-by: Jett Rink <jettrink@chromium.org>
* chip/it83xx: introduction of IT83202/BX versionDino Li2019-10-171-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Changing PLL and standby instruction didn't work on AX have been fixed on this version, so we can remove patches dedicated for AX. - Enable more chip config option. - Disable IT83XX_INTC_GROUP_21_22_SUPPORT option: Because IT8xxx2 series has its own interrupt group 21 and 22, so we will create another CL to support them. - System triggers a soft reset by default if IT83XX_ETWD_HW_RESET_SUPPORT option is enabled. BUG=b:134542199; b:133460224; b:142029177 BRANCH=none TEST=boots on BX version. console command reboot: reboot hard Hard-Rebooting! [Reset cause: power-on hard] reboot Rebooting! [Reset cause: soft] Change-Id: I06e57952cd758b4f344ada0f87729c961b1e747b Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1835884 Reviewed-by: Jett Rink <jettrink@chromium.org>
* it83xx/register: rename the register of MCCR3 to RVILMCR0Dino Li2019-07-031-1/+1
| | | | | | | | | | | | | | This register is specific to the risc-v core. We only apply the register to risc-v core. BUG=none BRANCH=none TEST=console commands: flasherase and flashwrite Change-Id: I241179170ca1394dca4f7631b266a57f959fe036 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1684955 Reviewed-by: Jett Rink <jettrink@chromium.org>
* it83xx/i2c_slave: the DMA registers have updated on IT8xxx2tim2019-07-021-0/+4
| | | | | | | | | | | | | | The DMA read and write target address registers have changed. BUG=none BRANCH=none TEST=Testing on IT8320dx and IT83202 EVB. Change-Id: I9e63c3f7f402ed22c461eb86daa5eba0e6dcb58e Signed-off-by: tim <tim2.lin@ite.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1660071 Commit-Queue: Jett Rink <jettrink@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* LICENSE: remove unnecessary (c) after CopyrightTom Hughes2019-06-191-1/+1
| | | | | | | | | | | | | | | | Ran the following command: git grep -l 'Copyright (c)' | \ xargs sed -i 's/Copyright (c)/Copyright/g' BRANCH=none BUG=none TEST=make buildall -j Change-Id: I6cc4a0f7e8b30d5b5f97d53c031c299f3e164ca7 Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1663262 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* core:RISC-V / chip:IT83202Dino Li2019-06-111-1/+10
| | | | | | | | | | | | | | | | The IT83202 is an embedded controller with RISC-V core. It supports maximum ram size to 256KB and internal flash to 1MB. BUG=none BRANCH=none TEST=EC boots and test console commands (eg: taskinfo, version, sysjump...) on it83202 EVB. Change-Id: I424c0d2878beb941c816363b5c7a3f57fda9fd13 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1588300 Reviewed-by: Jett Rink <jettrink@chromium.org> Commit-Queue: Jett Rink <jettrink@chromium.org>
* tcpm/it83xx.c: Bx and Dx transmit status bit of pd register swapRuibin Chang2019-04-301-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | Chip Bx and Dx transmit status bit (PD register offset 0x18, MTCR) swap. Bx: bit5, 1'b0 = none 1'b1 = goodcrc not received and retry times arrive bit1, 1'b0 = transmit OK 1'b1 = goodcrc not received or Tx discarded Dx: bit5, 1'b0 = transmit OK 1'b1 = goodcrc not received or Tx discarded bit1, 1'b0 = none 1'b1 = goodcrc not received and retry times arrive BRANCH=None BUG=None TEST=Test by device which do not respond goodcrc message Change-Id: Ia07ad4bdb7f4800b62a25eb88ac42e42311faa7d Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1545800 Reviewed-by: Jett Rink <jettrink@chromium.org>
* it83xx/i2cs: add i2c slave functiontim2019-03-301-0/+46
| | | | | | | | | | | | | | | | | | | | | | | | The I2C function of IT8320 is used as the slave. The slave channel A can support 16-byte FIFO for read and write data. The enhanced I2C channel D, E and F can support read and write 256-byte data by DMA mode. When master transmits data to slave, the interrupt signal will generate, and the data will be saved to buffer. BUG=none BRANCH=none TEST=none Change-Id: I167215352119ec11dfd96eb1f33abc1e2111dead Signed-off-by: tim <tim2.lin@ite.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/1488273 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Tim2 Lin <tim2.lin@ite.corp-partner.google.com> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
* common: replace 1 << digits, with BIT(digits)Gwendal Grignou2019-03-261-65/+65
| | | | | | | | | | | | | | | | Requested for linux integration, use BIT instead of 1 << First step replace bit operation with operand containing only digits. Fix an error in motion_lid try to set bit 31 of a signed integer. BUG=None BRANCH=None TEST=compile Change-Id: Ie843611f2f68e241f0f40d4067f7ade726951d29 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1518659 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* it83xx/intc:add type-c plug in interruptRuibin Chang2018-12-181-0/+8
| | | | | | | | | | | | | | | When tcpc detect type-c plug in (cc lines voltage change), it will interrupt fw to wake pd task, so task can react immediately. BRANCH=None BUG=None TEST=GRL USBPD test Change-Id: I194b2fcad1d0c62dde2d3296753abd47af8feea6 Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/1333207 Reviewed-by: Jett Rink <jettrink@chromium.org>
* ite: Add support for 3rd Type C port in bbramScott Collyer2018-09-131-2/+3
| | | | | | | | | | | | | | | | | DragonEgg has 3 Type C ports and needs BRAM_IDX_PD2 as only 2 ports were supproted previously. BUG=b:111281797 BRANCH=none TEST=Verfied that error messages from invalid bram_idx went away. Change-Id: I242850a89413f0a573155e5e325f4e0a540d33e6 Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/1178996 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* it83xx: clear BRAM if it is not validDino Li2018-08-031-4/+18
| | | | | | | | | | | | | | | | | IT8320 do not have indicator for VBAT power to indicate if BRAM is valid or not, so we create a magic number to do the job. And BRAM will get cleared if it is not valid. BUG=none BRANCH=none TEST=BRAM will be cleared if valid field of BRAM doesn't match the magic number. Change-Id: I6f3b166830f6c2f33f663ec0e5da9178d81d397b Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/1158453 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* IT8320DX: espi: reset espi module by FWDino Li2018-07-201-0/+4
| | | | | | | | | | | | | | | | | | | | | | | There is a bug on DX's espi_reset# pin. So we can't enable hardware mechanism of espi_reset#. To workaround this issue, this CL introduces a new macro to config_chip.h IT83XX_ESPI_RESET_MODULE_BY_FW which is defined when CHIP_VRAIANT is IT8320DX. When this macro is defined, the epsi hw reset pin function is disabled. Instead, the interrupt handler for this espi reset pin uses the GCTRL_RSTS register to force a reset of VCC domain logic in the EC which resets the eSPI and LPC modules. BUG=b:111480168 BRANCH=none TEST=The eSPI module is reset when EC's espi_reset# pin is asserted. Change-Id: Id7dfe746e7463c95735dde9a17777f3fce1030d0 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/1138134 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* tcpm: it83xx: IT8320 family compatibilityDino Li2018-07-161-0/+14
| | | | | | | | | | | | | | | | | | | | | | | The bit7 and bit3 at UFPVDR register are reserved on BX version. But in DX version, these two bits are used to get the result of fast swap voltage comparing in UFP mode. So we change to mask three bits only. Add the support of two TX SOP type on the DX version. (Debug SOP' and Debug SOP'') On BX version, cc1/cc2 voltage detector function is enabled by bit1 or bit5 at register CCCSR. But on DX version, the bit1 will control both cc1 and cc2. So we create an option for this change. BUG=none BRANCH=none TEST=Plug USB-C power adapter and USB-C to hdmi adapter, both work. Change-Id: If881ef54145f211f7d48a971f56a6118487d9eed Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/1119729 Reviewed-by: Jett Rink <jettrink@chromium.org>
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