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* Update license boilerplate text in source code filesMike Frysinger2022-09-121-1/+1
| | | | | | | | | | | | | | | Normally we don't do this, but enough changes have accumulated that we're doing a tree-wide one-off update of the name & style. BRANCH=none BUG=chromium:1098010 TEST=`repo upload` works Change-Id: Icd3a1723c20595356af83d190b2c6a9078b3013b Signed-off-by: Mike Frysinger <vapier@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3891203 Reviewed-by: Jeremy Bettis <jbettis@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* chip/it83xx/spi.c: Format with clang-formatJack Rosenthal2022-06-291-16/+15
| | | | | | | | | | | BUG=b:236386294 BRANCH=none TEST=none Change-Id: Id90f7f082098367af8f89b8a7bb9b8594958da74 Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729215 Reviewed-by: Jeremy Bettis <jbettis@chromium.org>
* ec: ite: Use EC_SPI_RX_READY macroSam Hurst2022-05-311-1/+1
| | | | | | | | | | | | | | | | Using EC_SPI_RX_READY instead of EC_SPI_OLD_READY prevents the SDO line going high when the AP shuts down. BUG=b:216831450 BRANCH=none TEST=zmake testall Verified on scope that SHI_SDO does not pulse high during AP Shutdown Signed-off-by: Sam Hurst <shurst@google.com> Change-Id: I08e0045b7712944fe5a951ef88d9b5a9504a2093 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3674598 Reviewed-by: Wai-Hong Tam <waihong@google.com>
* tree: Make all host commands staticTom Hughes2021-10-151-2/+7
| | | | | | | | | | | | | | Almost all of the host commands were already static. This change makes all of them static for consistency. BRANCH=none BUG=b:172020503 TEST=make buildall -j Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: I8330e85e6d64a039f08d7620eed1fe897f436567 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3221786 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* COIL: chip/it83xx: Rename SPI IRQ configCaveh Jalali2021-08-021-4/+4
| | | | | | | | | | | | | | | This renames the ITE chip specific SPI IRQ config from IT83XX_IRQ_SPI_SLAVE to IT83XX_IRQ_SPI_PERIPHERAL. BRANCH=none BUG=b:181607131 TEST=compare_build.sh matches Change-Id: Ib7a7674e6cf4f0bf81ee47b5f60225f77236f578 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3061913 Commit-Queue: Harry Cutts <hcutts@chromium.org> Reviewed-by: Harry Cutts <hcutts@chromium.org>
* COIL: chip/it83xx: Update SPI terminologyCaveh Jalali2021-08-021-14/+14
| | | | | | | | | | | | BRANCH=none BUG=b:181607131 TEST=compare_build.sh matches Change-Id: I6f5ac12ff64fe870709dc91bca71e0901bed3420 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3061911 Commit-Queue: Harry Cutts <hcutts@chromium.org> Reviewed-by: Harry Cutts <hcutts@chromium.org>
* it8xxx2/spi: re-init spi module after disable emmc boot modeDino Li2021-06-101-0/+17
| | | | | | | | | | | | | | | | This CL reset and re-initialize SPI module after AP jumped to BL. So EC will have a good state to start receiving AP's commands. BRANCH=icarus BUG=b:184702635 TEST=on cozmo, confirm that EC doesn't miss the first command from AP after booting. Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Change-Id: Ib7cf0e9cb70a67950d53d3abc7df42969c9b4dc2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2947422 Tested-by: Eric Yilun Lin <yllin@google.com> Reviewed-by: Eric Yilun Lin <yllin@google.com>
* it83xx/spi: add support emmc boot modeDino Li2020-12-291-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | IT81202 bx version can configure SPI module to work as eMMC boot mode to catch CMD0. Once this mode is enabled, SPI's CS# pin isn't required. HW will drop data until CMD goes low (CMD0 starts with 01b) and saving 128 bytes in RX FIFO. FW need to parse the data of FIFO and handle argument of CMD0 (GO_IDLE_STATE, GO_PRE_IDLE_STATE, and BOOT_INITIATION). Pinmux of eMMC boot mode are as following: GPM2->CLK GPM3->CMD GPM6->DATA0 BUG=b:170795623 BRANCH=none TEST=boot to kernel on Juniper (replace EC with it81202 bx). Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Change-Id: I1dac1848bfd79f4a7dc02e1d90905e0cd6b8af3f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2604802 Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* it83xx/spi: clean up unnecessary configurationtim2020-10-281-72/+36
| | | | | | | | | | | | | | | Rx valid length interrupt has been set as default, so the configuration of IT83XX_SPI_RX_VALID_INT can be removed. BUG=none BRANCH=none TEST=Boot to kernel on HAYATO and no error on the transaction of host command with EC. Change-Id: I92ab78b3e821f566053c816f51bf609394f3b199 Signed-off-by: tim <tim2.lin@ite.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2497366 Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* it83xx/spi: change configuration to IS_ENABLED() styletim2020-08-191-69/+67
| | | | | | | | | | | BUG=none BRANCH=none TEST=No error on the command of get EC protocol info. Signed-off-by: tim <tim2.lin@ite.corp-partner.google.com> Change-Id: I08d87bd20e60520c891f1b99d78ff91c1e89b2cb Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2359613 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* it83xx/spi: enable rx valid length interruptDino Li2020-08-141-0/+42
| | | | | | | | | | | | | | | | | | | | | Enable IT83XX_SPI_RX_VALID_INT which can obtain data length field of host requested. When received data to reach, Rx valid interrupt will be fired then start to parse. Instead of waiting for Rx 256 bytes reach interrupt method, this is effectively saving time to complete once transaction. BUG=b:160662061; b:161509047 BRANCH=none TEST=Boot to kernel with it81202 on asurada. No error on the command of get EC protocol info with 1MHz clock frequency. Change-Id: Ib56e3034d3ee39fa64818b95747eb7e9e5821294 Signed-off-by: tim <tim2.lin@ite.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2076826 Reviewed-by: Ting Shen <phoenixshen@chromium.org> Tested-by: Hung-Te Lin <hungte@chromium.org> Commit-Queue: Hung-Te Lin <hungte@chromium.org>
* ec: change usage of dummySam Hurst2020-08-051-2/+2
| | | | | | | | | | | | | | | | | | Google is working to change its source code to use more inclusive language. To that end, replace the term "dummy" with inclusive alternatives. BUG=b:162781382 BRANCH=None TEST=make -j buildall `grep -ir dummy *` The only results are in "private/nordic_keyboard/sdk8.0.0" which is not our code. Signed-off-by: Sam Hurst <shurst@google.com> Change-Id: I6a42183d998e4db4bb61625f962867fda10722e2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2335737 Reviewed-by: Tom Hughes <tomhughes@chromium.org>
* it83xx/spi: Reset SPI module before sysjumpDino Li2020-07-211-2/+15
| | | | | | | | | | | | | | | | | BUG=b:161327069 BRANCH=none TEST=No complaining bad data from SPI continuously after sysjump. NOTE: We might get one bad data message after sysjump (eg: "sysjump rw" command). Because EC isn't ready to receive data but request from AP might be already started. Change-Id: Ibe83c0b54c234022338a30c35b1b0564f7e5f266 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2301323 Tested-by: Eric Yilun Lin <yllin@chromium.org> Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* it83xx/spi: enable Rx byte reach(256 bytes) interrupttim2020-07-101-15/+15
| | | | | | | | | | | | | | | When Rx received data reaches FIFO target count, the status of Rx byte reach interrupt bit is set then start to parse transaction. BUG=b:160662061 BRANCH=none TEST=EC can receive more than 128 bytes(up to 256 bytes) from host. Signed-off-by: tim <tim2.lin@ite.corp-partner.google.com> Change-Id: I3e922265e35f5bc46e794e92adb1bede20f73498 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2284513 Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* it83xx/spi: drop static modifierYilun Lin2020-06-101-1/+1
| | | | | | | | | | | | | | | | spi_get_protocol_info is now declared in the spi.h, so we should drop the modifier. BRANCH=master BUG=none TEST=make buildall -j Change-Id: I499f0a99f05d6881dd76ceb873b28d362b86068c Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2235239 Commit-Queue: Eric Yilun Lin <yllin@chromium.org> Tested-by: Eric Yilun Lin <yllin@chromium.org> Reviewed-by: Tzung-Bi Shih <tzungbi@chromium.org>
* it83xx/spi: enable auto reset rx fifo functiontim2020-04-021-83/+63
| | | | | | | | | | | | | | | | | | | | | | | | In this change, we enable IT83XX_SPI_AUTO_RESET_RX_FIFO. When CS# deasserted, the rx fifo and fifo count can auto reset in time by the hardware way to avoid the time delay caused. And we removed the spi_chipset_startup and shutdown. we don't need to disable the interrupt of GPIO_SPI0_CS via hook during chipset suspend and enable it during chipset resume. Instead, when the interrupt of GPIO_SPI0_CS occurs, we judge whether the chipset state is enabled and then to disable deep sleep. BUG=none BRANCH=none TEST=boot to kernel with it81202 on elm board. Press the button to shutdown and resume testing 10 times are normal. Signed-off-by: tim <tim2.lin@ite.corp-partner.google.com> Change-Id: I263d63fa5c22ef430d8f807c694317b7496f238f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2100372 Reviewed-by: Jett Rink <jettrink@chromium.org> Commit-Queue: Dino Li <Dino.Li@ite.com.tw>
* it83xx/spi: add spi slave functiontim2019-12-111-0/+369
| | | | | | | | | | | | | | | | Add the spi slave function which is required to communicate with the EC when the CPU is the ARM processor. BUG=none BRANCH=none TEST=Replaced board elm's EC with it83202 and boot kernel and keyboard work. Change-Id: I7ce3bb56450276997b58e84b1c6de3f8e45bb4b7 Signed-off-by: tim <tim2.lin@ite.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1918991 Reviewed-by: Jett Rink <jettrink@chromium.org>
* it83xx/spi: rename spi.c to spi_master.ctim2018-12-131-171/+0
| | | | | | | | | | | | | | | | | In it83xx chip, the file of spi.c is renamed to spi_master.c, and the related config is renamed too. BUG=none BRANCH=none TEST=none Change-Id: Ia696e62afa2ff06da68a3e4af685615b1dbcc8e9 Signed-off-by: tim <tim2.lin@ite.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/1372870 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Tim2 Lin <tim2.lin@ite.corp-partner.google.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* spi: Add lock around spi_transactionShawn Nematbakhsh2016-10-041-0/+3
| | | | | | | | | | | | | | | | | | | | | | spi_transaction() can be called from motionsense, hooks, hostcmd, console, and chipset tasks, so add a mutex to ensure an in-process transaction isn't preempted by another transaction. BUG=chrome-os-partner:57912 BRANCH=gru TEST=On kevin, run "while true; do ectool motionsense odr 0 0; sleep 1; ectool motionsense odr 0 1000000; sleep 1; done", verify watchdog crash not encountered after 20 minutes. Change-Id: I7ec495bab295dc03ce02372c20e5c7c5c196715d Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/391892 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> (cherry picked from commit eabdea443775fab834aaabbb7afae871306c7530) Reviewed-on: https://chromium-review.googlesource.com/392226 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* it83xx: Support different PLL frequencies setting (24/48/96 MHz)Dino Li2016-06-141-3/+0
| | | | | | | | | | | | | | | | | | | | | | | Default setting is at 48MHz. For PLL frequency at 24MHz: 1. USB module can't work, it requires 48MHz to work. 2. SSPI clock frequency is divide by two. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=1. uart, i2c, timer, and pd modules are function normally at different PLL frequency settings. 2. use 'flashrom' utility to flash EC binary with different PLL settings. Change-Id: Iabce4726baff493a6136136af18732b58df45d7f Reviewed-on: https://chromium-review.googlesource.com/347551 Commit-Ready: Dino Li <Dino.Li@ite.com.tw> Tested-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* hooks: Add relative HOOK_INIT priority for peripheralsShawn Nematbakhsh2016-05-051-1/+1
| | | | | | | | | | | | | | | | | | | Using HOOK_PRIO_DEFAULT for peripheral initialization necessitates using HOOK_PRIO_DEFAULT+1 for board-level code. Instead, use a higher-than-default relative priority for peripheral initialization outside of board. BUG=None TEST=Verify PWM and ADC are functional on kevin. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Ia8e90a7a866bdb0a661099dd458e3dfcaaa3f6bb Reviewed-on: https://chromium-review.googlesource.com/342171 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* it8380dev: improve power consumptionDino Li2015-11-171-0/+1
| | | | | | | | | | | | | | | | In doze mode, these improvements help reduce EC power consumption. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=Power consumption has reduced. Change-Id: I8b0fe3301e408134284b4ac5778656ba9b92b0f1 Reviewed-on: https://chromium-review.googlesource.com/312632 Commit-Ready: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* it8380dev: modify sspi moduleDino Li2015-08-041-22/+33
| | | | | | | | | | | | | | | | | We need to modify SSPI module to fix compile fail due to SPI flash common code changed. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=console "spi_flashinfo" OK Change-Id: I83bb645eff1e5874d849056df518eea92340c39e Reviewed-on: https://chromium-review.googlesource.com/290089 Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw>
* common: change interface to SPI flashGwendal Grignou2015-07-301-3/+5
| | | | | | | | | | | | | | | | Allow more than one SPI master. Add CONFIG variables to address the system SPI flash. To have SPI master ports, spi_ports array must be defined. BRANCH=smaug TEST=compile BUG=chrome-os-partner:42304 Change-Id: Id43869f648965c1582b7be1c7fb3a38f175fda95 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/288512 Commit-Queue: David James <davidjames@chromium.org>
* it8380dev: add i2c control moduleDino Li2015-06-301-3/+3
| | | | | | | | | | | | | | | | | | | | Add i2c control module for emulation board. To rename CONFIG_ to CONFIG_IT83XX_ for IT83XX series configuration. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=1. console command "i2cscan" found devices correctly. 2. console command "i2cxfer". 2-a. port2 + battery, i2cxfer r, r16, and rlen OK. 2-b. port1 + slave evb, i2cxfer r, r16, rlen, w, and w16 OK. Change-Id: I67165f7dcdef538ba6dd03b47f1621a73cc68379 Reviewed-on: https://chromium-review.googlesource.com/263678 Reviewed-by: Alec Berg <alecaberg@chromium.org> Commit-Queue: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw>
* it8380dev: add sspi control moduleDino Li2015-06-231-0/+157
Add sspi control module for emulation board. Signed-off-by: Dino Li <dino.li@ite.com.tw> BRANCH=none BUG=none TEST=EVB + Winbond W25Q80 SPI ROM To define CONFIG_SPI_FLASH, CONFIG_SPI_FLASH_SIZE, and CONFIG_SPI_FLASH_W25X40 console "spi_flashinfo" can get SPI information > spi_flashinfo Manufacturer ID: ef Device ID: 40 14 Unique ID: c8 60 84 a1 1f 6a 7f 2f Capacity: 1024 MB Change-Id: I6c4d4d977536484d47a2207ed80dd0ea08a7c8fd Reviewed-on: https://chromium-review.googlesource.com/267403 Reviewed-by: Alec Berg <alecaberg@chromium.org> Commit-Queue: Dino Li <dino.li@ite.com.tw> Tested-by: Dino Li <dino.li@ite.com.tw>
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