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* chip: it83xx/gpio: condition for adding judgmentTim Lin2021-09-131-1/+1
| | | | | | | | | | | | | | | If there is an I/O expander driver for keyboard, there is no need to enter the keyboard_raw_interrupt(). BUG=b:199337186 BRANCH=none TEST=make buildall -j4 Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com> Change-Id: Ie24f5b5592325a76d9a36a689657bdd2e05c8fb1 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3151046 Reviewed-by: Eric Yilun Lin <yllin@google.com> Commit-Queue: Eric Yilun Lin <yllin@google.com>
* it83xx/nds32: Ensure EXT_IER has been disabled before enabling CPU interruptDino Li2021-09-022-1/+12
| | | | | | | | | | | | | | | | | | This CL read (load operation) an EC's extended interrupt enable register one time after configured. The load operation will ensure chip-level's interrupt has been disabled before enabling CPU interrupt. This CL will also assert failure if EC get interrupt number 0 in ISR. BRANCH=dedede BUG=b:197308582 TEST=No system reboot on storo during the drop test. Change-Id: I593d78626d1e3bb92e5316d1ff78f0ee54711741 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3124483 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* it83xx/riscv: Ensure IER has been disabled before enabling CPU interruptDino Li2021-09-021-1/+9
| | | | | | | | | | | | | | | | | | | | | This CL read EC's IER one time after configured. The load operation will ensure chip-level's interrupt has been disabled before enabling CPU interrupt. BRANCH=asurada, icarus BUG=b:179206540 TEST=create stress test on it8xxx2 evb: - Loop calling task_disable_irq() and task_enable_irq() to enable and disable IRQ 13 (keyboard KSI interrupt). - Toggle KSI continuously. Without the patch, EC will hit IRQ 0 issue in two seconds. Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Change-Id: I56bad182bd101d45b00368083b60aabbd9fb8bdb Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3139652 Reviewed-by: Eric Yilun Lin <yllin@google.com> Commit-Queue: Eric Yilun Lin <yllin@google.com>
* it83xx/irq: there is no need to configure IER on nds32 core chipDino Li2021-09-011-2/+10
| | | | | | | | | | | | | | | Configure interrupt enable register is redundant on nds32 core chip (IT8320). We just need to configure extended IER. BRANCH=asurada, dedede BUG=b:197308582 TEST=buildall passes, storo and hayato boot. Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Change-Id: I8f99f7b937ac98d95b2f50f5be7b461ae3e9a413 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3134888 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* adc: Include adc_chip.h from adc.hCaveh Jalali2021-08-272-7/+2
| | | | | | | | | | | | | | | | This reorganizes adc.h and adc_chip.h so that general code only needs to know about adc.h. adc_chip.h is now included by adc.h directly and does not need to be included in general code. BRANCH=none BUG=b:181271666 TEST=buildall passes (with next patch in series) Cq-Depend: chromium:3120316 Change-Id: I8bc107c6900e831a57f7a7fb8668eb08bb179d6c Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3120315 Reviewed-by: Keith Short <keithshort@chromium.org>
* system: fix system_get_scratchpad APIYuval Peress2021-08-201-9/+4
| | | | | | | | | | | | | | | The current API for system_get_scratchpad mixes the status and the value being read. Update the signature to allow both. BRANCH=none BUG=b:195481980 TEST=make testall && zmake testall Signed-off-by: Yuval Peress <peress@chromium.org> Change-Id: I3a5f5ad523d507c53a5d474806f58afafb82e70c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3074828 Commit-Queue: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Denis Brockus <dbrockus@chromium.org>
* COIL: chip/it83xx: Rename SPI IRQ configCaveh Jalali2021-08-025-10/+10
| | | | | | | | | | | | | | | This renames the ITE chip specific SPI IRQ config from IT83XX_IRQ_SPI_SLAVE to IT83XX_IRQ_SPI_PERIPHERAL. BRANCH=none BUG=b:181607131 TEST=compare_build.sh matches Change-Id: Ib7a7674e6cf4f0bf81ee47b5f60225f77236f578 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3061913 Commit-Queue: Harry Cutts <hcutts@chromium.org> Reviewed-by: Harry Cutts <hcutts@chromium.org>
* COIL: chip/it83xx: Rename SPI MAX_FREQ configCaveh Jalali2021-08-023-7/+16
| | | | | | | | | | | | | | | | This renames the ITE chip specific SPI speed configuration from IT83XX_ESPI_SLAVE_MAX_FREQ_CONFIGURABLE to IT83XX_ESPI_PERIPHERAL_MAX_FREQ_CONFIGURABLE. BRANCH=none BUG=b:181607131 TEST=compare_build.sh matches Change-Id: If2fcb086a8c35cf43ce15dc0963f3febbaa25f45 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3061912 Commit-Queue: Harry Cutts <hcutts@chromium.org> Reviewed-by: Harry Cutts <hcutts@chromium.org>
* COIL: chip/it83xx: Update SPI terminologyCaveh Jalali2021-08-023-39/+39
| | | | | | | | | | | | BRANCH=none BUG=b:181607131 TEST=compare_build.sh matches Change-Id: I6f5ac12ff64fe870709dc91bca71e0901bed3420 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3061911 Commit-Queue: Harry Cutts <hcutts@chromium.org> Reviewed-by: Harry Cutts <hcutts@chromium.org>
* it83xx: i2c: don't check bus busy if transaction is ongoing.Dino Li2021-07-301-4/+9
| | | | | | | | | | | | | | | | | | | | | This CL fixes that i2c driver will prompt "I2C chx reset cause 1" issue when one i2c transaction is separated into at least three i2c_xfer and I2C_XFER_START flag is set at least two times. eg. - i2c_xfer with I2C_XFER_START flag - i2c_xfer with I2C_XFER_START flag <= this will cause reset - xxx - i2c_xfer with I2C_XFER_STOP flag BRANCH=none BUG=none TEST=no i2c reset on Asurada, Drawcia, and ADL-RVP. Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Change-Id: I97161db0bb0c54de3ad55d82512a6a188036270f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3058724 Tested-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Eric Yilun Lin <yllin@google.com>
* it83xx: pwm: fix wrong index of pwm_channelsDino Li2021-07-211-3/+3
| | | | | | | | | | | | | BRANCH=none BUG=b:194047863 TEST=On spherion, no keyboard backlight blinking. Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Change-Id: I847291268720bf12ca98b3e38e29a556ec038cd0 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3043075 Tested-by: Ben Chen <ben.chen2@quanta.corp-partner.google.com> Reviewed-by: Ting Shen <phoenixshen@chromium.org> Reviewed-by: Eric Yilun Lin <yllin@google.com>
* driver/tcpm/ite_pd_intc: separate pd interrupt to ite_pd_intcRuibin Chang2021-07-091-78/+1
| | | | | | | | | | | | | | | | | Separate pd interrupt functions to ite_pd_intc for easier maintenance on cros_ec and zephyr. And enable PD interrupt functions for zephyr. BRANCH=none BUG=none TEST=1.can zmake hayato and make asurada 2.PD port functions work on board hayato Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw> Change-Id: I67082bb442da7dfb669e23d8315d81f4abe7ba76 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2999358 Reviewed-by: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org>
* it8xxx2/spi: re-init spi module after disable emmc boot modeDino Li2021-06-101-0/+17
| | | | | | | | | | | | | | | | This CL reset and re-initialize SPI module after AP jumped to BL. So EC will have a good state to start receiving AP's commands. BRANCH=icarus BUG=b:184702635 TEST=on cozmo, confirm that EC doesn't miss the first command from AP after booting. Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Change-Id: Ib7cf0e9cb70a67950d53d3abc7df42969c9b4dc2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2947422 Tested-by: Eric Yilun Lin <yllin@google.com> Reviewed-by: Eric Yilun Lin <yllin@google.com>
* include/flash: rename the APIsTim Lin2021-06-092-14/+15
| | | | | | | | | | | | | | | | The names conflict when enabling both Zephyr's flash driver and CONFIG_FLASH_CROS option. Rename all the APIs in include/flash.h BUG=b:187192628 BRANCH=none TEST=make buildall -j4 Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com> Change-Id: If1fd0ea28fa9f5cec1c1daa8f72f63eb7a0e6500 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2931749 Commit-Queue: Keith Short <keithshort@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Denis Brockus <dbrockus@chromium.org>
* it8xxx2/irq: wait until two equal interrupt values are readDino Li2021-06-081-1/+5
| | | | | | | | | | | | | | | This CL ensures that CPU won't get an IRQ number which is in generating. BRANCH=none BUG=b:179206540, b:189534384 TEST=No panic of unhandled irq. Change-Id: I934fc9ba7aeef520f5e275e8889722c7357c77f1 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2935652 Reviewed-by: Eric Yilun Lin <yllin@google.com> Commit-Queue: Eric Yilun Lin <yllin@google.com> Tested-by: Eric Yilun Lin <yllin@google.com>
* COIL: espi: replace VW_SLAVE_BTLD_STATUS_DONE with ↵Caveh Jalali2021-06-041-1/+1
| | | | | | | | | | | | | | | | | VW_PERIPHERAL_BTLD_STATUS_DONE This replaces VW_SLAVE_BTLD_STATUS_DONE with VW_PERIPHERAL_BTLD_STATUS_DONE. BRANCH=none BUG=b:163885307 TEST=buildall, compare_build.sh pass Change-Id: I0b8c71fa7e590dc89357e22aafce0b67717af183 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2938041 Reviewed-by: Harry Cutts <hcutts@chromium.org> Commit-Queue: Harry Cutts <hcutts@chromium.org>
* COIL: Rename MODULE_SPI_MASTER to MODULE_SPI_CONTROLLERCaveh Jalali2021-06-031-2/+2
| | | | | | | | | | | | | | | | This renames the MODULE_SPI_MASTER to MODULE_SPI_CONTROLLER. BRANCH=none BUG=b:181607131 TEST=make buildall passes; "compare_build.sh -b all" shows no difference Change-Id: I4d33f57fd82c5b57f111c12387113dc82cebe60b Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2932466 Reviewed-by: Craig Hesling <hesling@chromium.org> Reviewed-by: Harry Cutts <hcutts@chromium.org> Commit-Queue: Craig Hesling <hesling@chromium.org>
* COIL: Rename CONFIG_SPI_MASTER to CONFIG_SPI_CONTROLLERCaveh Jalali2021-06-031-1/+1
| | | | | | | | | | | | | | | | This replaces the CONFIG_SPI_MASTERR config option with CONFIG_SPI_CONTROLLER. BRANCH=none BUG=b:181607131 TEST=make buildall passes; "compare_build.sh -b all" shows no difference Change-Id: I3c921085179294765baadf7074652978fe04a4ed Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2932465 Reviewed-by: Craig Hesling <hesling@chromium.org> Commit-Queue: Craig Hesling <hesling@chromium.org>
* it83xx/hwtimer: swap timer 7 and timer 8's applicationDino Li2021-04-272-4/+16
| | | | | | | | | | | | | | | | | | | | This CL change watchdog warning timer to timer 8 (32bit) and change low power mode timer to timer 7 (24bit) The next step will be changing watchdog warning timer to timer 1 (16bit), so we will get a 32bit timer for future use. BUG=b:186028167 BRANCH=none TEST=console command "waitms" "waitms 1200", EC warning but no reset. "waitms 1600", EC warning and reset. No reset after EC waked-up from low power mode. Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Change-Id: Ibf1387ffe334a6e3e82d5b6a72cdb6e099d3a279 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2847671 Reviewed-by: Wai-Hong Tam <waihong@google.com> Reviewed-by: Sam Hurst <shurst@google.com>
* it83xx: disable pre-defined command at defaultDino Li2021-04-082-0/+4
| | | | | | | | | | | | | | | | With this change, no master is able to see the slave device of pre-defined command on port 0. BUG=b:184804044 BRANCH=none TEST=run i2cscan command on icarus, verified that the slave address isn't present on port 0. Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Change-Id: I6df72132d08a3be6ff97fb501eefc4a9fa8d6f08 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2813878 Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* it8xxx2: add support option CONFIG_PRESERVE_LOGSDino Li2021-04-073-1/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On it8xxx2 chips, assert WRST# to reset itself will clear memory content to default value, this is a HW mechanism. So if CONFIG_PRESERVE_LOGS and CONFIG_IT83XX_HARD_RESET_BY_GPG1 are enabled at the same time, we have to save EC logs into flash before reset. We will restore logs from flash on the next initialization before jumping to main routine. BUG=b:183899510, b:183466169 BRANCH=none TEST=1) __image_size is same as ec.RW.bin size. 2) buildall. 3) manually verify reboot, poweroff, and sysjump from AP console: localhost ~ # ectool uptimeinfo EC uptime: 64.755 seconds AP resets since EC boot: 0 Most recent AP reset causes: EC reset flags at last EC boot: reset-pin | power-on localhost ~ # reboot ... localhost ~ # ectool uptimeinfo EC uptime: 19.334 seconds AP resets since EC boot: 0 Most recent AP reset causes: 71.609: reset: at AP's request EC reset flags at last EC boot: reset-pin | power-on | hard localhost ~ # poweroff ... localhost ~ # ectool uptimeinfo EC uptime: 20.627 seconds AP resets since EC boot: 0 Most recent AP reset causes: 71.609: reset: at AP's request 32.149: reset: at AP's request EC reset flags at last EC boot: reset-pin | power-on | hard localhost ~ # ectool reboot_ec RW localhost ~ # ectool uptimeinfo EC uptime: 37.998 seconds AP resets since EC boot: 0 Most recent AP reset causes: 71.609: reset: at AP's request 32.149: reset: at AP's request EC reset flags at last EC boot: reset-pin | power-on | sysjump | hard localhost ~ # Change-Id: I76b5f172b7728dc5ce9bf3a965cb7b2d638f8fc3 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2794322 Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* it83xx/adc: Enable keeping ADC data bufferDino Li2021-03-172-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | IT83xx's ADC data is 10-bit and saving in two registers (VCHxDATL/bit7-0 and VCHxDATM/bit9-8). The CL enables the function of keeping ADC data buffer to prevent reporting incorrect ADC raw data due to the following race condition: 1) adc data valided: 0 0xf8 (voltage is 3x248/1024=0.72v) 2) ec read VCHxDATM(0x0) 3) next adc conversion done: 0x1 0x08 (voltage is 3x264/1024=0.77v) 4) ec read VCHxDATL(0x8) EC will return incorrect voltage (3x8/1024=0.02v) to caller for above conditions. BUG=b:175044329 BRANCH=none TEST=No thermal shutdown on stress test. Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Change-Id: I64d913a2b5d03ca51afcb31ffda6c6ee915338f6 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2759449 Tested-by: rasheed.hsueh <rasheed.hsueh@lcfc.corp-partner.google.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* chip/it83xx: Fix narrowing type warning when included from C++Tom Hughes2021-03-081-3/+3
| | | | | | | | | | | | | | | | | | chip/it83xx/registers.h:861:63: error: constant expression evaluates to -1 which cannot be narrowed to type 'uint32_t' (aka 'unsigned int') [-Wc++11-narrowing] [GPIO_KSI] = { 0x00F01D08, 0x00F01D09, 0x00F01D26, -1 }, BRANCH=none BUG=b:144959033 TEST=make buildall Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: I029cb79e132ce18158440812b26aa57e770ce423 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2740561 Commit-Queue: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Denis Brockus <dbrockus@chromium.org>
* it83xx/gpg1 reset EC: save panic data to bramDino Li2021-02-232-1/+57
| | | | | | | | | | | | | | | | | This change saves panic data to bram before EC reset is triggered if GPG1 reset mechanism is enabled. Because the reset will also clear RAM contents. With this change, we can restore panic data from bram after panic reboot. BUG=b:173075595 BRANCH=none TEST=crash EC and then run the panicinfo command to check if panic data is saved. Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Change-Id: I08f006c7969bce711695459b9f595ccc2fd6900b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2632123 Reviewed-by: Ting Shen <phoenixshen@chromium.org>
* it8xxx2: return -1 if EC INT number isn't validDino Li2021-02-041-0/+3
| | | | | | | | | | | | | | | Returns -1 in chip_get_ec_int() to assert unhandled_interrupt in core/riscv-rv32i/init.S if EC interrupt number isn't valid. BUG=b:179206540 BRANCH=none TEST=boot to kernel on hayato. Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Change-Id: Id55686ae860404b550b8df707387805b48931b61 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2674686 Reviewed-by: Eric Yilun Lin <yllin@chromium.org> Commit-Queue: Eric Yilun Lin <yllin@chromium.org>
* it83xx: deprecate BRAM_IDX_NVCONTEXTJack Rosenthal2021-02-022-13/+1
| | | | | | | | | | | | | | | Unused, as VBNV storage in EC bbram is gone. This makes inxedexs 0x10 to 0x1F in bbram available for future use. BUG=b:178689388 BRANCH=none TEST=buildall Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I013bc2885f06aa853b1fbdabe98d9e5658811e44 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2668689 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* spi: Pass in spi_device as argument to spi_enable instead of portTom Hughes2021-01-281-2/+4
| | | | | | | | | | | | | | | | | | | | | | Rather than passing in the port and iterating over the global spi_devices variable, pass in the specific spi_device that is being enabled/disabled. The spi_device_t struct has the port. This change makes the functions in spi.h more consistent since they now all take a spi_device_t*. This change is the first step in making the SPI configuration more dynamic. BRANCH=none BUG=b:177908650 TEST=git grep 'spi_enable(CONFIG' => no results TEST=make buildall TEST=Flash dragonclaw v0.2 and view console to verify FP sensor ID Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: I64124e0ebcf898e88496acb77703b5f59ae931c2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2654081 Commit-Queue: Abe Levkoy <alevkoy@chromium.org> Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
* it83xx/gpg1 reset EC: handle case of watchdog resetstabilize-13729.16.B-mainDino Li2021-01-151-6/+24
| | | | | | | | | | | | | | | This CL triggers GPG1 HW reset after a EC watchdog. So the EC_RST_ODL signal will be toggled after the reset. BUG=b:173075595 BRANCH=none TEST=trigger watchdog to reboot system and verified system is able to boot to kernel. Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Change-Id: I5d7a88dbb4bdb00977bc1fa02e5fa61e52347104 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2627536 Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* Refactor CONFIG_FLASH_SIZE to CONFIG_FLASH_SIZE_BYTESYuval Peress2021-01-153-9/+9
| | | | | | | | | | | | | | | | | | | | | In Zephyr CONFIG_FLASH_SIZE is a Kconfig value that is used throughout. The issue is that the units don't match. In Zephyr the value is in KiB instead of bytes. This refactor simply renames CONFIG_FLASH_SIZE in platform/ec to include the unit (via _BYTES). BRANCH=none BUG=b:174873770 TEST=make buildall be generated by the build instead of per board Signed-off-by: Yuval Peress <peress@chromium.org> Change-Id: I44bf3c7a20fcf62aaa9ae15715be78db4210f384 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2627638 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Hughes <tomhughes@chromium.org> Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
* version: Rename version.h to cros_version.hYuval Peress2021-01-071-1/+1
| | | | | | | | | | | | | | | This change simply moves the include/version.h file over to avoid a naming collision with zephyr's version.h. BRANCH=none BUG=b:167392037 TEST=make buildall -j Signed-off-by: Yuval Peress <peress@chromium.org> Change-Id: Ib41b3c21817d5f81e713d3b550bc46a0d1c55cf8 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2612772 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
* it83xx/system: introduce GPG1 reset EC featureDino Li2021-01-071-0/+7
| | | | | | | | | | | | | | | | | This CL added option of CONFIG_IT83XX_HARD_RESET_BY_GPG1. If we enabled the option, EC will assert GPG1 pin to reset itself instead of triggering an internal reset while receiving a reset request. BUG=b:173075595 BRANCH=none TEST=Enable CONFIG_IT83XX_HARD_RESET_BY_GPG1 and check if GPG1 goes high while receiving reset command. Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Change-Id: I930424c374dcbd742b8ecca7a1fa720699d42bb6 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2612233 Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* it83xx/spi: add support emmc boot modeDino Li2020-12-293-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | IT81202 bx version can configure SPI module to work as eMMC boot mode to catch CMD0. Once this mode is enabled, SPI's CS# pin isn't required. HW will drop data until CMD goes low (CMD0 starts with 01b) and saving 128 bytes in RX FIFO. FW need to parse the data of FIFO and handle argument of CMD0 (GO_IDLE_STATE, GO_PRE_IDLE_STATE, and BOOT_INITIATION). Pinmux of eMMC boot mode are as following: GPM2->CLK GPM3->CMD GPM6->DATA0 BUG=b:170795623 BRANCH=none TEST=boot to kernel on Juniper (replace EC with it81202 bx). Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Change-Id: I1dac1848bfd79f4a7dc02e1d90905e0cd6b8af3f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2604802 Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* tcpm: Move tcpm.h into an include directorySimon Glass2020-12-221-1/+1
| | | | | | | | | | | | | | | | | | This header file is used from quite a few files, relying on the EC build system to find includes in the driver/tcpm directory. For Zephyr we don't want to add that as an include. It makes more sense for header files to be in an include directory, so move it and fix up the users. BUG=b:175434113 BRANCH=none TEST=build Zephyr and ECOS on volteer Signed-off-by: Simon Glass <sjg@chromium.org> Change-Id: I5851914b1a7d3fdc1ba911c0fbe9046afbaf6f5d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2597985 Reviewed-by: Keith Short <keithshort@chromium.org>
* Cleanup: rename function nameRuibin Chang2020-12-211-2/+2
| | | | | | | | | | | | | | | | | Rename function name from it83xx_* to it8xxx2_* for it8xxx2 driver. Rename function name from *_tcpm_sw_reset to *_tcpm_hook_disconnect. BUG=none BRANCH=none TEST=make BOARD=drawcia -j make BOARD=asurada -j Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw> Change-Id: I8111ec5b9972d1badae625e87248c62e99eabbf6 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2598298 Tested-by: Ruibin Chang <Ruibin.Chang@ite.com.tw> Reviewed-by: Eric Yilun Lin <yllin@chromium.org> Commit-Queue: Ruibin Chang <Ruibin.Chang@ite.com.tw>
* it8xxx2: enable ILM0Dino Li2020-12-174-0/+45
| | | | | | | | | | | | | | | | | | This change enable ILM0 for it8xxx2 series, so we can pull more code into static cache to save latency of fetching code from flash. BUG=b:171172053 BRANCH=none TEST=Check timestamp of "Inits done" on asurada: Before the change was made, we got the timestamp is: [0.004408 Inits done] With this change, the timestamp is changed to: [0.003843 Inits done] Change-Id: Ie7a241bed2f926fd0034cecaf5d8e8183ca16d2e Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2563056 Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* it83xx/flash: workaround of IMMU tag is nds32 onlyDino Li2020-12-171-4/+11
| | | | | | | | | | | | | | This change excluded the workaround from core riscv. BUG=b:111808417 BRANCH=none TEST=On asurada and drawcia, no error while erasing and writing flash of address 0x7e000 ~ 0x7f000 Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Change-Id: If6510b181173862684552607d688b3afb046aa2c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2563356 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* task_set_event: remove the wait argumentDawid Niedzwiecki2020-12-143-6/+5
| | | | | | | | | | | | | | | | | | | | There is an option in the task_set_event function which force the calling task to wait for an event. However, the option is never used thus remove it. This also will help in the Zephyr migration process. BUG=b:172360521 BRANCH=none TEST=make buildall Signed-off-by: Dawid Niedzwiecki <dn@semihalf.com> Change-Id: Ic152fd3d6862d487bcc0024c48d136556c0b81bc Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2521599 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Tom Hughes <tomhughes@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
* COIL: Standardize i2c peripheral languageDossym Nurmukhanov2020-12-124-86/+85
| | | | | | | | | | | BUG=none TEST=validate volteer build (i2c_peripheral.c is not used by any boards) BRANCH=none Signed-off-by: dossym@chromium.org Change-Id: Ib2d78dc3fc9f4f189f84409cf43ab96788c429be Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2587227 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* COIL: Rename i2c_peripheral filesDossym Nurmukhanov2020-12-122-2/+2
| | | | | | | | | | | | BUG=none TEST=build and run on volteer BRANCH=none Signed-off-by: dossym@chromium.org Change-Id: I11a75e4954e918b2d4ff575dee14dec621a619b3 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2587226 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* it83xx/i2c: adjust Tlow and Thigh of 400kHz clockDino Li2020-11-251-2/+2
| | | | | | | | | | | | | | | | This CL increased clock's Tlow to 1.51 us (1.3 us minimum) and reduced Thigh to 1.087 us (0.6 us minimum). BUG=b:163384683 BRANCH=none TEST=i2c clock meet timing at 400kHz. Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Change-Id: Id62b2370018ba2d41e0dbc715a4c40629260d66b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2557281 Reviewed-by: Diana Z <dzigterman@chromium.org> Reviewed-by: Mike Goodey <mgoodey@google.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* chip/it83xx: move __RAM_CODE_SECTION_NAMETzung-Bi Shih2020-11-202-1/+2
| | | | | | | | | | | | | | | | Moves __RAM_CODE_SECTION_NAME from registers.h to config_chip.h. Or switch.S cannot see the macro. BRANCH=none BUG=none TEST=1. make BOARD=asurada 2. grep __switch_task build/asurada/RW/ec.RW.smap Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Change-Id: I1ef272c2e2181a88e4f53dc3024330a1a26c0688 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2549342 Reviewed-by: Dino Li <Dino.Li@ite.com.tw> Reviewed-by: Diana Z <dzigterman@chromium.org>
* core/riscv-rv32i: move essential code to ram_code only if supportsTzung-Bi Shih2020-11-191-1/+2
| | | | | | | | | | | | | | | | | | Commit "it83xx: pull more functions into __ram_code section" (https://crrev.com/c/2535899) breaks Asurada SCP. It moves some essential code to .ram_code section but only IT8XXX2 family includes .ram_code in linker script. Moves the context switch code to ram_code only if it supports. BRANCH=none BUG=none TEST=make BOARD=asurada_scp && make BOARD=asurada Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Change-Id: I8602f7ef0103282feeddbfe1757f7cf7fb5512dc Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2546722 Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* it83xx: pull more functions into __ram_code sectionDino Li2020-11-181-2/+2
| | | | | | | | | | | | | | | | | | Because we have space in the section, so we pulled more functions into the section. If a function is cached in __ram_code section (static cache), we can save latency of fetching code of the function from flash. (Fetching 64 bytes code from flash takes about 4us latency) BUG=none BRANCH=none TEST=buildall. Asurada and Drawcia are both able to boot to kernel. Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Change-Id: I8b413bd577c4e5b73a5c67018d17955da1ed0c55 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2535899 Reviewed-by: Diana Z <dzigterman@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* COIL: Rename CONFIG_I2C_PERIPHERALDiana Z2020-11-053-7/+7
| | | | | | | | | | | | | Rename CONFIG_I2C_PERIPHERAL and related comments. BRANCH=None BUG=None TEST=make -j buildall Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: I3f148e976f3a4d6a1dc6c58686368c056290d5d4 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2518660 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* COIL: Rename CONFIG_I2C_CONTROLLERDiana Z2020-11-052-2/+2
| | | | | | | | | | | | | Rename CONFIG_I2C_CONTROLLER and related comments. BRANCH=None BUG=None TEST=make -j buildall Signed-off-by: Diana Z <dzigterman@chromium.org> Change-Id: Ied6a1829bf54a5c9a32e6772982a4b8aa31aaf23 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2518659 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* Replace I2C_GET_ADDR with I2C_STRIP_FLAGSYuval Peress2020-11-021-1/+1
| | | | | | | | | | | | | | | | | The new I2C_STRIP_FLAGS macro was added to avoid conflict with Zephyr's macro. This CL performs the migration to that new API. BRANCH=none BUG=b:172067439 TEST=make runtests -j and built for various boards: eve, volteer, arcada_ish, atlas, hatch, kohaku, nocturne, samus, and scarlet Change-Id: I0583b647435db96ec268f186252b367bdc4118a6 Signed-off-by: Yuval Peress <peress@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2511097 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Commit-Queue: Jett Rink <jettrink@chromium.org>
* it83xx/adc: ADC read is successful if valid bit is setDino Li2020-10-301-20/+26
| | | | | | | | | | | | | | | | | | | | | | In task_wait_event_mask(), if task woke up by an event which isn't what we want (events |= __wait_evt(time_remaining_us, TASK_ID_IDLE)), and timeout occurs (time_remaining_us = deadline - get_time().val). EC will post timeout event to task even if the event we want ((eg.TASK_EVENT_ADC_DONE)) has been set. We fix this symptom with checking data valid bit of ADC's register. So we won't miss ADC read. BUG=b:171731189 BRANCH=none TEST=No ADC read error on RunInStressCountdown Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Change-Id: I56b301a0f58b64833ae17e2b6e789c879e48cc5c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2501091 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* it83xx/spi: clean up unnecessary configurationtim2020-10-282-76/+36
| | | | | | | | | | | | | | | Rx valid length interrupt has been set as default, so the configuration of IT83XX_SPI_RX_VALID_INT can be removed. BUG=none BRANCH=none TEST=Boot to kernel on HAYATO and no error on the transaction of host command with EC. Change-Id: I92ab78b3e821f566053c816f51bf609394f3b199 Signed-off-by: tim <tim2.lin@ite.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2497366 Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* it83xx: add support for IT81202BX and IT81302BXDino Li2020-10-281-2/+4
| | | | | | | | | | | | | | | | | | | | This CL applies A version's configurations to B version. They have the same HW except for new added function (eg. SPI emulate eMMC "Alternative Boot Mode") on B version. We can add new chip config option for B version in other CL if needed. BUG=none BRANCH=none TEST=Building asurada's EC image with selecting BX chip variant. Flashing the image into reworked asurada (change EC to IT81202BX) and boot to kernel. Signed-off-by: Dino Li <Dino.Li@ite.com.tw> Change-Id: I796a622df21842998ad8f808bfa189b924710649 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2501802 Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
* it83xx/espi: re-enable port80 after espi resetRuibin Chang2020-10-161-0/+6
| | | | | | | | | | | | | | | | | | Our HW design is that Vcc on->off transition will disable port80. Once we reset espi module, then Vcc has on -> off transition and this cause port80 disabled. I re-enable port80 after espi reset. BUG=b:163100497 BRANCH=none TEST=On drawcia, check port80 values and SPCTRL1 register (= 0xc2) after "reboot" and "power on" reset Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw> Change-Id: I2c6b0542cf08bee324e38886d1ce5909cd0b3776 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2479442 Tested-by: Ruibin Chang <Ruibin.Chang@ite.com.tw> Tested-by: Divagar Mohandass <divagar.mohandass@intel.com> Reviewed-by: Diana Z <dzigterman@chromium.org>
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