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* ish: Trim down the release branchstabilize-wristpin-14469.59.B-ishstabilize-voshyr-14637.B-ishstabilize-quickfix-14695.187.B-ishstabilize-quickfix-14695.124.B-ishstabilize-quickfix-14526.91.B-ishstabilize-14695.85.B-ishstabilize-14695.107.B-ishstabilize-14682.B-ishstabilize-14633.B-ishstabilize-14616.B-ishstabilize-14589.B-ishstabilize-14588.98.B-ishstabilize-14588.14.B-ishstabilize-14588.123.B-ishstabilize-14536.B-ishstabilize-14532.B-ishstabilize-14528.B-ishstabilize-14526.89.B-ishstabilize-14526.84.B-ishstabilize-14526.73.B-ishstabilize-14526.67.B-ishstabilize-14526.57.B-ishstabilize-14498.B-ishstabilize-14496.B-ishstabilize-14477.B-ishstabilize-14469.9.B-ishstabilize-14469.8.B-ishstabilize-14469.58.B-ishstabilize-14469.41.B-ishstabilize-14442.B-ishstabilize-14438.B-ishstabilize-14411.B-ishstabilize-14396.B-ishstabilize-14395.B-ishstabilize-14388.62.B-ishstabilize-14388.61.B-ishstabilize-14388.52.B-ishstabilize-14385.B-ishstabilize-14345.B-ishstabilize-14336.B-ishstabilize-14333.B-ishrelease-R99-14469.B-ishrelease-R98-14388.B-ishrelease-R102-14695.B-ishrelease-R101-14588.B-ishrelease-R100-14526.B-ishfirmware-cherry-14454.B-ishfirmware-brya-14505.B-ishfirmware-brya-14505.71.B-ishfactory-kukui-14374.B-ishfactory-guybrush-14600.B-ishfactory-cherry-14455.B-ishfactory-brya-14517.B-ishJack Rosenthal2021-11-051-293/+0
| | | | | | | | | | | | | | | | | | | | | | In the interest of making long-term branch maintenance incur as little technical debt on us as possible, we should not maintain any files on the branch we are not actually using. This has the added effect of making it extremely clear when merging CLs from the main branch when changes have the possibility to affect us. The follow-on CL adds a convenience script to actually pull updates from the main branch and generate a CL for the update. BUG=b:204206272 BRANCH=ish TEST=make BOARD=arcada_ish && make BOARD=drallion_ish Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I17e4694c38219b5a0823e0a3e55a28d1348f4b18 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3262038 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Tom Hughes <tomhughes@chromium.org>
* include/flash: rename the APIsTim Lin2021-06-091-12/+12
| | | | | | | | | | | | | | | | The names conflict when enabling both Zephyr's flash driver and CONFIG_FLASH_CROS option. Rename all the APIs in include/flash.h BUG=b:187192628 BRANCH=none TEST=make buildall -j4 Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com> Change-Id: If1fd0ea28fa9f5cec1c1daa8f72f63eb7a0e6500 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2931749 Commit-Queue: Keith Short <keithshort@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Denis Brockus <dbrockus@chromium.org>
* Refactor CONFIG_FLASH_SIZE to CONFIG_FLASH_SIZE_BYTESYuval Peress2021-01-151-1/+1
| | | | | | | | | | | | | | | | | | | | | In Zephyr CONFIG_FLASH_SIZE is a Kconfig value that is used throughout. The issue is that the units don't match. In Zephyr the value is in KiB instead of bytes. This refactor simply renames CONFIG_FLASH_SIZE in platform/ec to include the unit (via _BYTES). BRANCH=none BUG=b:174873770 TEST=make buildall be generated by the build instead of per board Signed-off-by: Yuval Peress <peress@chromium.org> Change-Id: I44bf3c7a20fcf62aaa9ae15715be78db4210f384 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2627638 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Hughes <tomhughes@chromium.org> Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
* include: Move RESET_FLAG_* into ec_commands.h as EC_RESET_FLAG_*You-Cheng Syu2019-08-261-2/+2
| | | | | | | | | | | | | | | | | | | | | | | RESET_FLAGS_* are used when setting/reading the field ec_reset_flags of struct ec_response_uptime_info, which is defined in ec_commands.h. So it might be better to put those macros there. To be consistent with the other macros in the file, add "EC_" prefixes to them. BUG=b:109900671,b:118654976 BRANCH=none TEST=make buildall -j Cq-Depend: chrome-internal:1054910, chrome-internal:1054911, chrome-internal:1045539 Change-Id: If72ec25f1b34d8d46b74479fb4cd09252102aafa Signed-off-by: You-Cheng Syu <youcheng@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1520574 Tested-by: Yu-Ping Wu <yupingso@chromium.org> Commit-Ready: Yu-Ping Wu <yupingso@chromium.org> Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org> Reviewed-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* LICENSE: remove unnecessary (c) after CopyrightTom Hughes2019-06-191-1/+1
| | | | | | | | | | | | | | | | Ran the following command: git grep -l 'Copyright (c)' | \ xargs sed -i 's/Copyright (c)/Copyright/g' BRANCH=none BUG=none TEST=make buildall -j Change-Id: I6cc4a0f7e8b30d5b5f97d53c031c299f3e164ca7 Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1663262 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* common: bit change 1 << constants with BIT(constants)Gwendal Grignou2019-03-261-1/+1
| | | | | | | | | | | | | | | | | Mechanical replacement of bit operation where operand is a constant. More bit operation exist, but prone to errors. Reveal a bug in npcx: chip/npcx/system-npcx7.c:114:54: error: conversion from 'long unsigned int' to 'uint8_t' {aka 'volatile unsigned char'} changes value from '16777215' to '255' [-Werror=overflow] BUG=None BRANCH=None TEST=None Change-Id: I006614026143fa180702ac0d1cc2ceb1b3c6eeb0 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1518660 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* cleanup: Remove redundant FLASH_SIZE CONFIGsShawn Nematbakhsh2015-09-161-1/+1
| | | | | | | | | | | | | | | | | | | | Since there is no more concept of a flash region belonging only to the EC, we only need one FLASH_SIZE config, which represents the actual physical size of flash. BRANCH=None BUG=chrome-os-partner:23796 TEST=With entire patch series, on both Samus and Glados: - Verify 'version' EC console command is correct - Verify 'flashrom -p ec -r read.bin' reads back EC image - Verify software sync correctly flashes both EC and PD RW images Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I18a34a943e02c8a029f330f213a8634a2ca418b6 Reviewed-on: https://chromium-review.googlesource.com/297824 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cleanup: Use appropriate image geometry CONFIGsShawn Nematbakhsh2015-05-151-7/+3
| | | | | | | | | | | | | | | | - Use CONFIG_*_MEM when dealing with images in program memory. - Use CONFIG_*_STORAGE when dealing with images on storage. - Use CONFIG_WP when dealing with the entire WP RO region. BUG=chrome-os-partner:39741,chrome-os-partner:23796 TEST=Manual on Cyan with subsequent commit. Verify that FMAP matches actual layout of image. Verify flashrom succeeds flashing + verifying EC image using host command interface. BRANCH=None Change-Id: Iadc02daa89fe3bf07b083ed0f7be2e60702a1867 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/270269
* flash: Add option to move pstate inside RO imageRandall Spangler2015-04-171-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, ECs with internal flash store the write protect state for RO in a separate write/erase block of flash. This is wasteful on chips where there are not many blocks of flash. Add a new CONFIG_FLASH_PSTATE_IN_BANK option which is defined by default. This is the old behavior, for compatibility. (And we're calling it 'bank' because that's what the existing code does, even if the terminology is somewhat etymologically... bankrupt.) If that config is #undef'd, then store the write protect flag directly inside the RO image. This uses only 4 bytes of the RO image, instead of an entire erase block. The magic numbers for the pstate values are chosen such that when protecting RO, bits are only transitioned away from their erased state. Unprotecting RO once it's protected requires reflashing RO; it's no longer possible to 'flashwp disable'. But that's ok, because realistically, the only reason to unprotect RO is if you're about to flash the RO firmware anyway. BUG=chromium:476659 BRANCH=none TEST=Without undefining CONFIG_FLASH_PSTATE_IN_BANK, make sure everything still works on samus and samus_pd. This ensures we didn't break the existing functionality: flashinfo -> no flags flashwp enable flashinfo -> ro_at_boot reboot flashinfo -> ro_at_boot flashwp disable flashinfo -> no flags Then recompile with #undef CONFIG_FLASH_PSTATE_IN_BANK and test: flashinfo -> no flags flashwp enable flashinfo -> ro_at_boot reboot flashinfo -> ro_at_boot flashwp disable -> fails with access denied flashinfo -> ro_at_boot Then reflash to verify that clears the ro_at_boot flag: flashinfo -> no flags Change-Id: Ie794b8cfed2a10c50b0e36dcf185884070b04666 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/266095 Reviewed-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Trybot-Ready: Vincent Palatin <vpalatin@chromium.org>
* Fix incorrect valid and writable flash flagsVic Yang2014-10-151-0/+26
| | | | | | | | | | | | | | | | The valid and writable flags the EC sends back to the AP are incorrect. They are a little bit different on differnt chips, so let's move it to flash physical layer. This is not any causing problem, but we should fix this. BUG=chrome-os-partner:32745 TEST=make buildall BRANCH=samus Change-Id: Ibcda5ae770f5ea02cde094490997a5bc447df88f Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/222661 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cleanup: Remove checkpatch warningsRandall Spangler2013-12-191-3/+3
| | | | | | | | | | | | | | | | This make minor syntactic changes and renames some camel-cased symbols to keep checkpatch from complaining. The goal is to reduce the temptation to use 'repo upload --no-verify'. This is a big furball of find/replace, but no functional changes. BUG=chromium:322144 BRANCH=none TEST=build all boards; pass unit tests Change-Id: I0269b7dd95836ef9a6e33f88c003ab0f24f842a0 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/180495
* lm4: Verify data buffer is aligned for flash writesRandall Spangler2013-11-021-0/+4
| | | | | | | | | | | | | | | | | | | All the current data buffers *are* aligned, but we should check anyway just to avoid unpleasant surprises in the future. This matches what we do on STM32L. On STM32F, we copy a byte at a time so alignment of the source data doesn't matter. BUG=chrome-os-partner:9526 BRANCH=none TEST=manual flasherase 0x20000 0x1000 flashwrite 0x20000 0x200 -> succeeds flashwrite 0x20201 0x200 -> fails Change-Id: Id1a0fd8f6871e1fcdc3f55ec25eea40f33b5214c Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175532 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Define watchdog_reload() to nothing if not CONFIG_WATCHDOGRandall Spangler2013-06-101-8/+8
| | | | | | | | | | | | | | | | | | | Currently, we need to have #ifdefs everywhere watchdog_reload() is called. With this fix we don't. Also don't bother including unused hardware timer watchdog code if the watchdog isn't defined. No change when CONFIG_WATCHDOG is defined (which it is for all normal builds). BUG=chrome-os-partner:20056 BRANCH=none TEST=build all platforms with CONFIG_WATCHDOG commented out in config.h Change-Id: Id3ce33af1a497eda127a4892e13651d9d2534d92 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/58094 Reviewed-by: Simon Glass <sjg@chromium.org>
* slippy/falco: Add back in flash and hiberantion setup codeDuncan Laurie2013-06-031-7/+0
| | | | | | | | | | | | | | | | | | | | These were tested to make sure they are not responsible for bricking boards. The flash code is necessary for software sync, and it is essential to be able to update boards without servo. The hibernate setup code was breaking jumping between images and the passing of data between the images -- needed for SW SYNC but also needed for things like "reboot ap-off". BUG=chrome-os-partner:19366 BRANCH=none TEST=manual: emerge-slippy chromeos-ec, flash+boot, update again via SW Sync Change-Id: Ib1363b353f18b21e0cad3209783e1e0b4ff24e86 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56820
* More low-level flash interface cleanupRandall Spangler2013-05-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Setting at-boot protection always used the same start/range (RO+PSTATE), so no point in passing that to the physical layer as params. flash_dataptr() should take a pointer to const data. No functional changes; just rearranging code. BUG=chrome-os-partner:15613 BRANCH=none TEST=build pit, link, spring - flashinfo -> (no flags) - enable WP (via screw or dut-control) - flashinfo -> wp_gpio_asserted - flashwp enable - flashinfo -> wp_gpio_asserted ro_at_boot - flashwp now - flashinfo -> wp_gpio_asserted ro_at_boot all_now (and possibly ro_now) - flashwp disable -> fails - flashinfo -> wp_gpio_asserted ro_at_boot all_now - reboot ap-off - flashinfo -> wp_gpio_asserted ro_at_boot ro_now - disable WP (via screw or dut-control) - reboot - flashinfo -> ro_at_boot - flashwp disable - flashinfo -> (no flags) Change-Id: Ifd6553dc907fa6fafce81b56af0c648ac6d6bee1 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56628
* Move flash_get_protect() and flash_set_protect() to flash_common.cRandall Spangler2013-05-241-82/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Much more flash code is now common between platforms, for more consistent behavior and easier testing. Also change STM32L to use pstate, the same way LM4 and STM32F do. BUG=chrome-os-partner:15613 BRANCH=none TEST=build pit, link, spring; do - flashinfo -> (no flags) - enable WP (via screw or dut-control) - flashinfo -> wp_gpio_asserted - flashwp enable - flashinfo -> wp_gpio_asserted ro_at_boot - flashwp now - flashinfo -> wp_gpio_asserted ro_at_boot all_now (and possibly ro_now) - flashwp disable -> fails - flashinfo -> wp_gpio_asserted ro_at_boot all_now - reboot ap-off - flashinfo -> wp_gpio_asserted ro_at_boot ro_now - disable WP (via screw or dut-control) - reboot - flashinfo -> ro_at_boot - flashwp disable - flashinfo -> (no flags) Change-Id: Iccd098786454ad9b72b4e5f9f312d86819a0c8eb Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56109
* Move write protect GPIO handling to flash moduleRandall Spangler2013-05-231-4/+8
| | | | | | | | | | | | | | | | | Write protect signal naming is now consistent across boards. New CONFIG_WP_ACTIVE_HIGH is present on systems where the write protect signal is active-high (e.g. Link). This will be used in the next CL, which moves flash_get_protect() to flash_common.c BUG=chrome-os-partner:15613 BRANCH=none TEST=flashinfo properly reports WP signal status Change-Id: I502ab033c3eb36661cc3ee97320874b3fbf6fc0d Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56087 Reviewed-by: Vic Yang <victoryang@chromium.org>
* Move flash persistent state to flash_commonRandall Spangler2013-05-231-116/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Persistent state is needed by all platforms to hold the protect-ro-at-boot flag. STM32F100 and LM4 implementations were near-identical, and are now common code (with one #ifdef to handle the single place where they weren't). STM32L doesn't use pstate yet, but it'll need to. I can't simply store the protect-ro-at-boot flag inside the WRP registers themselves because they're still writable in EC-RW. The change to STM32L to use pstate is coming next. BUG=chrome-os-partner:15613 BRANCH=none TEST=build pit, link, spring; on link and spring, do - flashinfo -> (no flags) - enable WP (via screw or dut-control) - flashinfo -> wp_gpio_asserted - flashwp enable - flashinfo -> wp_gpio_asserted ro_at_boot - flashwp now - flashinfo -> wp_gpio_asserted ro_at_boot all_now (and possibly ro_now) - flashwp disable -> fails - flashinfo -> wp_gpio_asserted ro_at_boot all_now - reboot ap-off - flashinfo -> wp_gpio_asserted ro_at_boot ro_now - disable WP (via screw or dut-control) - reboot - flashinfo -> ro_at_boot - flashwp disable - flashinfo -> (no flags) (Note that on Spring you'll need to 'forceen on' before enabling WP, or the console will be disabled once you enable ro_at_boot and reboot.) Change-Id: I415388b98ec8bf1d149803aaaa7fe8c7f3076c36 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/56064
* Create board configuration for falco bringupBill Richardson2013-05-201-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | This change just copies slippy and tweaks a few things that were slippy-specific instead of not-link-specific (there are still bugs open for those things). BUG=chrome-os-partner:18788 BRANCH=none TEST=manual Since there are no Falco-specific changes yet (just slippy with another name), I can try it on Slippy: cros_workon --board falco start chromeos-ec emerge-falco chromeos-ec ~/trunk/src/platform/ec/util/flash_ec --board falco I also built and tested Link EC, to make sure nothing broke there either. Change-Id: I9b3682032bd51adab4450520dfe52e3036750ef9 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/55820 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Fix detecting inconsistent flash stateRandall Spangler2013-05-171-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the last bank of flash in a region was protected and the rest of the region was unprotected, flash_get_protect() shoud return the INCONSISTENT flag, but this wasn't being properly detected. Port the existing fix from STM32F. BUG=chrome-os-partner:19529 BRANCH=none (not likely worth porting to link) TEST=protect just the last bank of RW firmware, then flashinfo > flashinfo Physical: 128 KB Usable: 128 KB Write: 64 B Erase: 256 B Protect: 4096 B Flags: all_now INCONSISTENT Protected now: ........ ........ ........ .......Y Should have the inconsistent flag set. Change-Id: I407737cef42748da6b3ec40d84968c76ee07972c Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/51498 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Slippy: Changes needed to boot EC without bricking.Bill Richardson2013-05-101-0/+7
| | | | | | | | | | | | | | | | This commits the hacks made during board bringup. Bugs can be filed and fixed based on this starting point. BUG=chrome-os-partner:18825 BRANCH=slippy TEST=manual Try it and see. Change-Id: Ia663eaf9a357633873b1b5d5cc6dbdda63513082 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/50875 Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* Replace generated CONFIG_TASK_ macros with HAS_TASK_Bill Richardson2013-04-241-1/+1
| | | | | | | | | | | | | | | CONFIG_ macros should be set directly. Expanding the task names in the same way made it difficult to tell what was a configuration choice and what was due to changes in ec.tasklist BUG=chrome-os-partner:18343 TEST=build all, run link BRANCH=none Change-Id: Ib82e34f974238ee2dd216f33b701b6f4c6a4f1f1 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/49098 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Add more paranoia for flash write protectRandall Spangler2012-12-101-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the entire flash is protected (as it normally is after software sync), fail all flash write/erase operations. Add a shadow copy of the all_now flag. BUG=chrome-os-partner:16727 BRANCH=link TEST=manual Verify that flash operations work properly before all_now. Then enable HW WP and flashwp enable flashwp now and try flasherase 0x38000 0x1000 flashwrite 0x38000 0x100 Those commands should fail with error 7 From the host side ectool flasherase 0x38000 0x1000 echo 'Khaaaaaaaaaaan' > /tmp/b16727 ectool flashwrite 0x38000 /tmp/b16727 should also fail. Change-Id: I99a4d2bb86080bd12c900582a8fbdfc79c99916c Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/39517 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Watchdog is reloaded by HOOK_TICK, not its own taskRandall Spangler2012-10-301-2/+2
| | | | | | | | | | | | | This reduces memory footprint. BUG=chrome-os-partner:15714 BRANCH=none TEST=system still boots; 'waitms 1500' prints watchdog error dump Change-Id: Ieb0248a34655514b03d919cc36c2b369691da716 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/36937 Reviewed-by: Simon Glass <sjg@chromium.org>
* Rename power_button module to switchRandall Spangler2012-10-301-3/+3
| | | | | | | | | | | | | | | Since it handles not just power button, but also lid switch, AC detect, and other switches. No functional changes; just renaming. BUG=chrome-os-partner:15579 BRANCH=none TEST=boot system, power on/off with power button Change-Id: I51628a52293f7207715f5f6bf368a08fe6c3dbce Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/36821
* Use SECOND and MSEC constantsRandall Spangler2012-10-291-2/+2
| | | | | | | | | | | | | | | | | | We'd defined them in a number of different files. This moves definitions to timer.h, and uses them everywhere we have large delays (since 10*SECOND is less typo-prone than 10000000). Also add msleep() and sleep() inline functions. No need for mdelay() or delay(), since any delays that long should use sleep funcs instead of spin-waiting. BUG=chrome-os-partner:15579 BRANCH=none TEST=boot system; taskinfo displays similar numbers to before Change-Id: I2a92a9f10f46b6b7b6571759b1f8ab4ecfbf8259 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/36726
* Cleanup: flash moduleRandall Spangler2012-10-251-14/+15
| | | | | | | | | | | | | No functional changes; just clean up comments and remove dead code BUG=chrome-os-partner:15579 BRANCH=none TEST=code compiles Change-Id: Id006ae18f2b26cea1720196f696f937811b6ba5b Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/36448 Reviewed-by: Simon Glass <sjg@chromium.org>
* Rename EC_FLASH_PROTECT_RW_* flags to EC_FLASH_PROTECT_ALL_*.Louis Yung-Chieh Lo2012-08-251-4/+8
| | | | | | | | | | | | | | | | | | | | Current *_RW_NOW/RW_AT_BOOT is used to lock the entire flash. This could lead confusion in the future. So, rename them. Since the bit definition is unchanged, thus the callers (u-boot, flashrom) is fine if they don't change the name. BUG=chrome-os-partner:12951 BRANCH=snow,link TEST=build in chroot only:daisy,snow,link,bds Signed-off-by: Louis Yung-Chieh Lo <yjlou@chromium.org> Change-Id: I2395e93793f590e6fb8aae7006eb8e5c836002bc Reviewed-on: https://gerrit.chromium.org/gerrit/31199 Commit-Ready: Yung-Chieh Lo <yjlou@chromium.org> Reviewed-by: Yung-Chieh Lo <yjlou@chromium.org> Tested-by: Yung-Chieh Lo <yjlou@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* flash: Only erase flash block that contain dataSimon Glass2012-08-231-4/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It wastes time to erase blocks that are already erased and it is faster on stm32 to check first. Add a check in flash_physical_erase() on all chips, using a common flash_is_erased() function. BUG=none BRANCH=snow,link TEST=manual Do software sync in U-Boot and see that it succeeds. This tests that we can still erase and then boot a written image. It typically saves a second on a full sync over i2c. SMDK5250 # cros_test swsync -f SF: Detected W25Q32 with page size 4 KiB, total 4 MiB Flashing RW EC image: erasing, writing, done Flashing RO EC image: erasing, writing, done Full software sync completed in 22.949s SMDK5250 # Also see that second erase is faster: SMDK5250 # time mkbp erase rw time: 0.952 seconds, 952 ticks SMDK5250 # time mkbp erase rw time: 0.054 seconds, 54 ticks SMDK5250 # Change-Id: I3699577217fdbb2f212d20d150d3ca15fdff03eb Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/30851 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Don't protect firmware now if protect-ro-at-boot is not setRandall Spangler2012-07-251-2/+6
| | | | | | | | | | | | | | | Otherwise, EC software sync protects the entire firmware except in recovery mode, regardless of the WP pin. BUG=chrome-os-partner:11847 TEST=boot with WP enabled but RO-at-boot disabled; flashinfo should show entire flash still writable CQ-DEPEND=28444 Change-Id: I58d60adfaa952b127e8695213f95f6da0e34821d Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/28445 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Refactor flash moduleRandall Spangler2012-07-231-20/+232
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a significant rewrite of the flash module, since it turns out that much less of the flash logic is actually common between stm32 and lm4. BUG=chrome-os-partner:11699 TEST=on link, (enable hardware wp) flashinfo -> wp_gpio_asserted flashwp enable flashinfo -> wp_gpio_asserted ro_at_boot reboot flashinfo -> wp_gpio_asserted ro_at_boot ro_now flashwp disable -> error 7 flashwp now flashinfo -> wp_gpio_asserted ro_at_boot ro_now rw_now reboot flashinfo -> wp_gpio_asserted ro_at_boot ro_now (disable hardware wp) reboot flashinfo -> ro_at_boot flashwp disable flashinfo -> (no flags) Change-Id: If22b02373946ce1c080d49ccded4f8fa3e380115 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/28200 Reviewed-by: Vic Yang <victoryang@chromium.org>
* Use config values for flash protect/erase/write sizesRandall Spangler2012-07-181-23/+4
| | | | | | | | | | | | Since they're config values anyway. Gets rid of an unneeded layer of function call. BUG=chrome-os-partner:11150 TEST=build link, snow, daisy; flashinfo returns same values Change-Id: I27fa007f64a446f1ec0fe22ae16c5c1ac667f8e9 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/27797
* Remove flash_read()Randall Spangler2012-07-181-17/+4
| | | | | | | | | | | | | | | | | | | Everything now uses flash_dataptr() to get at flash memory rather than calling the read function, since the read function adds a needless memcpy(). BUG=chrome-os-partner:11150 TEST=manual flashwp enable reboot flashinfo -> should show ro_at_boot flashwp disable reboot flashinfo -> should no longer show ro_at_boot Change-Id: I1830e2f036cf6777115c782c1737335ff2eb4ce0 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/27796
* Simplify flash protection, part 1Randall Spangler2012-07-181-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | 1. If the flash protection state is locked, RO firmware is explicitly locked. 2. Protecting flash now locks the entire flash. BUG=chrome-os-partner:11150 TEST=manual flashinfo -> nothing protected flashwp now flashinfo -> unlocked,applied; everything protected reboot flashinfo -> nothing protected flashwp lock -> flashinfo -> locked,applied; now has 40 Y's at start and 1 at end reboot flashinfo -> locked,applied; now has 40 Y's at start and 1 at end remove WP screw reboot flashinfo -> locked, not applied; nothing protected flashwp unlock flashinfo -> nothing protected Change-Id: I2cf0e8bfe82ab7a5bf88b9161b7a05b889cae71a Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/27717
* Flash pre-init reboots if it needs to clear protection registersRandall Spangler2012-07-161-0/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BUG=chrome-os-partner:11171 TEST=manual 1. Clear some of the writable-bits in the flash registers > ww 0x400fe40c 0xffff1234 write 0x400fe40c = 0xffff1234 > rw 0x400fe40c read 0x400fe40c = 0xffff1234 2. Reset using power+refresh 3. Register should be clear again > rw 0x400fe40c read 0x400fe40c = 0xffffffff 4. Sysinfo should indicate reset-pin reason AND hard-reset reason > sysinfo Reset flags: 0x0000000a (reset-pin power-on) 5. Reset using power+refresh 6. Sysinfo should indicate reset-pin reason only > sysinfo Reset flags: 0x00000002 (reset-pin) 7. Clear writable-bits again > ww 0x400fe40c 0xffff1234 write 0x400fe40c = 0xffff1234 8. Jump to another image. This should NOT trigger a hard reset. > sysjump A > sysinfo Reset flags: 0x00000402 (reset-pin sysjump) Change-Id: Ie1d6af2acc68217bb82faae464798ee85d63d1ea Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/27540 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Remove unused uart.h includesRandall Spangler2012-04-251-1/+0
| | | | | | | | | Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=none TEST=none Change-Id: I8f9c6e67427a5c7f2c42754b421db44504f9c10d
* Add timeout for flash operations.Randall Spangler2012-04-121-5/+19
| | | | | | | | | | | | | | | Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:7479 TEST=manual. From the linux console, ectool reboot_ec RO ectool flashread 81920 163840 /tmp/ec.bin ectool flasherase 163840 81920 ectool flashwrite 81920 /tmp/ec.bin ectool reboot_ec A Change-Id: I850f4cea5dfdb76cfe3957988b10cf8841de55c1
* Reload watchdog timer during flash operations.Randall Spangler2012-04-121-1/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:8967 TEST=manual While ssh'd into the device: 1) Create a test image: Extracting to: /tmp/ecup 132+1 records in 132+1 records out 136132 bytes (136 kB) copied, 0.000550122 s, 247 MB/s 2) Force the EC into its RO image: done. 3) Erase the A and B images, then reprogram them: Erasing 163840 bytes at offset 81920... done. Reading 136132 bytes from /home/chronos/user/ecb.bin... Writing to offset 81920... done. 4) Repeat step 3 about 10 times while monitoring the EC debug console. Commands should complete successfully all the time. (Note that during the flashwrite, there's a ton of debug output; what you should NOT see is something like this: WATCHDOG PC=00002104 / LR=0000597f / pSP=200013a0 Change-Id: I2f1f05eb19abcd6e19c6364f6d4ac785cca6a4c6
* Implement persistent flash write protect settingsRandall Spangler2012-04-021-177/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This uses the last bank of flash to hold persistent settings, and looks at the write protect GPIO to decide whether to protect the chip at boot (chrome-os-partner:7453). For ease of debugging, I've temporarily hacked this so flash uses the RECOVERYn signal (dut-control goog_rec_mode:on) to enable WP instead of the write protect signal; this works around chrome-os-partner:8580. Also note that if you write protect any blocks even temporarily, you'll need to do a power-on reset to clear them before you can reprogram the flash. See chrome-os-partner:8632. At the EC console, "hibernate 1" will do that, or you can just yank the power. This also fixes a bug in the flash write and erase commands, where they weren't properly detecting failure if you attempted to modify a protected block (missed an interrupt reason...) New "flashwp" console commands work. LPC commands need reworking. Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:8448 TEST=manual Change-Id: I49c38cc25c793094ae3331a4586fda0761b4bac6
* More cleanup of board/chip configs and initializationRandall Spangler2012-03-191-1/+1
| | | | | | | | | | | | | | | | | More modules can be disabled individually through CONFIG_ defines. Reordered early module pre-init and init, and added comments to explain why things are ordered in main() the way they are. Fixed a few assorted init-related bugs along the way, like st32m keyboard scan double-initializing. BUG=none TEST=build link, bds, daisy Signed-off-by: Randall Spangler <rspangler@chromium.org> Change-Id: I04a7fa51d743adfab4be4bdddaeef68943b96dec
* Make all warnings into errors.Bill Richardson2012-02-271-9/+8
| | | | | | | | | Also fix a couple places where that makes it fail. BUG=none TEST=none Change-Id: I3b434b4bfa547a579193aac67c1a9d440a2c4e51
* Clean up labels and TODOsRandall Spangler2012-01-101-12/+15
| | | | | | | | | Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=none TEST=none Change-Id: I8d6e99b3e2b60d32ea3719468590b055e692a67e
* Add flash write protect range commandRong Chang2011-12-121-4/+122
| | | | | | | | | | | This CL add host command to enable, get/set flash write protect range. BUG=None TEST=Use flashrom utility to set write protect range, enable write protect and get status. Change-Id: I345f1eb65944d8cf8028e6fdb7e43c40cc742a6d Signed-off-by: Rong Chang <rongchang@chromium.org>
* Initial sources import 1/3Randall Spangler2011-12-071-0/+183
source files mainly done by Randall. Signed-off-by: Randall Spangler <rspangler@chromium.org> Change-Id: Iaff83a842b17f3350fb6f2a3f1597ad4c29bd12a
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