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* main: Initialize I2C pretty earlyAlexandru M Stan2019-10-241-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Some devices (like the keyboard, CBI) need I2C access pretty early. Until now I2C would get initialized pretty late in a hook, which was far too late for some stuff. As a result from this change, CONFIG_I2C_MASTER now implies the i2c_init() function will be called at board boot. Some chips (cr50, host tests) needed a stub i2c_init in order to compile cleanly. BUG=b/138384267 TEST=EFS doesn't happen significantly later than it used to TEST=Recovery keys now work with I2C keyboard on jacuzzi TEST=make buildall TEST=Sanity check i2c behavior (booting, "i2scan", "battery") on a variety of ECs: * ampton (ite EC, x86 AP) * bobba (npcx EC, x86 AP) * jacuzzi (stm32f0 EC, ARM AP) * cheza (npcx EC, ARM AP) BRANCH=master Change-Id: Ifa830e8e509ff16b36b4dcc86617869b1cb86ac3 Signed-off-by: Alexandru M Stan <amstan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1772490 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* include: De-longify BIT() macroEvan Green2019-10-051-1/+1
| | | | | | | | | | | | | | | | | | | | | | | The BIT() macro was recently introduced to make things more comfortable to upstream Linux. However, there's no need for it to be a long. Change the macro back to being an int (int and long are the same on 32-bit platforms, which all of our ECs are), so that we can reduce the number of %l specifiers. The semantics of %l have changed, we are deprecating its use on master to reduce the risk that we accidentally cherry-pick one of those printfs to an old firmware branch. BUG=chromium:984041 TEST=make -j buildall BRANCH=None Change-Id: I95b9cd49895cc67998dcb1de9bab5b5591d93243 Signed-off-by: Evan Green <evgreen@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1834601 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: caveh jalali <caveh@chromium.org>
* printf: Fix formatting errorsEvan Green2019-10-051-1/+1
| | | | | | | | | | | | | | | | | | | This change fixes the printf formatting errors found by the compile-time prinf format checker. The errors fall into a few categories: 1. Incorrect size specifier (missing or extra l). 2. Missing or extra arguments. 3. Bad line splitting. BUG=chromium:984041 TEST=make -j buildall BRANCH=none Change-Id: I5618097a581210b9fcbfc81560dec050ae30b61c Signed-off-by: Evan Green <evgreen@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1819653 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* Remove __7b, __8b and __7bfDenis Brockus2019-07-201-3/+3
| | | | | | | | | | | | | | | | | | | The extentions were added to make the compiler perform most of the verification that the conversion was being done correctly to remove 8bit addressing as the standard I2C/SPI address type. Now that the compiler has verified the code, the extra extentions are being removed BUG=chromium:971296 BRANCH=none TEST=make buildall -j TEST=verify sensor functionality on arcada_ish Change-Id: I36894f8bb9daefb5b31b5e91577708f6f9af2a4f Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1704792 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* Use 7bit I2C/SPI slave addresses in ECDenis Brockus2019-07-191-7/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Opt for 7bit slave addresses in EC code. If 8bit is expected by a driver, make it local and show this in the naming. Use __7b, __7bf and __8b as name extensions for i2c/spi addresses used in the EC codebase. __7b indicates a 7bit address by itself. __7bf indicates a 7bit address with optional flags attached. __8b indicates a 8bit address by itself. Allow space for 10bit addresses, even though this is not currently being used by any of our attached devices. These extensions are for verification purposes only and will be removed in the last pass of this ticket. I want to make sure the variable names reflect the type to help eliminate future 7/8/7-flags confusion. BUG=chromium:971296 BRANCH=none TEST=make buildall -j Change-Id: I2fc3d1b52ce76184492b2aaff3060f486ca45f45 Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1699893 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* LICENSE: remove unnecessary (c) after CopyrightTom Hughes2019-06-191-1/+1
| | | | | | | | | | | | | | | | Ran the following command: git grep -l 'Copyright (c)' | \ xargs sed -i 's/Copyright (c)/Copyright/g' BRANCH=none BUG=none TEST=make buildall -j Change-Id: I6cc4a0f7e8b30d5b5f97d53c031c299f3e164ca7 Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1663262 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* common: bit change 1 << constants with BIT(constants)Gwendal Grignou2019-03-261-2/+2
| | | | | | | | | | | | | | | | | Mechanical replacement of bit operation where operand is a constant. More bit operation exist, but prone to errors. Reveal a bug in npcx: chip/npcx/system-npcx7.c:114:54: error: conversion from 'long unsigned int' to 'uint8_t' {aka 'volatile unsigned char'} changes value from '16777215' to '255' [-Werror=overflow] BUG=None BRANCH=None TEST=None Change-Id: I006614026143fa180702ac0d1cc2ceb1b3c6eeb0 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1518660 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* common: replace 1 << digits, with BIT(digits)Gwendal Grignou2019-03-261-15/+15
| | | | | | | | | | | | | | | | Requested for linux integration, use BIT instead of 1 << First step replace bit operation with operand containing only digits. Fix an error in motion_lid try to set bit 31 of a signed integer. BUG=None BRANCH=None TEST=compile Change-Id: Ie843611f2f68e241f0f40d4067f7ade726951d29 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1518659 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* common: adc/i2c: Mark task_waiting volatileShamile Khan2015-12-011-1/+1
| | | | | | | | | | | | | | | | | | | When Link Time Optimization is turned on, functions that set task_waiting multiple times have one of the sets removed by the linker leading to undesired results. Marking task_waiting volatile alleviates this issue. BUG=chrome-os-partner:46063 TEST=Manually tested on Kunimitsu. Console command adc shows correct value of approx 20000 mV for VBUS. BRANCH=none Change-Id: I85a6e5c9688ae72c45d90fb58296f94b74a301aa Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/314233 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* mec1322: Implement i2c_set_timeoutShawn Nematbakhsh2015-06-031-3/+0
| | | | | | | | | | | | | Allow timeout to be set at runtime by controller. BUG=chrome-os-partner:40780 TEST=Manual on Glados. Verify PD I2C communication is functional. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I582e47c7bebfed7a639789c90064d86ffe1a5401 Reviewed-on: https://chromium-review.googlesource.com/274967 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* i2c: Make i2c_xfer a wrapper function to chip_i2c_xferShawn Nematbakhsh2015-05-271-4/+4
| | | | | | | | | | | | | | | | i2c_xfer was previously implemented at the chip-level, but now we want to add some global retry logic. Rename the chip-level i2c_xfer functions to chip_i2c_xfer and add a new global wrapper function i2c_xfer. BUG=chrome-os-partner:39613 TEST=Run "battery" from EC console on Cyan, verify that values + strings are correctly printed. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: If37c85cc3cf94fd53feb6931553e10c30ad6cad6 Reviewed-on: https://chromium-review.googlesource.com/272939 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* i2c: Move i2c_read_string to common codeShawn Nematbakhsh2015-05-261-30/+0
| | | | | | | | | | | | | | | | | Since stm32 and mec1322 now support open-ended i2c_xfer, we can move the lm4 i2c_read_string implementation to common code and delete all chip-specific versions. BUG=chrome-os-partner:39613 TEST=Run "battery" from EC console on Cyan and Oak, verify that battery info + strings are correctly printed. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I06369df64bb2eb747d163664b4c96eeacb4b1faa Reviewed-on: https://chromium-review.googlesource.com/272938 Reviewed-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* I2C: Increase priority of i2c_initAlexandru M Stan2015-01-161-1/+1
| | | | | | | | | | | | | | | | Chipset sometimes needs I2C, therefore i2c_init should have a higher priority than power_common_init so i2c is available by the time the chipset might be talking to the battery. BUG=chrome-os-partner:35502, chrome-os-partner:35173 TEST=There is no "battery not responding" message at startup on veyron TEST=EC boot takes less than 1 second on veyron BRANCH=none Change-Id: Ib10b653decc7703e706d4dd1976abf0fdbc25ac2 Signed-off-by: Alexandru M Stan <amstan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/241102 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* EC: Add smbus interface read & write APIsSheng-Liang Song2014-08-291-0/+5
| | | | | | | | | | | | | | | | | | Ref: http://smbus.org/specs/smbus20.pdf - Support software CRC8 generation and checking. - Support read/write word (2-bytes) - Support read/write blocks (up to 32 bytes) BUG=chrome-os-partner:24741 BRANCH=ToT,glimmer TEST=Verified with smart battery firmware update application on glimmer. Passed LGC & Simplo Battery. Change-Id: Ic2e7f759af80c06741ed49fee1826213429fbf8a Signed-off-by: Sheng-Liang Song <ssl@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/209747 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* lm4 i2c: fixed lm4 i2c_xfer synchronization issueSheng-Liang Song2014-08-261-3/+6
| | | | | | | | | | | | | | Added atomic or/clear when modify a share register LM4_SYSTEM_SRI2C_ADDR among different i2c ports. BUG=None BRANCH=ToT TEST=Verified on Samus. Signed-off-by: Sheng-Liang Song <ssl@chromium.org> Change-Id: Ibf64b05a800ce2b8ddf9735bd3a762ab02031bc8 Reviewed-on: https://chromium-review.googlesource.com/213196 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* i2c: add support for timeout configuration at runtimeRandall Spangler2014-07-301-3/+12
| | | | | | | | | | | | | | | | | When the EC sends longer commands to the PD chip (such as flash erase/write over the passthru from AP), allow it to take a second instead of the default 100ms timeout. BUG=chrome-os-partner:30935 BRANCH=none TEST=samus boots battery command works from EC console ectool passthru of flash erase to PD works (requires hacked ectool) Change-Id: I08ff94f7ac6aee351aa73c9d28b5fd715d463b3a Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/209936 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* lm4: decrease i2c timeoutAlec Berg2014-06-041-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The i2c timeout on lm4 is currently 1 second, which is very long. This changes it to 100ms. Note, the biggest transfer we might every do is probably ~256 bytes to do a flash program using a host command over i2c. And the slowest bus speed is ~100kHz. So, worst case, the transaction shouldn't be more than about 25ms. Decreasing the timeout is useful when peripherals are not plugged in. For example, the ALS is sampled in the hooks task every second. We don't want the ALS sampling to be delayed for a second because it will throw off all of our other hooks. BUG=chrome-os-partner:29003 BRANCH=none TEST=ran on a samus and tested i2c commands to various peripherals Change-Id: I5e1b6d0f8b100cbcb6cd9209c6198e31d99bb085 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/202515 Reviewed-by: Bill Richardson <wfrichar@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Add cprints() and ccprints()Vic Yang2014-05-211-3/+3
| | | | | | | | | | | | | | | | | | | | | Our code base contains a lot of debug messages in this pattern: CPRINTF("[%T xxx]\n") or ccprintf("[%T xxx]\n") The strings are taking up spaces in the EC binaries, so let's refactor this by adding cprints() and ccprints(). cprints() is just like cprintf(), except that it adds the brackets and the timestamp. ccprints() is equivalent to cprints(CC_CONSOLE, ...) This saves us hundreds of bytes in EC binaries. BUG=chromium:374575 TEST=Build and check flash size BRANCH=None Change-Id: Ifafe8dc1b80e698b28ed42b70518c7917b49ee51 Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/200490 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* lm4: Update i2c handler to use task_wait_event_maskChromeOS Developer2014-03-261-25/+1
| | | | | | | | | | | BUG=chrome-os-partner:27180 BRANCH=rambi TEST=Verify i2c devices are still working (battery, charger) Change-Id: I9dc70454df35be9c9be3d9020c8dc3b760de5e07 Signed-off-by: Dave Parker <dparker@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/191301 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* force the compiler to use a valid register allocation for irq handlersVincent Palatin2014-03-111-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When we are calling the re-scheduling routine at the end of an irq handling routine, we need to ensure that the high registers are not currently saved on the system stack. On Cortex-M3/M4, the compiler is normally doing tail-call optimization there and behaving properly, but this fixes the fact that insanely large interrupt handling routines where sometimes not compile and not running properly (aka issue 24515). This also prepares for one more core-specific DECLARE_IRQ routine on Cortex-M0. Note: now on, the IRQ handling routines should no longer be "static". Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=chrome-os-partner:24515 TEST=make -j buildall revert the workaround for 24515, see the issue happening only without this CL. Change-Id: Ic419369231925568df05815fd079ed191a5446db Reviewed-on: https://chromium-review.googlesource.com/189153 Reviewed-by: Vic Yang <victoryang@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
* cleanup: Combined i2c unwedge code into one common functionAlec Berg2014-03-061-8/+63
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Refactored the i2c unwedge code to place it in the common directory so that any EC chip can use it. Added to the STM32F and LM4 boards, code to automatically detect and unwedge the i2c bus at the start of an i2c transaction. Note that STM32L already had this ability. To enable unwedging of the i2c port though, the gpio pins for SDA and SCL must be defined in the i2c_ports[] array in the board.c file. This allows the i2c module to bit bang the unwedging for the given port. If SDA and SCL are not defined for the port, then the unwedge code will not run. BUG=chrome-os-partner:26315, chrome-os-partner:23802 BRANCH=none TEST=Manual testing on machines with different EC chips. Testing made extensive use of https://chromium-review.googlesource.com/66389 in order to force wedging of the i2c bus so that we can attempt to unwedge it. Note that you can easily test if the bus is wedged by running i2cscan. On pit and spring: On pit, after each of the following, I verified that the bus was automatically unwedged. On spring, the unwedge only runs at reboot, so, for the non-reboot wedge commands, I manually ran console command unwedge, and verified that the bus became unwedged. (1) Bit bang a transaction but only read part of the response. Command to wedge: i2cwedge 0x90 0 2 2 (2) Bit bang a transaction to do a "write" and stop while the other side is acking. Command to wedge: i2cwedge 0x90 0 1 (3) Same as (1) but do a reboot instead of returning and see that the unwedge works at init time w/ no cancelled transactions. Command to wedge: i2cwedge 0x90 0 6 2 (4) Same as (2) but do a reboot instead of returning and see that the unwedge works at init time w/ no cancelled transactions. Command to wedge: i2cwedge 0x90 0 5 On glimmer: Added code to call i2c_unwedge in accel_init(). Then tested unwedging the accelerometer with the following. One extra difficulty testing this with the accelerometer is that sometimes the bit you stop on is high, which means it won't be wedged at all, the next start transaction will reset the bus. So, sometimes running i2cwedge won't wedge the bus and sometimes it will depending on the acceleration data. (1) Big bang transaction to do a "read" of accelerometer and stop partway: i2cwedge 0x1c 0x0f 2 2 i2cscan to make sure bus is actually wedged i2cunwedge i2cscan to make sure bus is now unwedged. (2) Bit bang transaction to do a "read" and stop partway, then reboot: i2cwedge 0x1c 0x0f 6 2. i2cscan to verify that the bus is working after the reboot. Change-Id: Ie3328e843ffb40f5001c96626fea131c0f9ad9b1 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/188422 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* lm4: move I2C transfer state machine to interrupt handlerRandall Spangler2014-01-161-184/+183
| | | | | | | | | | | | | | | | | | | | | | This significantly decreases the task swapping overhead when doing many transfers. Also fix a bug where on error, i2c_xfer() would issue a stop condition, but not actually wait for it to complete before returning; this could interfere with the next transfer in a back-to-back scenario. BUG=chrome-os-partner:25015 BRANCH=lm4 (more specifically, rambi and derivatives) TEST=battery command should show the same info as before i2cscan should show devices at bus 0 0x12, 0x16, bus 5 0x98 no charger errors on boot Change-Id: I2195f0f9800b03a54fa33170dbae6705382578c7 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182503 Reviewed-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Yung-chieh Lo <yjlou@chromium.org>
* Clean up hook priorties on LM4Randall Spangler2013-11-041-1/+1
| | | | | | | | | | | | | | | | | | | | Fan no longer needs a special priority to wait for the host memmap to become available, since LPC inits earlier. I2C and PECI don't need explicit ordering on freq change. Thermal now uses the explicit prio for temp sensors done. Commented hook test. BUG=chromium:314768 BRANCH=none TEST=boot link; enable/disable PLL; verify fanset and temps commands work afterwards. Change-Id: I71766614dff2950dd307acd0635405e6b59e330a Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175601 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* lm4: Modified clock gating to allow easy expansion to low power.Alec Berg2013-10-101-3/+3
| | | | | | | | | | | | | | | | | | | | | Created a new function to enable or disable clocks to various peripherals. This new function makes it easy to specify if you want the clock enabled in run mode, sleep mode, and/or deep sleep mode. Added infrastructure to specify which GPIOs should interrupt the EC from deep sleep. BUG=none BRANCH=none TEST=Passes all unit tests. Ran on a peppy and verified that the clock gate control registers in run mode (LM4_RCGC regs) were the same before and after this change. Change-Id: Ia5009ac8c837f61dca52fe86ebdeede2e1a7fe4d Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172454 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cleanup: Replace awkward I2C_PORTS_USED macro with constantBill Richardson2013-10-071-5/+5
| | | | | | | | | | | | | | | | | | | | We only used I2C_PORTS_USED to iterate through the list of hardware ports actually in use, but we defined it in board.h at the same place where we matched particular I2C devices to the (possibly shared) buses they're on. This CL makes I2C_PORTS_USED into a global constant, so it can be set automatically where we initialize the ports, and doesn't have to be related to the list of attached devices. BUG=chrome-os-partner:18343 BRANCH=none TEST=manual Build everything, run all tests, should still work. Change-Id: I65f22f5cadfc4b3afe51af48faa5fb369bc3aa09 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/171884
* Clean up configuring GPIO alternate functionsRandall Spangler2013-08-071-25/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | GPIO alternate functions used to be configured throughout the code, which made it hard to tell which ones you needed to configure yourself in board.c. It also sometimes (chip/lm4/i2c.c) led to GPIOs being configured as alternate functions even if they weren't used on a given board. With this change, every board has a table in board.c which lists ALL GPIOs which have alternate functions. This is now the only place where alternate functions are configured. Each module then calls gpio_init_module() to set up its GPIOs. This also fixes a bug where gpio_set_flags() ignored most of the flags passed to it (only direction and level were actually used). On stm32f, gpio_set_alternate() does not exist, and pins are configured via direct register writes from board.c. Rather than attempt to change that in the same CL, I've stubbed out gpio_set_alternate() for stm32f, and will fix the register writes in a follow-up CL. BUG=chrome-os-partner:21618 BRANCH=peppy (fixes I2C1 being initialized even though those pins are used for other things) TEST=boot link, falco, pit, spring Change-Id: I40f47025d8f767e0723c6b40c80413af9ba8deba Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/64400
* Add build-time checks on board-specific array sizes.Bill Richardson2013-07-311-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We've been declaring a bunch of statically-sized arrays: extern struct foo_t foo[FOO_COUNT]; And then initializing them like so: struct foo_t foo[FOO_COUNT] = { /* blah */ }; That only catches cases where we initialize with too many entries. It doesn't catch cases where we haven't initialized enough. This change tests for both cases like so: extern struct foo_t foo[]; struct foo_t foo[] = { /* blah */ }; BUILD_ASSERT(ARRAY_SIZE(foo) == FOO_COUNT); The affected arrays are: adc_channels[ADC_CH_COUNT] gpio_list[GPIO_COUNT] temp_sensors[TEMP_SENSOR_COUNT] x86_signal_list[X86_SIGNAL_COUNT] i2c_ports[I2C_PORTS_USED] BUG=chrome-os-partner:18343 BRANCH=falco,peppy TEST=build all platforms All platforms should still build, all tests should still pass. Change-Id: Ibb16dc3201f32df7cdc875648e89ba4ffb09f733 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/63833 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Change i2c port configs to make BDS the special case, not Link.Bill Richardson2013-06-061-12/+11
| | | | | | | | | | | | | This matches our reference design for the EC's i2c GPIOs. BUG=none BRANCH=none TEST=none Change-Id: I8320b6234e2db8d645d0c4d4e982e3817da9f5e7 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/57809 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Send STOP to clear bus when I2C encounters an error.Bill Richardson2013-06-061-2/+7
| | | | | | | | | | | | | | | | | Reading from a nonexistant/nonresponsive smart battery fails (as it should). But then it leaves the i2c clock line low, so that subsequent i2cscan commands fail too. This change just sends a STOP to clear the bus when an i2c error occurs. BUG=chromium:247037 BRANCH=none TEST=none Change-Id: I599bed7149ed3dd3748f1a939c2ea8fdf65e3d72 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/57808 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Add some ifdefs to distinguish between Link and SlippyBill Richardson2013-05-021-1/+1
| | | | | | | | | | | | | | | I'll still need to decide what to do differently for Slippy, but for now let's just identify the places where there will likely be a difference. BUG=chrome-os-partner:18825 BRANCH=slippy TEST=manual Link still works. Change-Id: I950f0e5356ccf9838f2140d853122235f884e34f Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/49931
* Move i2cread and i2cwrite functions to i2c_commonRandall Spangler2013-04-301-157/+22
| | | | | | | | | | | | | | | | | | | | Also moves the handy i2cscan command to i2c_common. The platform-dependent interface is now i2c_xfer(). Still more to do in follow-up CLs; for example, i2c_read_string() has platform-dependent implementation, and the i2c/i2cread console commands aren't common yet. BUG=chrome-os-partner:18969 BRANCH=none TEST=i2cscan on link, spring Change-Id: Ia53d57beaa157bece293a4262257e20b4107589e Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/49492 Reviewed-by: Simon Glass <sjg@chromium.org> Commit-Queue: Daniel Erat <derat@chromium.org> Commit-Queue: Simon Glass <sjg@chromium.org>
* Handle arbitration lost on I2C portsRandall Spangler2012-11-281-9/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This seems to happen when the I2C signals come up so that the EC sees a start condition from the remote end. In this case, the EC refuses to talk on the I2C port until the EC's I2C state machine is reset. Also, don't fail on bus-busy, since that's true during a multi-part transaction such as an I2C string read. BUG=chrome-os-partner:16262 BRANCH=link TEST=boot system; 'battery' and 'temps' should give good info Then run snanda's suspend_stress_test for a while and repeat. Or a better test is to open 2 crosh shells, sudo bash in each, and 1) while true; do ectool temps all; sleep 0.5; done 2) suspend_stress_test Then watch the EC console for "I2C5 bad status" errors. These happen rarely, only on some systems. With this fix, they'll be reported when they occur, but should not cause errors to be reported by 'ectool temps all', since the I2C module will clear the arbitration-lost status before retrying. Change-Id: Idfaf9cd7e8ef2abcc0130332890329dd5d2ca052 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/38686 Reviewed-by: Yung-Chieh Lo <yjlou@chromium.org>
* Handle bus errors on thermal I2C busRandall Spangler2012-11-261-2/+29
| | | | | | | | | | | | | | | | | | | | | | | | | 1) Properly report I2C errors on TMP006 as error, not device-not-powered. 2) Treat clock timeout and bus-busy I2C status as error (previously ignored). 3) If clock timeout or bus-busy, reset I2C master for that bus to clear the error. These should help with systems where the thermal I2C bus gets into a weird state on suspend/resume. BUG=chrome-os-partner:16262 BRANCH=link TEST=boot system; 'battery' and 'temps' should give good info Then run snanda's suspend_stress_test for a while and repeat. Change-Id: I534be8236a4d6de82575fe6d33a68502ce0a3a95 Original-Change-Id: Iec5d6bbd357d2e5eb3dc3d361c829f353e996ab6 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/38444 Reviewed-on: https://gerrit.chromium.org/gerrit/38659 Reviewed-by: Yung-Chieh Lo <yjlou@chromium.org>
* Use SECOND and MSEC constantsRandall Spangler2012-10-291-1/+1
| | | | | | | | | | | | | | | | | | We'd defined them in a number of different files. This moves definitions to timer.h, and uses them everywhere we have large delays (since 10*SECOND is less typo-prone than 10000000). Also add msleep() and sleep() inline functions. No need for mdelay() or delay(), since any delays that long should use sleep funcs instead of spin-waiting. BUG=chrome-os-partner:15579 BRANCH=none TEST=boot system; taskinfo displays similar numbers to before Change-Id: I2a92a9f10f46b6b7b6571759b1f8ab4ecfbf8259 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/36726
* Clean up I2C moduleRandall Spangler2012-10-251-121/+125
| | | | | | | | | | | | | No functional changes, just cleanup BUG=chrome-os-partner:15579 BRANCH=none TEST=i2cscan; should find all expected devices Change-Id: I8e11d3fa460236e80a0ce1ee923e4413b3202c1e Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/36569 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Hook functions no longer return valuesRandall Spangler2012-10-231-10/+4
| | | | | | | | | | | | | | | Previously, all hook functions returned EC_SUCCESS, which was meaningless because nothing ever looked at the return value. Changing the return value to void saves ~100 bytes of code size and an equal amount of source code size. BUG=none BRANCH=none TEST=code still builds; link still boots Change-Id: I2a636339894e5a804831244967a9c9d134df7d13 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/36372
* Prevent I2C interrupts from consuming pending task eventsBill Richardson2012-09-211-5/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This manifested as the lightbar task missing transitions between CPU states. The underlying cause was that when a task talks over the I2C bus, the I2C communication was using the task scheduler to wait for an interrupt to signal completed I2C traffic without blocking the other threads, but while doing so it was not preserving pending events. This CL seems to fix it. BUG=chrome-os-partner:12431 BRANCH=all TEST=manual The original bug is tricky to reproduce without adding some delay to the I2C task code, but you can do it. Boot the CPU, then from the EC console repeatedly alternate these two commands: lightbar seq s0 lightbar seq s3 You should see the lightbar pattern turn off and on, but occasionally you'll type the command and the EC won't change the pattern. With this change applied, it should *always* work. Change-Id: Ie6819a4a36162a8760455c71c41ab8a468656af1 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/33805 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Clean up debug outputRandall Spangler2012-08-071-1/+1
| | | | | | | | | | | | Should print with [%T prefix BUG=none TEST=if it boots, it works Change-Id: I035c081ae3e8ad0088daf0bba404118e1a1f9b41 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/29480 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Better help for console commandsRandall Spangler2012-05-251-7/+13
| | | | | | | | | | | | | | | | | | | | Additional help messages and usage are gated by CONFIG_CONSOLE_CMDHELP, so we can turn it on if there's space (adds about 3KB to image size) and turn it off when there isn't. Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=none TEST=manual 1) help 2) help list 3) help gpioset 4) gpioset -> wrong number of params 5) gpioset fred 0 -> param1 bad 6) gpioset cpu_prochot fred -> param2 bad Change-Id: Ibe99f37212020f763ebe65a068e6aa83a809a370
* Fix I2C port frequency calculationRandall Spangler2012-05-241-6/+38
| | | | | | | | | | | | | | | | | | Also fix 'i2cscan' output, and detect/ignore busy ports Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:9928 TEST=manual 1) check i2cscan i2cscan -> thermal port should report busy gpioset enable_vs 1 i2cscan -> thermal port should show 4 devices 2) probe EC_SMB_CK[012] signals to verify clock frequency Change-Id: I52e165de77eb9ed2619d648d84f251152772fe1c
* More debug command cleanup to save spaceRandall Spangler2012-05-211-14/+6
| | | | | | | | | | (saves another 1.5KB) BUG=none TEST=(run the commands) Change-Id: Id3ca58528fa68a4cec606edf2b98b9af38ac228f Signed-off-by: Randall Spangler <rspangler@chromium.org>
* Clean up debug commands to use less spaceRandall Spangler2012-05-211-15/+10
| | | | | | | | BUG=none TEST=(run the commands) Change-Id: I6ed4aee169311825190bcc386b86cdc32ba0866a Signed-off-by: Randall Spangler <rspangler@chromium.org>
* Add a list of I2C portsRandall Spangler2012-05-171-23/+22
| | | | | | | | | | | | | | | | | This cleans up I2C init and debug commands across boards. Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=none TEST=on link and bds: i2cscan lightbar run powerbtn (to power on system) temps (to read i2c temp sensors) battery (to read battery) charger (to read charger) Change-Id: If3fb0cdb8d3178592bf68cbb2e72bc4b7f71dec5
* Use console output instead of uart output for console commandsRandall Spangler2012-04-241-15/+14
| | | | | | | | | | | | This completes console output cleanup. The remaining calls to uart_puts() and uart_printf() actually need to be that way. Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:7464 TEST=manual Change-Id: Ib1d6d370d30429017b3d11994894fece75fab6ea
* Added HOOK_INIT for driver module initsRandall Spangler2012-04-191-1/+2
| | | | | | | | | | | | This covers modules which need to initialize before task_start(), but don't particularly care in what order they're initialized. Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=none TEST=if it boots, it works Change-Id: I69829aac8d1c3c14ee04916a794b84bbf03a09eb
* Add hooks module so modules can be notified of system-level events.Randall Spangler2012-04-191-3/+8
| | | | | | | | | | | | This will be used for sleep/wake/sysjump/etc. For now it's just wired up to clock frequency changing. Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=none TEST=manual: use nopll command, should still work Change-Id: Iedcea5830bc18eacfd955c29b8f793aba8905dd8
* Support dynamically changing the system clockRandall Spangler2012-04-091-16/+21
| | | | | | | | | | | | | | | | | | | | | | | Add nopll command to turn off the PLL, reducing the system clock to 16Mhz. Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:8798 TEST=manual boot system press power button to boot x86 temps // should print all temperatures timerinfo timerinfo timerinfo // convince yourself this is counting up at about 1MHz nopll // this drops the system clock to 16MHz temps // should still print all temperatures timerinfo timerinfo timerinfo // should still be counting up at about 1MHz Change-Id: Ie29ceb17af348148bffadf63d60c1b731f4c3f6d
* Change task messages to eventsRandall Spangler2012-04-061-5/+5
| | | | | | | | | | | | | Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:7461 TEST=manual make BOARD={bds,link,daisy} make tests flash link system and make sure it boots Change-Id: I1241a1895c083e387e38ddab01ac346ca4474eb9
* GPIO changes for link proto1Randall Spangler2012-03-121-1/+2
| | | | | | | | | | | | | Note that this moves the charger to a different I2C port. If you're working on battery charging, you'll need to hack board.h in your local repo to move it back. Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:8458 TEST=manual Change-Id: Id94ee2ce1ef6c973c1786037e07d0c64a89a9940
* Add I2C transmit/receive functionRong Chang2012-03-061-116/+164
| | | | | | | | | | | | | | | | | | | Implement a generalized I2C transmit-receive function that write-then-read blocks of raw data. Original 8-bit and 16-bit read/write functions are refactored. SMBus read-block protocol for ASCII string is also implemented based on this API. Signed-off-by: Rong Chang <rongchang@chromium.org> BUG=chrome-os-partner:8026,8316 TEST=manual: Type 'lightsaber' to check 8-bit read/write. Type 'charger' to check 16-bit read. Type 'charger input 4032' to check 16-bit write. Change-Id: I0ad3ad45b796d9ec03d8fbc1d643aa6a92d6343f
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