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* ish: Trim down the release branchstabilize-wristpin-14469.59.B-ishstabilize-voshyr-14637.B-ishstabilize-quickfix-14695.187.B-ishstabilize-quickfix-14695.124.B-ishstabilize-quickfix-14526.91.B-ishstabilize-14695.85.B-ishstabilize-14695.107.B-ishstabilize-14682.B-ishstabilize-14633.B-ishstabilize-14616.B-ishstabilize-14589.B-ishstabilize-14588.98.B-ishstabilize-14588.14.B-ishstabilize-14588.123.B-ishstabilize-14536.B-ishstabilize-14532.B-ishstabilize-14528.B-ishstabilize-14526.89.B-ishstabilize-14526.84.B-ishstabilize-14526.73.B-ishstabilize-14526.67.B-ishstabilize-14526.57.B-ishstabilize-14498.B-ishstabilize-14496.B-ishstabilize-14477.B-ishstabilize-14469.9.B-ishstabilize-14469.8.B-ishstabilize-14469.58.B-ishstabilize-14469.41.B-ishstabilize-14442.B-ishstabilize-14438.B-ishstabilize-14411.B-ishstabilize-14396.B-ishstabilize-14395.B-ishstabilize-14388.62.B-ishstabilize-14388.61.B-ishstabilize-14388.52.B-ishstabilize-14385.B-ishstabilize-14345.B-ishstabilize-14336.B-ishstabilize-14333.B-ishrelease-R99-14469.B-ishrelease-R98-14388.B-ishrelease-R102-14695.B-ishrelease-R101-14588.B-ishrelease-R100-14526.B-ishfirmware-cherry-14454.B-ishfirmware-brya-14505.B-ishfirmware-brya-14505.71.B-ishfactory-kukui-14374.B-ishfactory-guybrush-14600.B-ishfactory-cherry-14455.B-ishfactory-brya-14517.B-ishJack Rosenthal2021-11-051-600/+0
| | | | | | | | | | | | | | | | | | | | | | In the interest of making long-term branch maintenance incur as little technical debt on us as possible, we should not maintain any files on the branch we are not actually using. This has the added effect of making it extremely clear when merging CLs from the main branch when changes have the possibility to affect us. The follow-on CL adds a convenience script to actually pull updates from the main branch and generate a CL for the update. BUG=b:204206272 BRANCH=ish TEST=make BOARD=arcada_ish && make BOARD=drallion_ish Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I17e4694c38219b5a0823e0a3e55a28d1348f4b18 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3262038 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Tom Hughes <tomhughes@chromium.org>
* ec: change usage of dummySam Hurst2020-08-051-1/+1
| | | | | | | | | | | | | | | | | | Google is working to change its source code to use more inclusive language. To that end, replace the term "dummy" with inclusive alternatives. BUG=b:162781382 BRANCH=None TEST=make -j buildall `grep -ir dummy *` The only results are in "private/nordic_keyboard/sdk8.0.0" which is not our code. Signed-off-by: Sam Hurst <shurst@google.com> Change-Id: I6a42183d998e4db4bb61625f962867fda10722e2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2335737 Reviewed-by: Tom Hughes <tomhughes@chromium.org>
* LICENSE: remove unnecessary (c) after CopyrightTom Hughes2019-06-191-1/+1
| | | | | | | | | | | | | | | | Ran the following command: git grep -l 'Copyright (c)' | \ xargs sed -i 's/Copyright (c)/Copyright/g' BRANCH=none BUG=none TEST=make buildall -j Change-Id: I6cc4a0f7e8b30d5b5f97d53c031c299f3e164ca7 Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1663262 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* common: replace 1 << digits, with BIT(digits)Gwendal Grignou2019-03-261-30/+30
| | | | | | | | | | | | | | | | Requested for linux integration, use BIT instead of 1 << First step replace bit operation with operand containing only digits. Fix an error in motion_lid try to set bit 31 of a signed integer. BUG=None BRANCH=None TEST=compile Change-Id: Ie843611f2f68e241f0f40d4067f7ade726951d29 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1518659 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* ACPI: Support accessing memmap data over ACPI CMD / DATA portsstabilize-6915.BShawn Nematbakhsh2015-03-251-1/+1
| | | | | | | | | | | | | | | | | | | | | | | Some platforms are unable to access the 900h-9ffh region over LPC and must instead access memmap data through the ACPI CMD / DATA ports. To avoid racing with data updates, disallow changes to multi-byte memmap data while in burst mode. Linux currently enables burst mode when accessing multi-byte data and disables it immediately afterward, though the ACPI spec defines burst mode in a more general way. BUG=chrome-os-partner:38224 TEST=Manual on Samus. Undefine LPC_MEMMAP and modify asl to move memmap data to ERAM at offset 0x20. Verify system boots cleanly and battery status is updated immediately on plug / unplug. BRANCH=None Change-Id: Ib848bdb491fdfece96ad0cee7a44ba85b4a1a50b Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/262072 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* lm4 i2c: fixed lm4 i2c_xfer synchronization issueSheng-Liang Song2014-08-261-0/+2
| | | | | | | | | | | | | | Added atomic or/clear when modify a share register LM4_SYSTEM_SRI2C_ADDR among different i2c ports. BUG=None BRANCH=ToT TEST=Verified on Samus. Signed-off-by: Sheng-Liang Song <ssl@chromium.org> Change-Id: Ibf64b05a800ce2b8ddf9735bd3a762ab02031bc8 Reviewed-on: https://chromium-review.googlesource.com/213196 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* mec1322: initial commitVic (Chun-Ju) Yang2013-11-211-0/+2
| | | | | | | | | | | | | | | | | | | | This is the initial commit of mec1322 support. This includes: - Basic GPIO driver. Interrupt not supported yet. - Microsecond timer - UART driver The script to pack the firmware binary will be checked in in following-up CL. BUG=chrome-os-partner:24107 TEST=Build and boot on eval board BRANCH=None Change-Id: I9013c908049d1f740f84bb56abca51b779f39eef Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175716 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* lm4: fix enabling RTC alarmRandall Spangler2013-10-301-0/+1
| | | | | | | | | | | | | | | | | | | | | | All hibernate register writes must wait for the WC bit. When we're enabling the RTC alarm, it's important to wait for the WC bit afterwards, too, or else we could go into deep sleep before the write to HIBIM is committed. Also make sure that the normal hibernate() path enables the RTC alarm if it has a timeout. This bug wasn't noticed until the low-power idle code called system_reset_rtc_alarm(), since before then HIBIM was initialized to 1 and just stayed there. BUG=chrome-os-partner:23678 BRANCH=anywhere we use low power idle (wolf/leon, too) TEST=with hacked firmware, note that HIBIM=1 just before the wfi instruction in chip/lm4/clock.c Change-Id: Ie01b106ac6a6c5894811f9a333715b22ef896f82 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175013 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* lm4: Add a low power idle task.stabilize-4825.BAlec Berg2013-10-151-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | First implementation of a low power idle task for the LM4 chip. The low power mode is selected by defining CONFIG_LOW_POWER_IDLE in a board.h file. This commit turns it on for Peppy, Slippy, and Falco only because those are the only boards tested. When using the low power idle task, the chip goes in to deep sleep when it can. Deep sleep disables clocks to most peripherals and puts the onboard flash and RAM into a low power mode. The chip is woken out of deep sleep using the RTC in the hibernate module. Increased the idle task stack size to handle more involved idle task. In board.c, the array of GPIO info can be used to select which GPIO points can wake up the EC from deep sleep. Currenlty selected are the power button, lid open, AC present, PCH_SLP_S3, and PCH_SLP_S5. Additionally the port with the KB scan row GPIO point is also enabled to wake up the EC from deep sleep. Signed-off-by: Alec Berg <alecaberg@chromium.org> BUG=None BRANCH=none TEST=Passes all unit tests. Runs on slippy, peppy, and falco with no noticeable side affects. Verified that the power consumed by the EC is lower when in S3, S5 and G3 by scoping the sense resistor powering the chip. Change-Id: I83fa9a159a4b79201b99f2c32678dc4fc8921726 Reviewed-on: https://chromium-review.googlesource.com/172183 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Alec Berg <alecaberg@chromium.org> Tested-by: Alec Berg <alecaberg@chromium.org>
* lm4: Modified clock gating to allow easy expansion to low power.Alec Berg2013-10-101-13/+27
| | | | | | | | | | | | | | | | | | | | | Created a new function to enable or disable clocks to various peripherals. This new function makes it easy to specify if you want the clock enabled in run mode, sleep mode, and/or deep sleep mode. Added infrastructure to specify which GPIOs should interrupt the EC from deep sleep. BUG=none BRANCH=none TEST=Passes all unit tests. Ran on a peppy and verified that the clock gate control registers in run mode (LM4_RCGC regs) were the same before and after this change. Change-Id: Ia5009ac8c837f61dca52fe86ebdeede2e1a7fe4d Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/172454 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Lock BOOTCFG to safe values for all LM4sBill Richardson2013-08-211-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The BOOTCFG register configures a couple of important things: whether to allow jumping into the builtin ROM bootloader at reset, and whether or not to allow JTAG access for programing and debugging. The default is "no" and "yes". But the BOOTCFG register can be locked so that it can't be changed again, which means that if the wrong values are put into it, the system is pretty much bricked. On Link, we wrote a BOOTCFG value that allowed a GPIO to be used as a bypass to optionally trigger the ROM bootloader, but on Slippy and its derivatives that GPIO is not pulled up. If you program the Link values into BOOTCFG on a Slippy, the system is stuck in the ROM bootloader more or less forever. This change disables that GPIO, keeps JTAG enabled, and locks those settings for all LM4 chips (it's a chip config now, not a board config). We've never actually used the GPIO to invoke the ROM bootloader, but we have managed to brick a number of systems just by having it enabled, so we're going to lock it into a safe configuration now. BUG=chrome-os-partner:19247 BRANCH=falco,peppy TEST=manual Reflash, boot, power cycle (actually unplug the EC from AC and battery) a few times. It should continue to work. Change-Id: Iaf1a81d6814104421a56425490e3d5164ea9b617 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/66538 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Clean up configuring GPIO alternate functionsRandall Spangler2013-08-071-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | GPIO alternate functions used to be configured throughout the code, which made it hard to tell which ones you needed to configure yourself in board.c. It also sometimes (chip/lm4/i2c.c) led to GPIOs being configured as alternate functions even if they weren't used on a given board. With this change, every board has a table in board.c which lists ALL GPIOs which have alternate functions. This is now the only place where alternate functions are configured. Each module then calls gpio_init_module() to set up its GPIOs. This also fixes a bug where gpio_set_flags() ignored most of the flags passed to it (only direction and level were actually used). On stm32f, gpio_set_alternate() does not exist, and pins are configured via direct register writes from board.c. Rather than attempt to change that in the same CL, I've stubbed out gpio_set_alternate() for stm32f, and will fix the register writes in a follow-up CL. BUG=chrome-os-partner:21618 BRANCH=peppy (fixes I2C1 being initialized even though those pins are used for other things) TEST=boot link, falco, pit, spring Change-Id: I40f47025d8f767e0723c6b40c80413af9ba8deba Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/64400
* Move REG16 and REG32 macros to common.hRandall Spangler2013-04-101-141/+140
| | | | | | | | | | | | | | | And use them for LM4 as well as STM32. Consistency is good. No functional changes, just moving/renaming code. BUG=chrome-os-partner:18343 BRANCH=none TEST=build all platforms Change-Id: I029a21fadb50726500255219dc38615874a369e7 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/47700 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Handle arbitration lost on I2C portsRandall Spangler2012-11-281-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This seems to happen when the I2C signals come up so that the EC sees a start condition from the remote end. In this case, the EC refuses to talk on the I2C port until the EC's I2C state machine is reset. Also, don't fail on bus-busy, since that's true during a multi-part transaction such as an I2C string read. BUG=chrome-os-partner:16262 BRANCH=link TEST=boot system; 'battery' and 'temps' should give good info Then run snanda's suspend_stress_test for a while and repeat. Or a better test is to open 2 crosh shells, sudo bash in each, and 1) while true; do ectool temps all; sleep 0.5; done 2) suspend_stress_test Then watch the EC console for "I2C5 bad status" errors. These happen rarely, only on some systems. With this fix, they'll be reported when they occur, but should not cause errors to be reported by 'ectool temps all', since the I2C module will clear the arbitration-lost status before retrying. Change-Id: Idfaf9cd7e8ef2abcc0130332890329dd5d2ca052 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/38686 Reviewed-by: Yung-Chieh Lo <yjlou@chromium.org>
* Reset LPC from-host channel status on LPC resetRandall Spangler2012-09-171-0/+1
| | | | | | | | | | | | | | | | | | | | | This works around a LM4 bug where the LPC module stops triggering interrupts for a channel if bytes are written too rapidly to that channel. This should only affect port 80 because other channels use busy-status-handshaking to avoid flooding the EC. BUG=chrome-os-partner:12349 BRANCH=link TEST=manual 1. From a root shell: ectool port80flood 2. Repeat until the EC console stops showing port 80 codes coming in 3. From a root shell: reboot 4. Port 80 codes should be printed by EC as the BIOS boots Change-Id: I3b3463ce668727cad9900b576fdeb531986a415e Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/33142 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* Add real-time clock supportRandall Spangler2012-08-071-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BUG=chrome-os-partner:12290 TEST=manual From EC console, rtcget (wait a few sec) rtcget hibernate 3 (wait for wake) rtcget (hold power+refresh; wait for reboot) rtcget rtcset 20000 rtcget (wait a few sec) rtcget Each rtcget should be a few seconds after the previous one. Pull the battery and remove AC power. Then restore AC power and rtcget (wait a few sec) rtcget Should be close to 0. That is, it should have reset to 0 when power was lost. From root shell, ectool rtcget should match the time from rtcget, truncated to the nearest second. ectool rtcset 30000 should set the time (do a rtcget to check). Change-Id: I535097feb7af8aa6583c8ef50ade66bb19bdff8f Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/29349 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Add support for ACPI read/write commandsRandall Spangler2012-07-301-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is needed to support the kernel keyboard backlight driver through ACPI. Also adds a few other memory addresses for testing this interface - version, test, and test-compliment. BUG=chrome-os-partner:12001 TEST=manual - query next ACPI event io_write8 0x66 0x84 io_read8 0x62 0x00 - read ACPI memmap version io_write8 0x66 0x80 io_write8 0x62 0 io_read8 0x62 0x01 - extra command writes shouldn't crash io_write8 0x66 0x80 io_write8 0x66 0x80 io_write8 0x62 1 - extra data writes shouldn't crash either io_write8 0x62 1 io_write8 0x62 1 - write test address io_write8 0x66 0x81 io_write8 0x62 1 io_write8 0x62 0x2a - read it back io_write8 0x66 0x80 io_write8 0x62 1 io_read8 0x62 0x2a - read back test compliment io_write8 0x66 0x80 io_write8 0x62 2 io_read8 0x62 0xd5 - set keyboard backlight to 50% io_write8 0x66 0x81 io_write8 0x62 3 io_write8 0x62 50 - read it back io_write8 0x66 0x80 io_write8 0x62 3 io_read8 0x62 0x32 Change-Id: I619fdbd322cdef8ffffbb882b3bbb587e364334d Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/28714 Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* Refactor HIBDATA access so we can use multiple hibernate regsRandall Spangler2012-07-161-2/+3
| | | | | | | | | BUG=chrome-os-partner:11368 TEST=none Change-Id: I33ba317ce1cff957add7ebe34860fa4a3c686ca0 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/27380
* Revise EEPROM init and write routinesRandall Spangler2012-06-221-0/+2
| | | | | | | | | | | | | | | | | | | | | They now more closely resemble TI's recommended flow. BUG=chrome-os-partner:10764 TEST=manual: eewrite 1 12 0x1000 eeread 1 12 --> should be 0x1000 eewrite 1 12 0 eewrite 1 12 1 ... eewrite 1 12 100 eewrite 1 12 0xabcd eeread 1 12 --> should be 0xabcd Signed-off-by: Randall Spangler <rspangler@chromium.org> Change-Id: I309caea2774615518e68a0d01d33b052d6945c0f Reviewed-on: https://gerrit.chromium.org/gerrit/25941 Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* Move System Control Block registers to core headerVincent Palatin2012-06-151-2/+0
| | | | | | | | | | | | | | | | | | | The SCB registers are defined in the ARMv7-M architecture, so they are common to all chips. We will need System Control Register (SCR aka SYSCTRL) to implement power management on stm32. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=None TEST=make BOARD=link && make BOARD=snow Change-Id: I35c283731306541b3d21398c96fdca89954fe20a Reviewed-on: https://gerrit.chromium.org/gerrit/25392 Reviewed-by: Randall Spangler <rspangler@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
* Add basic SPI support to linkRandall Spangler2012-05-301-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds SPI transaction support, and a debug command to read a few values from the SPI EEPROM. Note that the SPI controller is normally *disabled* with all its I/Os high-Z, so this will not interfere with main processor or Servo on the SPI bus. The bus is only enabled during the SPIROM command itself. BUG=chrome-os-partner:7844 TEST=manual 1) Reboot system 2) on EC console, 'spirom'. Should print Man/Dev ID : 0xef 0x16 JEDEC ID : 0xef 0x40 0x17 Unique ID : 0xd1 0x61 0x44 0xb0 0x63 0x5d 0x40 0x32 Status reg 1: 0x00 Status reg 2: 0x00 Note that unique ID is, well, unique, so it won't match my value. But it should still be something not all 0xff's. 3) Power on the system. x86 should still boot normally, indicating that the EC isn't interfering with the SPI bus. Change-Id: I53bf5fdbbe7a37949375d0463e30e408cc6fb6a8
* Enable brown-out resetRandall Spangler2012-05-241-0/+1
| | | | | | | | | | | This resets the EC when power falls below the brown-out threshold Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:9952 TEST=hopefully srikanth can; requires hardware mods to test. Change-Id: I161e49003409cb68eb43303c3c8de0eb4cc27104
* Set BOOTCFG register to test valueRandall Spangler2012-04-241-0/+1
| | | | | | | | | | | | | | Needed for testing preprogramming chips Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:8769 TEST=manual hibernate 1; should reboot rw 0x400fe1d0; should print: read word 0x400fe1d0 = 0xfffffdfe Change-Id: I95b419d7285a0bf5204f95d1f68f64dc212bb39e
* Remove clock calibration for PIOSCRandall Spangler2012-04-201-1/+7
| | | | | | | | | | | Proto1 has A3 silicon which is factory-trimmed. Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:7693 TEST=boot and look for glitchy EC console. If it's not glitchy, it worked. Change-Id: I56cb2458e600e76e458bce0f24832ef4f456ac14
* Add USER_REG3 and indicate it's reserved for preprogramming process data.Randall Spangler2012-04-111-0/+3
| | | | | | | | | Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:8889 TEST=code still builds Change-Id: Ifdd31189fb5de779f090aa089173407e381c62b7
* Support dynamically changing the system clockRandall Spangler2012-04-091-0/+10
| | | | | | | | | | | | | | | | | | | | | | | Add nopll command to turn off the PLL, reducing the system clock to 16Mhz. Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:8798 TEST=manual boot system press power button to boot x86 temps // should print all temperatures timerinfo timerinfo timerinfo // convince yourself this is counting up at about 1MHz nopll // this drops the system clock to 16MHz temps // should still print all temperatures timerinfo timerinfo timerinfo // should still be counting up at about 1MHz Change-Id: Ie29ceb17af348148bffadf63d60c1b731f4c3f6d
* Support chipinfo command (ectool/host commands)Louis Yung-Chieh Lo2012-04-091-0/+2
| | | | | | | | | | | | | | | | Add a host command returning chip information. The interface is in common/ while the implementations are in chip-specific code (note: added simple value for stm). BUG=chrome-os-partner:8567 TEST=on board % ectool chipinfo Chip info: vendor: xx name: yyyy revision: zzzzz Change-Id: I5030a03a6fcfbfc080d5acd8efb763fde7eefde5
* Add support for generating SCI via LPCDuncan Laurie2012-04-061-0/+5
| | | | | | | | | | | | | | | | | | | | | | The SCI pin is not connected to a GPIO and it uses a different method to trigger a pulse via LPC0SCI. The ACPI specification requires SCI for 3 conditions: - SCI event pending - Input Buffer Empty - Output Buffer Full The buffer full/empty SCIs are used to nudge the kernel driver along so it does not have to poll for a potential slow EC to be ready. This only really makes sense for the kernel channel so they are only generated there. BUG=chrome-os-partner:8277 TEST=using (unreleased) coreboot BIOS to test that the kernel can receive SCI events and the ACPI method is successfully run. Change-Id: I6b3717fcad6569bda4482d9aaa37d45b4cf36335 Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
* Use precision internal osciallator for UART and ADCRandall Spangler2012-03-121-2/+4
| | | | | | | | | | | This simplifies upcoming transitions to/from sleep (with PLL shutdown). Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=none TEST=manual - make sure 'adc' command and uarts still work Change-Id: I070ca2d96ba4fef6fef6519896e7e9a181866efc
* Add PECI module and CPU temperature monitoringRandall Spangler2012-02-101-0/+24
| | | | | | | | | Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:7493 TEST='powerbtn' to boot main processor, then 'temps' and 'pecitemp' Change-Id: Id57526ebb37c8aecb05ecebccc2824f462b9de1a
* NVIC registers are not SoC specificVincent Palatin2012-01-251-6/+0
| | | | | | | | | | | | | Preparatory work to introduce a second SoC : 5/5 All Cortex-M3/4 have the same NVIC registers at the same address. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BUG=None TEST=run EC firmware on BDS and check a few console commands Change-Id: I6b03c4c1fb21850be8c8afb711ea44134c8cdea1
* Calibrate internal oscillator using hibernate clockRandall Spangler2012-01-231-1/+3
| | | | | | | | | | | | This works around a chip errata where the internal oscillator on early EC parts (as used on proto0) is untrimmed. Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:7693 TEST=if it runs, it works Change-Id: Ie82a524543f4cf25efd0de7998dbdae103bd126b
* Configure all GPIOsRandall Spangler2012-01-121-0/+1
| | | | | | | | | Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:7528 TEST=none Change-Id: I0a9be4c689fb72507edcf202073b23c58902d7de
* Tidy GPIO configuration and board-specific configs for modules.Randall Spangler2012-01-121-6/+8
| | | | | | | | | Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:7528 TEST=none Change-Id: Ia06707db78ea9a9313b49a93e8732a7fc9fcc191
* Add JTAG moduleRandall Spangler2012-01-111-0/+2
| | | | | | | | | | | This just ensures the JTAG pins are reset to JTAG function on warm reboot. Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=chrome-os-partner:7448 TEST=none Change-Id: I0cccdbe7a68c228db7f354898ed30598e9fabff0
* Use #defined constants for IRQ namesRandall Spangler2011-12-191-0/+89
| | | | | | | | | Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=none TEST=none Change-Id: If07ac671cef6b9d0e9fe0a96bf04455a3d2626ff
* Change register.h macros to use inline funcs without concatenate (##).Randall Spangler2011-12-131-28/+61
| | | | | | | | | Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=none TEST=none Change-Id: Ia8c54bfeff2351e8f76d97db558952a9d2ca9a45
* Add IRQ constants, and task functions to enable/disable/trigger IRQs.Randall Spangler2011-12-121-0/+14
| | | | | | | | | | | | | The constants don't work with the DECLARE_IRQ() macro yet, because it relies on stringizing the IRQ number. Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=none TEST=none Change-Id: Ie6ddecd79e28c319b095089131579ba994a17da3 (cherry picked from commit e24904644a977f2618f51629cc066b93a3d53595)
* Clean up UART codeRandall Spangler2011-12-121-1/+6
| | | | | | | | | | | | LPC module no longer directly talks to UART registers, and vice-versa. Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=none TEST='ectool sertest' on target system Change-Id: Id070c0d849bdfe91c752e0af651d357b695d2648 (cherry picked from commit ab8c3c2b8e3b08a4bf5573cda3a12dd3a384e67d)
* Add flash write protect range commandRong Chang2011-12-121-0/+1
| | | | | | | | | | | This CL add host command to enable, get/set flash write protect range. BUG=None TEST=Use flashrom utility to set write protect range, enable write protect and get status. Change-Id: I345f1eb65944d8cf8028e6fdb7e43c40cc742a6d Signed-off-by: Rong Chang <rongchang@chromium.org>
* Add user-mode LPC endpointRandall Spangler2011-12-081-1/+7
| | | | | | | | | Signed-off-by: Randall Spangler <rspangler@chromium.org> BUG=none TEST='ectool hello' on target system Change-Id: I39845c2ea107ea6f85ef556d58e49343f5a0e9c0
* Initial sources import 1/3Randall Spangler2011-12-071-0/+312
source files mainly done by Randall. Signed-off-by: Randall Spangler <rspangler@chromium.org> Change-Id: Iaff83a842b17f3350fb6f2a3f1597ad4c29bd12a
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