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* Cleanup: gate RTC console/host command behind new config optionsphilipchen2016-06-291-0/+4
| | | | | | | | | | | | | | | | Put RTC code supporting console/host command behind new flags 'CONFIG_CMD_RTC'/'CONFIG_HOSTCMD_RTC' BUG=chromium:613699 TEST=make buildall BRANCH=master Change-Id: Ida52265d124978f48bd6ca522be3badee9f99588 Reviewed-on: https://chromium-review.googlesource.com/356206 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* servo_v4: Fix ADC console commandNick Sanders2016-05-261-12/+0
| | | | | | | | | | | | | | | | | | | | | | The console adc command prints adc values in the order they appear in hardware, however they are lableled in the order they are enumerated in board.h, which is not necessarily the same. This prints the correct name and value pairs, and removes the adc_read_all_channels function which is not otherwise used. BUG=chromium:571476 BRANCH=None TEST="adc" command associates correct values with names now. Change-Id: I688641953d20082224b4120eaefe0d634ad4c74c Signed-off-by: Nick Sanders <nsanders@google.com> Reviewed-on: https://chromium-review.googlesource.com/340892 Commit-Ready: Nick Sanders <nsanders@chromium.org> Tested-by: Nick Sanders <nsanders@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* hooks: Add relative HOOK_INIT priority for peripheralsShawn Nematbakhsh2016-05-053-3/+4
| | | | | | | | | | | | | | | | | | | Using HOOK_PRIO_DEFAULT for peripheral initialization necessitates using HOOK_PRIO_DEFAULT+1 for board-level code. Instead, use a higher-than-default relative priority for peripheral initialization outside of board. BUG=None TEST=Verify PWM and ADC are functional on kevin. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Ia8e90a7a866bdb0a661099dd458e3dfcaaa3f6bb Reviewed-on: https://chromium-review.googlesource.com/342171 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* pwm: Add PWM_CONFIG_DSLEEP config flagShawn Nematbakhsh2016-04-271-4/+1
| | | | | | | | | | | | | | | | | | | Add PWM_CONFIG_DSLEEP PWM config flag, which can be set to keep a channel active during low-power idle / deep sleep. Currently it's supported by npcx and mec1322. BUG=chrome-os-partner:52783 BRANCH=glados TEST=Manual on chell w/ subsequent commit + CONFIG_LOW_POWER_S0. Verify KB backlight does not flicker during idle. Change-Id: Ib9df5879aaa7dfa5764de1583496de84d40d2bb5 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/341002 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Todd Broch <tbroch@chromium.org>
* UART: Remove enable/disable interrupt functionsAnton Staaf2016-04-271-10/+0
| | | | | | | | | | | | | | | | These were not being used and complicate changes to the UART API. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Change-Id: I73e256f09f7ea72f0cc4831cc7ce391a7125e555 Reviewed-on: https://chromium-review.googlesource.com/340841 Commit-Ready: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* Deferred: Remove hard coded number of deferredsAnton Staaf2016-04-191-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | Previously the maximum number of deferred routines was specified by the the default maximum number of deferred routines you had to override this, and if you wanted fewer, you still payed the price of having the defer_until array statically allocated to be the maximum size. This change removes that define and instead creates the RAM state of the deferred routine (the time to wait until to call the deferred) when the deferred is declared. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j manually test on discovery-stm32f072 Change-Id: Id3db84ee1795226b7818c57f68c1f637567831dc Reviewed-on: https://chromium-review.googlesource.com/335597 Commit-Ready: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* Deferred: Use deferred_data instead of function pointerAnton Staaf2016-04-181-1/+1
| | | | | | | | | | | | | | | | | | | | | Previously calls to hook_call_deferred were passed the function to call, which was then looked up in the .rodata.deferred section with a linear search. This linear search can be replaced with a subtract by passing the pointer to the deferred_data object created when DECLARE_DEFERRED was invoked. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None CQ-DEPEND=CL:*255812 TEST=make buildall -j Change-Id: I951dd1541302875b102dd086154cf05591694440 Reviewed-on: https://chromium-review.googlesource.com/334315 Commit-Ready: Bill Richardson <wfrichar@chromium.org> Tested-by: Bill Richardson <wfrichar@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* ec: Add a chipset reset hookDuncan Laurie2016-01-251-0/+13
| | | | | | | | | | | | | | | | | | | | | | There are hooks for chipset power sequencing but not one to indicate that the system has reset at runtime. Add a hook for this and implement for lm4 and mec1322. The hook is notified on any platform reset, including those that happen on the way into S3/S5 state. There is a new config variable added because the hook is notified in the interrupt handler and needs a deferrable function that needs to be added to every board. BUG=chrome-os-partner:46049 BRANCH=none TEST=tested on glados and samus Change-Id: I3be639414e18586344e0ec84632a50dfc1df586b Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/315221 Commit-Ready: Aaron Durbin <adurbin@chromium.org> Tested-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* GPIO: Add gpio_reset functionAnton Staaf2016-01-191-2/+1
| | | | | | | | | | | | | | | | | The gpio_reset function returns a GPIO to its initialy configured state. Using it removes a few more uses of gpio_list. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Change-Id: Ie24e8e8a96d0ff50f521a918e80ed2b379f8c1a9 Reviewed-on: https://chromium-review.googlesource.com/321951 Commit-Ready: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* common: adc/i2c: Mark task_waiting volatileShamile Khan2015-12-012-2/+2
| | | | | | | | | | | | | | | | | | | When Link Time Optimization is turned on, functions that set task_waiting multiple times have one of the sets removed by the linker leading to undesired results. Marking task_waiting volatile alleviates this issue. BUG=chrome-os-partner:46063 TEST=Manually tested on Kunimitsu. Console command adc shows correct value of approx 20000 mV for VBUS. BRANCH=none Change-Id: I85a6e5c9688ae72c45d90fb58296f94b74a301aa Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/314233 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* cleanup: Standardize use of CONFIG_I2C and add MASTER/SLAVE CONFIGsShawn Nematbakhsh2015-11-031-1/+0
| | | | | | | | | | | | | | | | | | | Some chips previously defined CONFIG_I2C and others didn't. Standardize the usage by removing CONFIG_I2C from all config_chip files and force it to be defined at the board level. Also, make boards define CONFIG_I2C_MASTER and/or CONFIG_I2C_SLAVE based on the I2C interfaces they will use - this will assist with some later cleanup. BUG=chromium:550206 TEST=`make buildall -j` BRANCH=None Change-Id: I2f0970e494ea49611abc315587c7c9aa0bc2d14a Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/310070 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org>
* cleanup: Put chip-specific configs in config_chip.hBill Richardson2015-09-211-0/+8
| | | | | | | | | | | | | | | | | | | | include/config_std_internal_flash.h is an optional header that can be used to implement the most common EC flash layout. However, CONFIG_INTERNAL_STORAGE, CONFIG_MAPPED_STORAGE, and CONFIG_MAPPED_STORAGE_BASE are fixed by the SoC, so they belong in config_chip.h, not in the optional header. BRANCH=none BUG=chrome-os-partner:23796 TEST=make buildall Refactoring only, no behavioral differences. Change-Id: I114c3e194837041920e6f228a2bed6747be8231c Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/301330 Reviewed-by: Shawn N <shawnn@chromium.org>
* chip: Set CONFIG_FPU on a board basis.Gwendal Grignou2015-09-181-1/+0
| | | | | | | | | | | | | | Only few boards need FPU. Not enabling FPU saves on stack memory. BRANCH=none BUG=chrome-os-partner:36126 TEST=compile all boards. Change-Id: I1fed9920f9d64664be303e9e2a74673416c05365 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/299517 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org>
* cleanup: Remove redundant FLASH_SIZE CONFIGsShawn Nematbakhsh2015-09-162-2/+2
| | | | | | | | | | | | | | | | | | | | Since there is no more concept of a flash region belonging only to the EC, we only need one FLASH_SIZE config, which represents the actual physical size of flash. BRANCH=None BUG=chrome-os-partner:23796 TEST=With entire patch series, on both Samus and Glados: - Verify 'version' EC console command is correct - Verify 'flashrom -p ec -r read.bin' reads back EC image - Verify software sync correctly flashes both EC and PD RW images Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I18a34a943e02c8a029f330f213a8634a2ca418b6 Reviewed-on: https://chromium-review.googlesource.com/297824 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cleanup: Rename geometry constantsShawn Nematbakhsh2015-09-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Rename and add geometry constants to match spec doc - https://goo.gl/fnzTvr. CONFIG_FLASH_BASE becomes CONFIG_PROGRAM_MEMORY_BASE CONFIG_FLASH_MAPPED becomes CONFIG_MAPPED_STORAGE Add CONFIG_INTERNAL_STORAGE, CONFIG_EXTERNAL_STORAGE and CONFIG_MAPPED_STORAGE_BASE where appropriate. This CL leaves chip/npcx in a broken state -- it's fixed in a follow-up CL. BRANCH=None BUG=chrome-os-partner:23796 TEST=With entire patch series, on both Samus and Glados: - Verify 'version' EC console command is correct - Verify 'flashrom -p ec -r read.bin' reads back EC image - Verify software sync correctly flashes both EC and PD RW images Change-Id: Idb3c4ed9f7f6edd0a6d49ad11753eba713e67a80 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/297484 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Cleanup: Remove COMPILE_FOR_RAM option from linker scriptsBill Richardson2015-09-081-3/+0
| | | | | | | | | | | | | | | This option was added way back in January 2012 for early EC bringup, and never used since. We can probably remove it. BUG=none BRANCH=none TEST=make buildall Change-Id: Idc8c3099388f2e28d620848a0e78b555b02fba9c Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/297334 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* lm4: Add debug output for overlapping HCs.Aseda Aboagye2015-08-051-1/+4
| | | | | | | | | | | | | | | | | | | | | | Currently, when a host command is received which would overlap with an ongoing host command, we ignore it silently. This commit simply logs a line to the EC console stating that we are ignoring the overlapping host command. BRANCH=None BUG=chrome-os-partner:23806 TEST=make -j buildall tests TEST=Build, flash, and boot samus. Using ectool, read 64K from flash while also querying the current EC switch positions. Observe the log message being printed to the EC console. Change-Id: Ic0d249ccec2efb9600bcf8567392add1ee6295d9 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/290545 Trybot-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* common: change interface to SPI flashGwendal Grignou2015-07-301-15/+29
| | | | | | | | | | | | | | | | Allow more than one SPI master. Add CONFIG variables to address the system SPI flash. To have SPI master ports, spi_ports array must be defined. BRANCH=smaug TEST=compile BUG=chrome-os-partner:42304 Change-Id: Id43869f648965c1582b7be1c7fb3a38f175fda95 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/288512 Commit-Queue: David James <davidjames@chromium.org>
* ADC: Add common priority for the ADC initVijay Hiremath2015-07-161-1/+1
| | | | | | | | | | | | | | Added common priority for the ADC init to ensure board level priority is defined for the ADC pre init. BUG=none TEST=make buildall -j BRANCH=none Change-Id: Id1649df6a68ab53bd110e58a0722bd4c70cbffc5 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/286040 Reviewed-by: Shawn N <shawnn@chromium.org>
* flash_ec: move openocd configs from chip/ to util/Myles Watson2015-07-093-93/+0
| | | | | | | | | | | | | | Avoid duplicating servo configurations for every chip. BRANCH=none BUG=chrome-os-partner:22990 TEST=None. This is an intermediate step to make it clear what's happening. CQ-DEPEND=CL:273950 Change-Id: I448543b6ab9d39423955e8d2589b6035c59e838a Signed-off-by: Myles Watson <mylesgw@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/273906 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Fix assertion crash in __wait_evt()Chiranjeevi Rapolu2015-06-251-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | mutex_lock() is called from MEC1322_IRQ_ACPIEC0_IBF interrupt context, causing deadlock and assertion in __wait_evt(). In the interrupt context it now checks for mutex lock first. If the mutex is already locked,, it will disable ACPI interrupts and defer the memmap mutex lock. Added LPC interrupt disable/enable functions as needed. Increased deferred function count where needed. BRANCH=None BUG=chrome-os-partner:40820 TEST=Test for suspend-resume, cold, warm reboots and other general stability. Change-Id: I3dda0d4635a6b6281faf200c8c7b6fcba8877254 Signed-off-by: Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.com> Reviewed-on: https://chromium-review.googlesource.com/280418 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org> Commit-Queue: Divya Jyothi <divya.jyothi@intel.com> Tested-by: Divya Jyothi <divya.jyothi@intel.com>
* cleanup: fix all the header guardsBill Richardson2015-06-181-3/+3
| | | | | | | | | | | | | | | This unifies all the EC header files to use __CROS_EC_FILENAME_H as the include guard. Well, except for test/ util/ and extra/ which use __TEST_ __UTIL_ and __EXTRA_ prefixes respectively. BUG=chromium:496895 BRANCH=none TEST=make buildall -j Signed-off-by: Bill Richardson <wfrichar@chromium.org> Change-Id: Iea71b3a08bdec94a11239de810a2b2e152b15029 Reviewed-on: https://chromium-review.googlesource.com/278121 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* flash_ec: remove unused USB and unprotect optionsMyles Watson2015-06-181-15/+0
| | | | | | | | | | | | | | There is no need for the usb flag, remove it. There is no need for the unprotect flag, remove it. BRANCH=none BUG=chrome-os-partner:22990 TEST=run flash_ec before and after Change-Id: I201bad7f5be63a90bb8168e21baef2c6fa8d85b4 Signed-off-by: Myles Watson <mylesgw@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/273904 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Remove obsolete board-specific codeRandall Spangler2015-06-101-53/+0
| | | | | | | | | | | | | | | | | Now that we've removed boards from ToT, also delete board-specific code used only by the removed boards. There are still more things to remove (unused charging chips, LED drivers, COMx support). More CLs coming. BUG=chromium:493866 BRANCH=none TEST=make buildall -j Change-Id: Ie6bdeaf96e61cadd77e3f6336c73b9b54ff4eabb Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/276524 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* mec1322: Implement i2c_set_timeoutShawn Nematbakhsh2015-06-031-3/+0
| | | | | | | | | | | | | Allow timeout to be set at runtime by controller. BUG=chrome-os-partner:40780 TEST=Manual on Glados. Verify PD I2C communication is functional. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I582e47c7bebfed7a639789c90064d86ffe1a5401 Reviewed-on: https://chromium-review.googlesource.com/274967 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* i2c: Make i2c_xfer a wrapper function to chip_i2c_xferShawn Nematbakhsh2015-05-271-4/+4
| | | | | | | | | | | | | | | | i2c_xfer was previously implemented at the chip-level, but now we want to add some global retry logic. Rename the chip-level i2c_xfer functions to chip_i2c_xfer and add a new global wrapper function i2c_xfer. BUG=chrome-os-partner:39613 TEST=Run "battery" from EC console on Cyan, verify that values + strings are correctly printed. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: If37c85cc3cf94fd53feb6931553e10c30ad6cad6 Reviewed-on: https://chromium-review.googlesource.com/272939 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* mec1322: Simplify GPIO listsSteven Jian2015-05-271-0/+3
| | | | | | | | | | | | | | | Our existing GPIO macros use port# / gpio#, but the concept of different GPIO ports does not exist on the mec1322. Therefore, add new GPIO macros for chips which do not have distinct GPIO ports. BUG=None BRANCH=None TEST=make buildall -j Change-Id: Ibda97c6563ad447d16dab39ecadab43ccb25174b Signed-off-by: Steven Jian <steven.jian@intel.com> Reviewed-on: https://chromium-review.googlesource.com/262841 Reviewed-by: Anton Staaf <robotboy@chromium.org>
* i2c: Move i2c_read_string to common codeShawn Nematbakhsh2015-05-261-30/+0
| | | | | | | | | | | | | | | | | Since stm32 and mec1322 now support open-ended i2c_xfer, we can move the lm4 i2c_read_string implementation to common code and delete all chip-specific versions. BUG=chrome-os-partner:39613 TEST=Run "battery" from EC console on Cyan and Oak, verify that battery info + strings are correctly printed. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I06369df64bb2eb747d163664b4c96eeacb4b1faa Reviewed-on: https://chromium-review.googlesource.com/272938 Reviewed-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cleanup: Use appropriate image geometry CONFIGsShawn Nematbakhsh2015-05-152-34/+4
| | | | | | | | | | | | | | | | - Use CONFIG_*_MEM when dealing with images in program memory. - Use CONFIG_*_STORAGE when dealing with images on storage. - Use CONFIG_WP when dealing with the entire WP RO region. BUG=chrome-os-partner:39741,chrome-os-partner:23796 TEST=Manual on Cyan with subsequent commit. Verify that FMAP matches actual layout of image. Verify flashrom succeeds flashing + verifying EC image using host command interface. BRANCH=None Change-Id: Iadc02daa89fe3bf07b083ed0f7be2e60702a1867 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/270269
* cleanup: Rename image geometry CONFIGsShawn Nematbakhsh2015-05-121-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | Rename image geometry configs with a uniform naming scheme to make their purposes more clear. CONFIG_RO_MEM_OFF (was CONFIG_FW_RO_OFF) - RO image offset in program memory CONFIG_RO_STORAGE_OFF (was CONFIG_RO_SPI_OFF) - RO image offset on storage CONFIG_RO_SIZE (was CONFIG_FW_RO_SIZE) - Size of RO image CONFIG_RW_MEM_OFF (was CONFIG_FW_RW_OFF) - RW image offset in program memory CONFIG_RW_STORAGE_OFF (was CONFIG_RW_SPI_OFF) - RW image offset on storage CONFIG_RW_SIZE (was CONFIG_FW_RW_SIZE) - Size of RW image CONFIG_WP_OFF (was CONFIG_FW_WP_RO_OFF) - Offset of WP region on storage CONFIG_WP_SIZE (was CONFIG_FW_WP_RO_SIZE) - Size of WP region on storage BUG=chrome-os-partner:39741,chrome-os-partner:23796 TEST=Set date / version strings to constants then `make buildall -j`. Verify that each ec.bin image is identical pre- and post-change. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I6ea0a4e456dae71c266fa917a309b9f6fa4b50cd Reviewed-on: https://chromium-review.googlesource.com/270189 Reviewed-by: Anton Staaf <robotboy@chromium.org>
* flash: Add option to move pstate inside RO imageRandall Spangler2015-04-171-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, ECs with internal flash store the write protect state for RO in a separate write/erase block of flash. This is wasteful on chips where there are not many blocks of flash. Add a new CONFIG_FLASH_PSTATE_IN_BANK option which is defined by default. This is the old behavior, for compatibility. (And we're calling it 'bank' because that's what the existing code does, even if the terminology is somewhat etymologically... bankrupt.) If that config is #undef'd, then store the write protect flag directly inside the RO image. This uses only 4 bytes of the RO image, instead of an entire erase block. The magic numbers for the pstate values are chosen such that when protecting RO, bits are only transitioned away from their erased state. Unprotecting RO once it's protected requires reflashing RO; it's no longer possible to 'flashwp disable'. But that's ok, because realistically, the only reason to unprotect RO is if you're about to flash the RO firmware anyway. BUG=chromium:476659 BRANCH=none TEST=Without undefining CONFIG_FLASH_PSTATE_IN_BANK, make sure everything still works on samus and samus_pd. This ensures we didn't break the existing functionality: flashinfo -> no flags flashwp enable flashinfo -> ro_at_boot reboot flashinfo -> ro_at_boot flashwp disable flashinfo -> no flags Then recompile with #undef CONFIG_FLASH_PSTATE_IN_BANK and test: flashinfo -> no flags flashwp enable flashinfo -> ro_at_boot reboot flashinfo -> ro_at_boot flashwp disable -> fails with access denied flashinfo -> ro_at_boot Then reflash to verify that clears the ro_at_boot flag: flashinfo -> no flags Change-Id: Ie794b8cfed2a10c50b0e36dcf185884070b04666 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/266095 Reviewed-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Trybot-Ready: Vincent Palatin <vpalatin@chromium.org>
* gpio: Refactor IRQ handler pointer out of gpio_listAseda Aboagye2015-04-101-6/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the gpio_info struct, we had a irq_handler pointer defined even though a majority of the GPIOs did not have irq handlers associated. By removing the irq_handler pointer out of the struct, we can save some space with some targets saving more than others. (For example, ~260 bytes for samus_pd). This change also brings about a new define: GPIO_INT(name, port, pin, flags, signal) And the existing GPIO macro has had the signal parameter removed since they were just NULL. GPIO(name, port, pin, flags) In each of the gpio.inc files, all the GPIOs with irq handlers must be defined at the top of the file. This is because their enum values from gpio_signal are used as the index to the gpio_irq_handlers table. BUG=chromium:471331 BRANCH=none TEST=Flashed ec to samus and samus_pd, verified lightbar tap, lid, power button, keyboard, charging, all still working. TEST=Moved a GPIO_INT declaration after a GPIO declaration and watched the build fail. TEST=make -j BOARD=peppy tests TEST=make -j BOARD=auron tests TEST=make -j BOARD=link tests Change-Id: Id6e261b0a3cd63223ca92f2e96a80c95e85cdefb Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/263973 Reviewed-by: Randall Spangler <rspangler@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> Trybot-Ready: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org>
* ACPI: Support accessing memmap data over ACPI CMD / DATA portsstabilize-6915.BShawn Nematbakhsh2015-03-252-1/+19
| | | | | | | | | | | | | | | | | | | | | | | Some platforms are unable to access the 900h-9ffh region over LPC and must instead access memmap data through the ACPI CMD / DATA ports. To avoid racing with data updates, disallow changes to multi-byte memmap data while in burst mode. Linux currently enables burst mode when accessing multi-byte data and disables it immediately afterward, though the ACPI spec defines burst mode in a more general way. BUG=chrome-os-partner:38224 TEST=Manual on Samus. Undefine LPC_MEMMAP and modify asl to move memmap data to ERAM at offset 0x20. Verify system boots cleanly and battery status is updated immediately on plug / unplug. BRANCH=None Change-Id: Ib848bdb491fdfece96ad0cee7a44ba85b4a1a50b Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/262072 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* lm4: stm32: Store panic data in backup registers on hard resetShawn Nematbakhsh2015-03-141-3/+37
| | | | | | | | | | | | | | | | | | On hard reset / hibernate, RAM will be erased and panic data will normally be lost. When software panic data saving is enabled, try to save this data just before hard reset and restore it when we come back up. BUG=chrome-os-partner:37380 TEST=Manual on Samus with WP + SW sync enabled. Boot AP, then run "crash divzero" on console. After hard reset, verify that "panicinfo" dumps data and shows divzero exception code. BRANCH=Samus Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I9516dd4b6db12ef35e512cc4710f9b97d7e663cb Reviewed-on: https://chromium-review.googlesource.com/255912 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Remove unused CONFIG_PSTATE_AT_END optionRandall Spangler2015-02-271-11/+1
| | | | | | | | | | | | | | | | All current boards in ToT place pstate at the end of the RO section. Remove the unused option to place it at the end of the RW section; we'll never do that again. BUG=none BRANCH=none TEST=make buildall -j Change-Id: I0d279a4c9786bb33367a7387423481cc9b94e115 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/253636 Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* lm4: workaround to force __enter_hibernate in SRAMVincent Palatin2015-01-231-1/+2
| | | | | | | | | | | | | | | | | | | | | | The new toolchain is putting again the __enter_hibernate function in flash (.text) rather than in SRAM (.iram.text) after inlining both the hibernate() and __enter_hibernate() function. Workaround this issue by forcing "noinline" on __enter_hibernate(). Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=all BUG=chrome-os-partner:35774 TEST=make BOARD=samus dis and check the disassembly, the __enter_hibernate is called in SRAM through a veneer. Change-Id: I015928ebe18ba8fd93252eece3e8a0fcf4b2a037 Reviewed-on: https://chromium-review.googlesource.com/242691 Trybot-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
* lm4: ignore overlapping LPC commandsVincent Palatin2015-01-231-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | If the AP ignores the LPC_ST_BUSY bit (which is software-defined) and tries to send a second host command while the first one is still processed, we discard it. This doesn't prevent the host to re-write the command arguments stored in LPC shared mem (aka LPC_POOL_CMD_DATA) but when we will call host_packet_receive, we will have either the old arguments or the new arguments (or even a mix of both, which is less unlikely to pass the checksum check), and we will copy them once before calling the HOSTCMD task. So the host command task will have a single coherent (not changing) view of the arguments when performing its input validation. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=samus BUG=chrome-os-partner:31492 chrome-os-partner:23806 TEST=Boot Samus and play with ectool Change-Id: I9aa1b8cdac05e323b91998188bd873826e83c274 Reviewed-on: https://chromium-review.googlesource.com/242593 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Trybot-Ready: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Kees Cook <keescook@chromium.org>
* I2C: Increase priority of i2c_initAlexandru M Stan2015-01-161-1/+1
| | | | | | | | | | | | | | | | Chipset sometimes needs I2C, therefore i2c_init should have a higher priority than power_common_init so i2c is available by the time the chipset might be talking to the battery. BUG=chrome-os-partner:35502, chrome-os-partner:35173 TEST=There is no "battery not responding" message at startup on veyron TEST=EC boot takes less than 1 second on veyron BRANCH=none Change-Id: Ib10b653decc7703e706d4dd1976abf0fdbc25ac2 Signed-off-by: Alexandru M Stan <amstan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/241102 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* lm4: Increase time to wake up from deep sleepShawn Nematbakhsh2015-01-081-2/+2
| | | | | | | | | | | | | | | | | | The recent change to decrease the time to wake up from deep sleep when not using LFIOSC was too agressive. Increase the time to wake up based upon the worst observed case. BUG=chrome-os-partner:35184 TEST=Manual on Samus. Go to deep sleep, verify that no "overslept by Xus" prints are seen. BRANCH=Samus Change-Id: Ib9fe2eba5e29a112e03fffaedbc5ae53d6d650ff Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/239242 Reviewed-by: Alec Berg <alecaberg@chromium.org> Commit-Queue: Alec Berg <alecaberg@chromium.org> Tested-by: Alec Berg <alecaberg@chromium.org>
* lm4: decrease time to wake up from deep sleep to save powerAlec Berg2015-01-061-0/+8
| | | | | | | | | | | | | | | | | | Decrease the time to wake up from deep sleep when not using LFIOSC (when using PIOSC in deep sleep). This helps keep us in deep sleep longer and therefore save power. BUG=none BRANCH=samus TEST=Load onto samus and run for a couple of hours, varying from S0 to S5, with and without EC. Use idlestats to check that closest we get to missing deadline is 86us away. Change-Id: I3eee908e9f42a1c5b549e93d63588a3cb6e29a5d Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/238412 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Samus: Handle fan startup in the EC, not the fan controllerBill Richardson2014-11-061-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | The fans on samus have a recommended minimum duty cycle of 20% while running, but 30% in order to start. We've been using the EC's built-in fan controller for the start requirement, but it has a minimum fast-start duty cycle of 50%. It turns out that that speed is noticeably noisy. This change handles the startup with logic in the EC instead, so that the fan only tries to spin at 30% initially (or if it drops too much below the minimum turning speed). BUG=chrome-os-partner:33429 BRANCH=ToT,samus TEST=make buildall -j Boot the system, let it idle with the browser windows closed, the browse a bit, then idle. Listen for changes to the fans. Before, I could hear the fans kick in and out as the AP load changed. Now it's much quieter. Change-Id: Id35215520c064eb6843686ec8bb5f3618dac6cf6 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/227658 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* EC:KBC: Wait until LPC host senses the IRQ and gets the character.Kenji Chen2014-10-281-1/+6
| | | | | | | | | | | | | BRANCH=master BUG=chrome-os-partner:29139 TEST=Buiid an EC FW image and run on Rambi to test if key loss is improved and any side effect somes with this change. Need more test units to confirm this. Signed-off-by: Kenji Chen <kenji.chen@intel.com> Change-Id: I2399e33d2ca3defe8cd9b1f94ab0af1db7f84635 Reviewed-on: https://chromium-review.googlesource.com/225557 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Mohammed Habibulla <moch@chromium.org>
* samus: change fan RPM values, enable fast-startBill Richardson2014-10-221-5/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Updating the fan speeds according to the manufacturer's specs. The fan vendor recommends that the minimum fan speed be a 20% duty cycle. Since the built-in fan controller has a tach-based feedback loop, I'm using the RPM value instead of the duty cycle (20% is 2286 RPM, according to the vendor). The vendor also wants a 30% duty cycle to start turning, but the built-in fan controller provides support for fast-start too. The controller's minimum fast-start duty cycle is 50%, but it also has a programmable number of revolutions that it will wait before backing off. Holding my ear down close to the fans while they start and stop, it seems that the minimum 2 revolution start period is sufficient and provides the least noise. Of course, since I've never had any problems starting the fans directly at 1000 RPM this noise is a little more noticeable than that. It's quite possible that the built-in controller is smart enough to make 1000 RPM work by bumping the duty cycle up until the fans turn even if the fans don't like it. BUG=chrome-os-partner:32892 BRANCH=ToT,samus TEST=manual Listen closely and run the EC console "faninfo" command to see the fans start and stop as the system boots and idles. Change-Id: I47c9e7cef3f9f4bd815a13032fe10234decd62ed Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/224830 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Fix incorrect valid and writable flash flagsVic Yang2014-10-151-0/+26
| | | | | | | | | | | | | | | | The valid and writable flags the EC sends back to the AP are incorrect. They are a little bit different on differnt chips, so let's move it to flash physical layer. This is not any causing problem, but we should fix this. BUG=chrome-os-partner:32745 TEST=make buildall BRANCH=samus Change-Id: Ibcda5ae770f5ea02cde094490997a5bc447df88f Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/222661 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* EC: Add smbus interface read & write APIsSheng-Liang Song2014-08-291-0/+5
| | | | | | | | | | | | | | | | | | Ref: http://smbus.org/specs/smbus20.pdf - Support software CRC8 generation and checking. - Support read/write word (2-bytes) - Support read/write blocks (up to 32 bytes) BUG=chrome-os-partner:24741 BRANCH=ToT,glimmer TEST=Verified with smart battery firmware update application on glimmer. Passed LGC & Simplo Battery. Change-Id: Ic2e7f759af80c06741ed49fee1826213429fbf8a Signed-off-by: Sheng-Liang Song <ssl@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/209747 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* lm4 i2c: fixed lm4 i2c_xfer synchronization issueSheng-Liang Song2014-08-262-3/+8
| | | | | | | | | | | | | | Added atomic or/clear when modify a share register LM4_SYSTEM_SRI2C_ADDR among different i2c ports. BUG=None BRANCH=ToT TEST=Verified on Samus. Signed-off-by: Sheng-Liang Song <ssl@chromium.org> Change-Id: Ibf64b05a800ce2b8ddf9735bd3a762ab02031bc8 Reviewed-on: https://chromium-review.googlesource.com/213196 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* Auron: Initial EC commitMohammed Habibulla2014-08-201-0/+11
| | | | | | | | | | | | | | Clone of Peppy with only string changes BUG=chrome-os-partner:31285 TEST=emerge-auron chromeos-ec BRANCH=none Change-Id: I1f7288e44cdc5ff1caa41de5ee299dbfa3411fa1 Signed-off-by: Mohammed Habibulla <moch@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/212971 Reviewed-by: Bernie Thompson <bhthompson@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* openocd: update configuration filesDominic Chen2014-08-156-75/+31
| | | | | | | | | | | | | | | | | 1. use ftdi interface driver instead of deprecated ft2232 2. remove custom target config and use upstream stellaris target 3. replaced deprecated servo_v2.cfg with servo_v2_slower.cfg 4. deprecated openocd.cfg BUG=none BRANCH=none TEST=flash samus works CQ-DEPEND=CL:210778 Change-Id: I572a717613eedc3afc44009a0f1aba1f1d36d7f7 Signed-off-by: Dominic Chen <ddchen@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/210920 Reviewed-by: Todd Broch <tbroch@chromium.org>
* i2c: add support for timeout configuration at runtimeRandall Spangler2014-07-301-3/+12
| | | | | | | | | | | | | | | | | When the EC sends longer commands to the PD chip (such as flash erase/write over the passthru from AP), allow it to take a second instead of the default 100ms timeout. BUG=chrome-os-partner:30935 BRANCH=none TEST=samus boots battery command works from EC console ectool passthru of flash erase to PD works (requires hacked ectool) Change-Id: I08ff94f7ac6aee351aa73c9d28b5fd715d463b3a Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/209936 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* watchdog: Give more leeway to the independent watchdogDoug Anderson2014-06-231-1/+2
| | | | | | | | | | | | | | | | | | | | | | It would be really nice to be guaranteed to see watchdog warnings before we actually hit a watchdog reset even if something strange is going on with the CPU. Let's increase the margin between the timer and the independent so that the hardware watchdog is really hit as a last resort. It seems like a 1.6 second hardware watchdog wouldn't be the end of the world so let's bump that way rather than increasing the number of warnings. BRANCH=ToT BUG=chrome-os-partner:29162 TEST="waitms 1000" on EC console no longer ever reboots and "waitms 2000" usually does. Change-Id: Ic5e5ddec22fb8484cc7c552b19d3f2043c105d0c Signed-off-by: Doug Anderson <dianders@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/204895 Reviewed-by: Randall Spangler <rspangler@chromium.org>
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