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In the interest of making long-term branch maintenance incur as little
technical debt on us as possible, we should not maintain any files on
the branch we are not actually using.
This has the added effect of making it extremely clear when merging CLs
from the main branch when changes have the possibility to affect us.
The follow-on CL adds a convenience script to actually pull updates from
the main branch and generate a CL for the update.
BUG=b:204206272
BRANCH=ish
TEST=make BOARD=arcada_ish && make BOARD=drallion_ish
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I17e4694c38219b5a0823e0a3e55a28d1348f4b18
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3262038
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Tom Hughes <tomhughes@chromium.org>
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This requests that cros lint (and repo upload hook) use the new
Chromium OS 4 space indent policy.
Since legacy python scripts still use 2 space, I added pylint ignore
statements to the individual files to disable indentation checking.
Note: There are still valid pylint errors in some of these legacy scripts.
BRANCH=none
BUG=none
TEST=cros lint util/*.py
Signed-off-by: Craig Hesling <hesling@chromium.org>
Change-Id: I439f5a87bc50f1f43a4996e574bbc0626922a88e
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3064761
Reviewed-by: Mike Frysinger <vapier@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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MEC152x SPI image layout is different due to optional
Secure Boot features. A MEC152x specific image generator
script was added with make rules to to select the script
based on chip family.
BRANCH=none
BUG=b:177463787
TEST=Booted skylake RVP to Chrome OS
Signed-off-by: Scott Worley <scott.worley@microchip.corp-partner.google.com>
Change-Id: I621e5b6e8f06f44467ea2761d9bca768c0635c72
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2601208
Reviewed-by: Ravin Kumar <ravin.kumar@microchip.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Ravin Kumar <ravin.kumar@microchip.com>
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