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* adc: Include adc_chip.h from adc.hCaveh Jalali2021-08-272-7/+0
| | | | | | | | | | | | | | | | This reorganizes adc.h and adc_chip.h so that general code only needs to know about adc.h. adc_chip.h is now included by adc.h directly and does not need to be included in general code. BRANCH=none BUG=b:181271666 TEST=buildall passes (with next patch in series) Cq-Depend: chromium:3120316 Change-Id: I8bc107c6900e831a57f7a7fb8668eb08bb179d6c Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3120315 Reviewed-by: Keith Short <keithshort@chromium.org>
* common: move standard library functions from util.c to another fileMichał Barnaś2021-08-251-1/+1
| | | | | | | | | | | | | | | | | | This commit moves some of the standard library functions from util.c file to util_stdlib.c file. It will allow to use util.c for both CrOS EC and Zephyr builds and will make shim util file unnecessary. BRANCH=main BUG=b:177096231 TEST=Build both, CrOS EC and Zephyr firmwares Compilation should finish without any problems After flashing, both versions work as they should Change-Id: If6f930a04d28bec35faa16759f43b36176bf3de7 Signed-off-by: Michał Barnaś <mb@semihalf.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3081827 Commit-Queue: Keith Short <keithshort@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org>
* system: fix system_get_scratchpad APIYuval Peress2021-08-201-2/+3
| | | | | | | | | | | | | | | The current API for system_get_scratchpad mixes the status and the value being read. Update the signature to allow both. BRANCH=none BUG=b:195481980 TEST=make testall && zmake testall Signed-off-by: Yuval Peress <peress@chromium.org> Change-Id: I3a5f5ad523d507c53a5d474806f58afafb82e70c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3074828 Commit-Queue: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Denis Brockus <dbrockus@chromium.org>
* mchp: Update RPM-PWM registers and configurationmartin yan2021-08-193-12/+23
| | | | | | | | | | | | | | | Update RPM-PWM block's registers and configuration as POR, RPM based Fan Control Algorithm via RPM-PWM hardware block is not supported or validated in previous mchp projects. BUG=none BRANCH=none TEST=Tested on ADL RVP and MCHP1727 MECC system via UART console Signed-off-by: martin yan <martin.yan@microchip.corp-partner.google.com> Change-Id: Ibe15dfbec4f2c2d4558d27c8b101345ad81a09f3 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3100925 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* mchp: Optimize spi_flash_read() APImartin yan2021-08-061-0/+12
| | | | | | | | | | | | | | | | | | Optimize SPI flash read timing, MEC172x QMSPI controller controls CS# by hardware, it will add several system clock cycles delay between CS deassertion to CS assertion at the start of the next transaction, this guarantees SPI back to back transactions, so 1ms delay can be removed to optimze timing. BUG=none BRANCH=none TEST=Tested on ADL RVP and MCHP1727 MECC system via FAFT ECBootTime job save 720ms as EC performs 180KB RW code's SHA256 hash computation Signed-off-by: martin yan <martin.yan@microchip.corp-partner.google.com> Change-Id: I5cf9c668efb1cd008b91cdd8aa09f7351c017af0 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3074767 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* pylintrc: Copy Chromium OS platform2's configCraig Hesling2021-08-023-0/+12
| | | | | | | | | | | | | | | | | | | | This requests that cros lint (and repo upload hook) use the new Chromium OS 4 space indent policy. Since legacy python scripts still use 2 space, I added pylint ignore statements to the individual files to disable indentation checking. Note: There are still valid pylint errors in some of these legacy scripts. BRANCH=none BUG=none TEST=cros lint util/*.py Signed-off-by: Craig Hesling <hesling@chromium.org> Change-Id: I439f5a87bc50f1f43a4996e574bbc0626922a88e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3064761 Reviewed-by: Mike Frysinger <vapier@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* mchp: Correct integrated SPI flash pins' configurationmartin yan2021-07-141-2/+2
| | | | | | | | | | | | | | | | | | | Corrected MEC1727 integrated SPI flash CS# (GPIO116) and CLK (GPIO117) alternative function as 1 (Internal SPI functionality) from 2 (General purpose SPI functionality). BUG=none BRANCH=none TEST=Tested on ADL RVP via EC UART console > sysjump RW: able to switch to RW from RO > sysjump RO: able to switch to RO from RW Signed-off-by: martin yan <martin.yan@microchip.corp-partner.google.com> Change-Id: I870925183e670022dc023812265a7ef496b5f255 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3021101 Reviewed-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* mchp: Correct assigning I2C controller to a portVijay Hiremath2021-06-302-3/+15
| | | | | | | | | | | | | | | | | | Corrected default assignment of controller to I2C port based on the number of I2C ports being used rather than the port in use. This avoids overlapping of I2C controller assignment when the I2C ports used are not greater than MCHP_I2C_CTRL_MAX. BUG=none BRANCH=none TEST=Tested on ADLRVP, default I2C controller assignment is correct. Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Change-Id: I875b0f7e94162f923325e9ed07e7549cc760fdf8 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2980432 Reviewed-by: Martin Yan <martin.yan@microchip.corp-partner.google.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* mchp: Move I2C_CONTROLLER_COUNT and I2C_PORT_COUNT to chipmartin yan2021-06-302-0/+8
| | | | | | | | | | | | | | | | | | Move I2C_CONTROLLER_COUNT and I2C_PORT_COUNT to registers-mec172x.h and registers-mec152x.h from board.h, both are chip specific BRANCH=none BUG=none TEST=Tested adlrvpp_mchp1727 and sklrvp_mchp1723 adlrvpp_mchp1521 and sklrvp_mchp Signed-off-by: martin yan <martin.yan@microchip.corp-partner.google.com> Change-Id: Icd91e9877e0053c83c1a73d10470ffefedd90a01 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2982390 Reviewed-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* mchp: Add ADC MAX reading value for MEC172xmartin yan2021-06-101-0/+5
| | | | | | | | | | | | | | | | | | | Update ADC_READ_MAX for MEC172x, its ADC is 12BIT resolution in default BRANCH=none BUG=b:190518298 TEST=Tested on ADL RVP via UART console > temps Ambient : 300 K = 27 C 34% DDR : 299 K = 26 C 31% Skin : 301 K = 28 C 37% VR : 297 K = 24 C 25% Signed-off-by: martin yan <martin.yan@microchip.corp-partner.google.com> Change-Id: If657d79d989b017fb34df437e28ceed291c9e1d3 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2935558 Reviewed-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* mchp: Update stack size MACROsmartin yan2021-06-101-5/+6
| | | | | | | | | | | | | | | | add ULTRA_TASK_STACK_SIZE and TRENTA_TASK_STACK_SIZE for PD tasks which requires larger stack size, and reduce other stack sizes which were configured for development purpose BRANCH=none BUG=none TEST=make buildall -j Signed-off-by: martin yan <martin.yan@microchip.corp-partner.google.com> Change-Id: Ib055253a9a8e45da46b81f8f1ea2e60a8f738484 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2945630 Reviewed-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* include/flash: rename the APIsTim Lin2021-06-091-12/+12
| | | | | | | | | | | | | | | | The names conflict when enabling both Zephyr's flash driver and CONFIG_FLASH_CROS option. Rename all the APIs in include/flash.h BUG=b:187192628 BRANCH=none TEST=make buildall -j4 Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com> Change-Id: If1fd0ea28fa9f5cec1c1daa8f72f63eb7a0e6500 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2931749 Commit-Queue: Keith Short <keithshort@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Denis Brockus <dbrockus@chromium.org>
* COIL: espi: replace VW_SLAVE_BTLD_STATUS_DONE with ↵Caveh Jalali2021-06-041-25/+25
| | | | | | | | | | | | | | | | | VW_PERIPHERAL_BTLD_STATUS_DONE This replaces VW_SLAVE_BTLD_STATUS_DONE with VW_PERIPHERAL_BTLD_STATUS_DONE. BRANCH=none BUG=b:163885307 TEST=buildall, compare_build.sh pass Change-Id: I0b8c71fa7e590dc89357e22aafce0b67717af183 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2938041 Reviewed-by: Harry Cutts <hcutts@chromium.org> Commit-Queue: Harry Cutts <hcutts@chromium.org>
* COIL: Rename MODULE_SPI_MASTER to MODULE_SPI_CONTROLLERCaveh Jalali2021-06-031-2/+2
| | | | | | | | | | | | | | | | This renames the MODULE_SPI_MASTER to MODULE_SPI_CONTROLLER. BRANCH=none BUG=b:181607131 TEST=make buildall passes; "compare_build.sh -b all" shows no difference Change-Id: I4d33f57fd82c5b57f111c12387113dc82cebe60b Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2932466 Reviewed-by: Craig Hesling <hesling@chromium.org> Reviewed-by: Harry Cutts <hcutts@chromium.org> Commit-Queue: Craig Hesling <hesling@chromium.org>
* mchp: Default espi configurationPoornima Tom2021-05-202-29/+38
| | | | | | | | | | | | | | | | In ESPI communication, when no specific configs are defined, the default configuration must use Maximum frequency, all channels and all modes. BUG=b:186669325 BRANCH=none TEST=make buildall -j Signed-off-by: Poornima Tom <poornima.tom@intel.com> Change-Id: I61caa65f22d394093bfd1ebd39c9d065d5c1b2d0 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2784334 Tested-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: caveh jalali <caveh@chromium.org>
* mchp: Add lfw/gpio.inc in chipmartin yan2021-04-152-1/+108
| | | | | | | | | | | | | | | | | Add gpio.inc in chip, and update build.mk; Delete lfw/gpio.inc under all mchp boards; BRANCH=none BUG=none TEST=Build sklrvp_mchp172x. Signed-off-by: martin yan <martin.yan@microchip.corp-partner.google.com> Change-Id: Icd98d4d93cb31f70592d6668e598fbc88e727450 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2810884 Reviewed-by: Martin Yan <Martin.Yan@microchip.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* mchp: Add i2c_chip.h and board_i2c_p2c() in chipmartin yan2021-04-052-0/+39
| | | | | | | | | | | | | | | | Add board_i2c_p2c() which returns default I2C controller for i2c but this function can be overridden by board BRANCH=none BUG=none TEST=Build sklrvp_mchp172x. Signed-off-by: martin yan <martin.yan@microchip.corp-partner.google.com> Change-Id: I88740517f11c6afcfc1edb37a59bbf04f336f655 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2800091 Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* mchp: Move general flash definitions into chipmartin yan2021-04-051-0/+16
| | | | | | | | | | | | | | | | | | | | | Move general flash definitions: CONFIG_SPI_FLASH_PORT CONFIG_SPI_FLASH into config_chip.h Redefine CONFIG_FLASH_SIZE_BYTES per MEC1727 with integrated SPI flash BRANCH=none BUG=none TEST=Build MEC170x/MEC152x boards and sklrvp_mchp172x. Signed-off-by: martin yan <martin.yan@microchip.corp-partner.google.com> Change-Id: I2dc9af69b0794ec2e3ec11c45be9ff74aa19f561 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2799977 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Ravin Kumar <ravin.kumar@microchip.com> Tested-by: Ravin Kumar <ravin.kumar@microchip.com> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* mchp: Update number of I2C controllers for MEC172xScott Worley2021-03-301-40/+54
| | | | | | | | | | | | | | | | | | | | MEC172x has five I2C controllers whereas MEC152x has eight and MEC170x has four. Updated controller arrays and interrupt service routines. BRANCH=none BUG=none TEST=Build MCHP MEC170x and MEC152x boards Signed-off-by: Scott Worley <scott.worley@microchip.corp-partner.google.com> Change-Id: I087240b9420e2e495fab901a0738a8c58f94d243 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2748854 Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Martin Yan <martin.yan@microchip.corp-partner.google.com> Reviewed-by: Ravin Kumar <ravin.kumar@microchip.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Ravin Kumar <ravin.kumar@microchip.com> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* mchp: Update chip clock and system code for MEC172xScott Worley2021-03-302-72/+195
| | | | | | | | | | | | | | | | | | | | | | | | Add minor MEC172x changes to chip level clock and system code. MEC172x implements different 32 KHz clock source selection including hardware to test and monitor the 32 KHz input source if desired. Change hard coded EC clock divider values to defined values from chip specific header files. Add MEC172x chip ID strings. Minor tweak to sleep entry and exit: MEC172x new port 80h capture hardware does not need to be manually enabled/disabled in sleep sequence. BRANCH=none BUG=none TEST=Build MCHP MEC170x and MEC152x boards Signed-off-by: Scott Worley <scott.worley@microchip.corp-partner.google.com> Change-Id: I46bd3a12541f71f575a0a7af4e07734b74259679 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2748794 Reviewed-by: Martin Yan <martin.yan@microchip.corp-partner.google.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Ravin Kumar <ravin.kumar@microchip.com> Tested-by: Martin Yan <martin.yan@microchip.corp-partner.google.com> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* mchp: Add MEC172x build filesScott Worley2021-03-303-0/+949
| | | | | | | | | | | | | | | | | | | | Update chip build rules for MEC172x. Add a new little-firmware (LFW) linker file supporting the larger SRAM size of MEC172x. Add a new python SPI image generator for MEC172x new SPI layout (no flash-map). BRANCH=none BUG=none TEST=Build MEC170x and MEC152x boards Signed-off-by: Scott Worley <scott.worley@microchip.corp-partner.google.com> Change-Id: I9ff2302ca99d4e7296acdb8352849f5cd355adf0 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2749674 Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Martin Yan <martin.yan@microchip.corp-partner.google.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Ravin Kumar <ravin.kumar@microchip.com> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Martin Yan <martin.yan@microchip.corp-partner.google.com>
* mchp: MEC172x update Port 80h and ACPI ECScott Worley2021-03-302-24/+84
| | | | | | | | | | | | | | | | | | | | | | | | Update the number of ACPI EC instances: MEC172x and MEC170x implement 5 whereas MEC152x implements 4. Update Port 80h capture code for MEC172x BIOS Debug Port (BDP) implementation. BDP implements a 32 entry FIFO storing 16 bit entries. Each entry contains the data byte and flags indicating byte lane and FIFO status. BDP does not include the time stamp counter of MEC170x/MEC152x Port 80h capture hardware. BRANCH=none BUG=none TEST=Build MCHP MEC170x and MEC15x boards Signed-off-by: Scott Worley <scott.worley@microchip.corp-partner.google.com> Change-Id: I145619bc16dc1ed292e0c2b3d3d3fe9c6d8ed81d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2749515 Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Martin Yan <martin.yan@microchip.corp-partner.google.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Ravin Kumar <ravin.kumar@microchip.com> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Martin Yan <martin.yan@microchip.corp-partner.google.com>
* mchp: PWM add MEC172x and clean upScott Worley2021-03-304-74/+60
| | | | | | | | | | | | | | | | | | | | | Add MEC172x PWM support and clean up the hard coded PWM PCR numeric values with PWM PCR register defines for (SZ) 144 pin parts. MEC1701, MEC152x, and MEC172x 144 pin parts have 9 PWM's. MEC152x and MEC172x have 4 TACH's. MEC1701 has 3 TACH's. BRANCH=none BUG=none TEST=Build MCHP MEC170x and MEC152x boards Signed-off-by: Scott Worley <scott.worley@microchip.corp-partner.google.com> Change-Id: Ibd69d6391975668186679812ff74435856baea60 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2748856 Reviewed-by: Martin Yan <martin.yan@microchip.corp-partner.google.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Ravin Kumar <ravin.kumar@microchip.com> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Martin Yan <martin.yan@microchip.corp-partner.google.com>
* mchp: Update chip watchdog timer for MEC172xScott Worley2021-03-301-55/+72
| | | | | | | | | | | | | | | | | | | | MEC172x uses the same watchdog timer hardware as MEC152x. Update the macro logic to build same code for both MEC152x and MEC172x. Fix bug in debug configuration: modify control register instead of overwriting. BRANCH=none BUG=none TEST=Build MCHP MEC170x and MEC152x boards Signed-off-by: Scott Worley <scott.worley@microchip.corp-partner.google.com> Change-Id: I407fa0b4ed0acc33e4d86a980749b64cd7465ac8 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2748795 Reviewed-by: Martin Yan <martin.yan@microchip.corp-partner.google.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Ravin Kumar <ravin.kumar@microchip.com> Tested-by: Martin Yan <martin.yan@microchip.corp-partner.google.com> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* mchp: Update chip configuration and flash layout for MEC172xScott Worley2021-03-132-24/+42
| | | | | | | | | | | | | | | | | | | Adding MEC172x specific changes to chip configuration and flash layout header files. MEC172x Boot-ROM loader SPI flash layout is different from previous chips. BRANCH=none BUG=none TEST=Build MCHP MEC170x and MEC152x boards Signed-off-by: Scott Worley <scott.worley@microchip.corp-partner.google.com> Change-Id: Id02cdeac8131844e948799c0c9de4f45c47d4d73 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2747654 Reviewed-by: Martin Yan <martin.yan@microchip.corp-partner.google.com> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Ravin Kumar <ravin.kumar@microchip.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Martin Yan <martin.yan@microchip.corp-partner.google.com>
* mchp: Add Microchip MEC172x registersScott Worley2021-03-134-66/+1536
| | | | | | | | | | | | | | | | | | | | Microchip MEC172xN is an EC with 416KB total SRAM with eSPI and SPI Host interfaces. The CPU is an ARM Cortex-M4 with FPU, 8 region MPU, and maximum frequency of 96 MHz. This change also adds common CPU clock divider defines for all MEC chips and moves the DMA API struct to the common register header. BRANCH=none BUG=none TEST=Build MCHP MEC170x and MEC152x boards Signed-off-by: Scott Worley <scott.worley@microchip.corp-partner.google.com> Change-Id: Ie159a4addf0bbcd30404339944d5b1695482ab6c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2746438 Reviewed-by: Ravin Kumar <ravin.kumar@microchip.com> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Martin Yan <martin.yan@microchip.corp-partner.google.com>
* mchp: Disable BGPO on pin used in GPIO listScott Worley2021-03-034-0/+65
| | | | | | | | | | | | | | | | | | | | | Microchip MEC parts have a small number of GPIO pins that default to a mode controlled by VBAT powered logic. When configured for VBAT operation the GPIO control register is bypassed. This change switches any of these pins in the GPIO list back to GPIO control. BRANCH=none BUG=none TEST=Manually check pins are no longer controlled by VBAT logic. Signed-off-by: Scott Worley <scott.worley@microchip.corp-partner.google.com> Change-Id: I2d78365b61616ccce568810aecd81fe882e90200 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2717742 Reviewed-by: Ravin Kumar <ravin.kumar@microchip.com> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Poornima Tom <poornima.tom@intel.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Poornima Tom <poornima.tom@intel.com> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* mchp: Add ADC channel enumeration to chipScott Worley2021-02-101-0/+13
| | | | | | | | | | | | | | | Add a chip level ADC channel enumerated type. BRANCH=none BUG=b:177463787 TEST=Booted skylake RVP to Chrome OS Signed-off-by: Scott Worley <scott.worley@microchip.corp-partner.google.com> Change-Id: If30a71698b1d084380c6695e4c4b8921f5b8eec2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2673019 Reviewed-by: Ravin Kumar <ravin.kumar@microchip.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Ravin Kumar <ravin.kumar@microchip.com>
* mchp: MEC152x update PWM instancesScott Worley2021-02-101-4/+11
| | | | | | | | | | | | | | | | | Adjust chip PWM code for the different number of PWM instances based upon chip family. BRANCH=none BUG=b:177463787 TEST=Booted skylake RVP to Chrome OS Signed-off-by: Scott Worley <scott.worley@microchip.corp-partner.google.com> Change-Id: Ie42bb99120d2811f81a49678102a78f8a1ce868b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2601209 Reviewed-by: Ravin Kumar <ravin.kumar@microchip.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Ravin Kumar <ravin.kumar@microchip.com>
* mchp: Add MEC152x SPI image generator scriptScott Worley2021-02-102-1/+806
| | | | | | | | | | | | | | | | | | | MEC152x SPI image layout is different due to optional Secure Boot features. A MEC152x specific image generator script was added with make rules to to select the script based on chip family. BRANCH=none BUG=b:177463787 TEST=Booted skylake RVP to Chrome OS Signed-off-by: Scott Worley <scott.worley@microchip.corp-partner.google.com> Change-Id: I621e5b6e8f06f44467ea2761d9bca768c0635c72 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2601208 Reviewed-by: Ravin Kumar <ravin.kumar@microchip.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Ravin Kumar <ravin.kumar@microchip.com>
* mchp: Support any chip UART for EC consoleScott Worley2021-02-102-80/+127
| | | | | | | | | | | | | | | | | | | MEC170X and MEC152X have two and three UART's respectively. Add board level EC console selection configuration item. Add chip level support for using the selected UART in both main EC and little-firmware EC code. BRANCH=none BUG=b:177463787 TEST=Booted skylake RVP to Chrome OS Signed-off-by: Scott Worley <scott.worley@microchip.corp-partner.google.com> Change-Id: I3446d4683bff9cea73d5881ef909cb2f5cd1ebaa Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2601207 Reviewed-by: Ravin Kumar <ravin.kumar@microchip.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Ravin Kumar <ravin.kumar@microchip.com>
* mchp: MEC152X watchdog interrupt supportScott Worley2021-02-101-9/+81
| | | | | | | | | | | | | | | | | | MEC152X watchdog timer can fire an EC interrupt. Update watchdog code to use EC interrupt and not use 16-bit timer used for MEC170X. BRANCH=none BUG=b:177463787 TEST=Booted skylake RVP to Chrome OS Signed-off-by: Scott Worley <scott.worley@microchip.corp-partner.google.com> Change-Id: I16ed7c6e7140f6d3fbda190e3bcb0565ce13e70f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2601206 Reviewed-by: Ravin Kumar <ravin.kumar@microchip.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Ravin Kumar <ravin.kumar@microchip.com>
* mchp: MEC152x eSPI adjust number of ACPI EC instancesScott Worley2021-02-102-65/+29
| | | | | | | | | | | | | | | | | | MEC152X has one fewer ACPI EC instance than MEC170X. Adjust ACPI EC initialization tables. Update KBC enable for eSPI mode. Remove MCHP debug trace statements. BRANCH=none BUG=b:177463787 TEST=Booted skylake RVP to Chrome OS Signed-off-by: Scott Worley <scott.worley@microchip.corp-partner.google.com> Change-Id: I97bed09f4eb949e47bc792a76f3bb4d626b8c5b2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2601205 Reviewed-by: Ravin Kumar <ravin.kumar@microchip.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Ravin Kumar <ravin.kumar@microchip.com>
* mchp: MEC152X does not have GP-SPI controllerScott Worley2021-02-101-1/+3
| | | | | | | | | | | | | | | | | | MEC152X does not implement the general purpose SPI controllers only the QMSPI controller. Add guard logic to print build error if GP-SPI is mistakenly enabled. BRANCH=none BUG=b:177463787 TEST=Booted skylake RVP to Chrome OS Signed-off-by: Scott Worley <scott.worley@microchip.corp-partner.google.com> Change-Id: Id5d789063d50d9edb6f731c1f1f38a1bda8cb93e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2601204 Reviewed-by: Ravin Kumar <ravin.kumar@microchip.com> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Ravin Kumar <ravin.kumar@microchip.com>
* mchp: MEC152x increase number of I2C controllersScott Worley2021-02-101-159/+259
| | | | | | | | | | | | | | | | | | Microchip MEC152x has eight I2C controllers. The first five include network layer DMA options the remaining three do not. The current I2C driver does not use network layer therefore we updated the driver to support all I2C controllers available. BRANCH=none BUG=b:177463787 TEST=Booted skylake RVP to Chrome OS Signed-off-by: Scott Worley <scott.worley@microchip.corp-partner.google.com> Change-Id: I30ebfa55faf8e3bdc02373726ad6ca5f696e77e2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2601203 Reviewed-by: Ravin Kumar <ravin.kumar@microchip.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Ravin Kumar <ravin.kumar@microchip.com>
* mchp: MEC152x chip level GPIO updatesScott Worley2021-02-103-18/+32
| | | | | | | | | | | | | | | | | | | | | | | | Add support for the unimplemented pin macro. MEC152x GPIO control includes an input pad disable feature enabled by default to reduce leakage. We add logic to enable the input pad when the pin is configured. Note when pad input is disabled the pin can be used as output, reading the input value always returns 0, and interrupt detection is disabled. MEC170x does not implement input pad disable bit. Added a bit define with value 0 to MEC170x register file so that no condition compile logic is required. BRANCH=none BUG=b:177463787 TEST=Booted skylake RVP to Chrome OS Signed-off-by: Scott Worley <scott.worley@microchip.corp-partner.google.com> Change-Id: Ie5ce58a698311328012440d76eedb1f2ce768d0e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2601202 Reviewed-by: Ravin Kumar <ravin.kumar@microchip.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Ravin Kumar <ravin.kumar@microchip.com>
* mchp: MEC152x clock configuration and system updatesScott Worley2021-02-103-116/+119
| | | | | | | | | | | | | | | | | | | Add MEC152x changes to clock configuration and system ID. Update PCR reset status bits to match chip documentation. NOTE: chip RESET_SYS is triggered by any of VTR power rail reset, nRESET_IN pin, WDT event, EC firmware writing PCR SOFT_SYS_RESET bit, or ARM Cortex-M4 SYSRESETREQ. BRANCH=none BUG=b:177463787 TEST=Booted skylake RVP to Chrome OS Signed-off-by: Scott Worley <scott.worley@microchip.corp-partner.google.com> Change-Id: Ie3befba1bf22f0d00746037aef4892d43f4b9f37 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2601201 Reviewed-by: Ravin Kumar <ravin.kumar@microchip.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Ravin Kumar <ravin.kumar@microchip.com>
* mchp: MEC152x chip configuration and flash layout changesScott Worley2021-02-102-9/+28
| | | | | | | | | | | | | | | | | | Update chip configuration and flash layout for MEC152x. MEC152x Boot-ROM SPI loader uses a different SPI image header layout. BRANCH=none BUG=b:177463787 TEST=Booted skylake RVP to Chrome OS Signed-off-by: Scott Worley <scott.worley@microchip.corp-partner.google.com> Change-Id: Ib88960e545b50d5f4c7906eea85dcee736fee31b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2601200 Reviewed-by: Ravin Kumar <ravin.kumar@microchip.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Ravin Kumar <ravin.kumar@microchip.com>
* mchp: MEC152x chip family updateScott Worley2021-02-101-1/+1
| | | | | | | | | | | | | | | | | | | Make chip family nomenclature more consistent by changing the MEC1701 MEC17XX family name to MEC170X family. This change will make future MEC172X support be similar to MEC152X. BRANCH=none BUG=b:177463787 TEST=Booted skylake RVP to Chrome OS Signed-off-by: Scott Worley <scott.worley@microchip.corp-partner.google.com> Change-Id: Id5fbd20fdb1f612dfd7ca6a35b7d33c0922555d7 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2601199 Reviewed-by: Ravin Kumar <ravin.kumar@microchip.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Ravin Kumar <ravin.kumar@microchip.com>
* mchp: Add Microchip MEC152x register changesScott Worley2021-02-103-1767/+3054
| | | | | | | | | | | | | | | | | | | Microchip MEC152x is an EC with eSPI and SPI Host interface (no LPC) and a new Boot-ROM SPI loader. This commit modifies the chip level register header to include MEC1701 or MEC152x register definitions based upon chip family. BRANCH=none BUG=b:177463787 TEST=Booted skylake RVP to Chrome OS Signed-off-by: Scott Worley <scott.worley@microchip.corp-partner.google.com> Change-Id: I4c4788012a339f81b8b8fe754cbc2986c08961a1 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2601198 Reviewed-by: Ravin Kumar <ravin.kumar@microchip.com> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Ravin Kumar <ravin.kumar@microchip.com>
* spi: Pass in spi_device as argument to spi_enable instead of portTom Hughes2021-01-283-16/+11
| | | | | | | | | | | | | | | | | | | | | | Rather than passing in the port and iterating over the global spi_devices variable, pass in the specific spi_device that is being enabled/disabled. The spi_device_t struct has the port. This change makes the functions in spi.h more consistent since they now all take a spi_device_t*. This change is the first step in making the SPI configuration more dynamic. BRANCH=none BUG=b:177908650 TEST=git grep 'spi_enable(CONFIG' => no results TEST=make buildall TEST=Flash dragonclaw v0.2 and view console to verify FP sensor ID Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: I64124e0ebcf898e88496acb77703b5f59ae931c2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2654081 Commit-Queue: Abe Levkoy <alevkoy@chromium.org> Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
* Refactor CONFIG_FLASH_SIZE to CONFIG_FLASH_SIZE_BYTESYuval Peress2021-01-151-1/+1
| | | | | | | | | | | | | | | | | | | | | In Zephyr CONFIG_FLASH_SIZE is a Kconfig value that is used throughout. The issue is that the units don't match. In Zephyr the value is in KiB instead of bytes. This refactor simply renames CONFIG_FLASH_SIZE in platform/ec to include the unit (via _BYTES). BRANCH=none BUG=b:174873770 TEST=make buildall be generated by the build instead of per board Signed-off-by: Yuval Peress <peress@chromium.org> Change-Id: I44bf3c7a20fcf62aaa9ae15715be78db4210f384 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2627638 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Hughes <tomhughes@chromium.org> Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
* version: Rename version.h to cros_version.hYuval Peress2021-01-071-1/+1
| | | | | | | | | | | | | | | This change simply moves the include/version.h file over to avoid a naming collision with zephyr's version.h. BRANCH=none BUG=b:167392037 TEST=make buildall -j Signed-off-by: Yuval Peress <peress@chromium.org> Change-Id: Ib41b3c21817d5f81e713d3b550bc46a0d1c55cf8 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2612772 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
* task_set_event: remove the wait argumentDawid Niedzwiecki2020-12-141-1/+1
| | | | | | | | | | | | | | | | | | | | There is an option in the task_set_event function which force the calling task to wait for an event. However, the option is never used thus remove it. This also will help in the Zephyr migration process. BUG=b:172360521 BRANCH=none TEST=make buildall Signed-off-by: Dawid Niedzwiecki <dn@semihalf.com> Change-Id: Ic152fd3d6862d487bcc0024c48d136556c0b81bc Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2521599 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Tom Hughes <tomhughes@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
* Replace I2C_GET_ADDR with I2C_STRIP_FLAGSYuval Peress2020-11-021-1/+1
| | | | | | | | | | | | | | | | | The new I2C_STRIP_FLAGS macro was added to avoid conflict with Zephyr's macro. This CL performs the migration to that new API. BRANCH=none BUG=b:172067439 TEST=make runtests -j and built for various boards: eve, volteer, arcada_ish, atlas, hatch, kohaku, nocturne, samus, and scarlet Change-Id: I0583b647435db96ec268f186252b367bdc4118a6 Signed-off-by: Yuval Peress <peress@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2511097 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Commit-Queue: Jett Rink <jettrink@chromium.org>
* Replace __attribute__((noreturn)) with noreturnTom Hughes2020-08-172-4/+8
| | | | | | | | | | | | | | | _Noreturn was added in C11 and the convenience macro "noreturn" is specified by stdnoreturn.h: https://en.cppreference.com/w/c/language/_Noreturn. BRANCH=none BUG=none TEST=make buildall -j Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: I30361bb5290cea1c776a7356f7e3a68edf1f8e39 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2324816 Reviewed-by: Ting Shen <phoenixshen@chromium.org>
* chip: support dynamic hibernate_wake_pins configTing Shen2020-08-061-0/+5
| | | | | | | | | | | | | | | | Add CONFIG_HIBERNATE_WAKE_PINS_DYNAMIC to let board config their wake pins at runtime. BUG=b:162814191 TEST=make BRANCH=master Signed-off-by: Ting Shen <phoenixshen@google.com> Change-Id: Iae2072ec7239a0daa84222c23733b90153e732f1 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2340730 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Commit-Queue: Ting Shen <phoenixshen@chromium.org> Tested-by: Ting Shen <phoenixshen@chromium.org>
* ec: change usage of dummySam Hurst2020-08-058-26/+26
| | | | | | | | | | | | | | | | | | Google is working to change its source code to use more inclusive language. To that end, replace the term "dummy" with inclusive alternatives. BUG=b:162781382 BRANCH=None TEST=make -j buildall `grep -ir dummy *` The only results are in "private/nordic_keyboard/sdk8.0.0" which is not our code. Signed-off-by: Sam Hurst <shurst@google.com> Change-Id: I6a42183d998e4db4bb61625f962867fda10722e2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2335737 Reviewed-by: Tom Hughes <tomhughes@chromium.org>
* mchp: Add chip_read_reset_flagsDaisuke Nojiri2020-05-061-2/+7
| | | | | | | | | | | | | | | | | | | | Battery backed up RAM is used to store the reset flags. This patch wraps the code reading the reset flags with an API for the consistency and make it available to external callers. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=chromium:1078470 BRANCH=none TEST=buildall Change-Id: I11dd5a75eb51fa02664e0c30fa7e23a9ea2dc3bc Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2182562 Reviewed-by: Craig Hesling <hesling@chromium.org> Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Auto-Submit: Daisuke Nojiri <dnojiri@chromium.org>
* common/system: Unify ec_current_image and system_image_copy_tTom Hughes2020-02-282-12/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | "enum ec_current_image" is exposed in ec_commands.h (and used by non-EC code, such as biod). We also have an "enum system_image_copy_t" that is the exact same thing (though has a few more definitions). A followup CL (I714b6bd8c0d7192386404c25a831e38438fa5238) adds the "sysinfo" host command, so we want to be able to expose all the potential image variants. Rather than maintain two enums that can potentially get out of sync, unify the code to use a single enum. We choose to keep the "enum ec_current_image", since external code depends on it. To verify that this change results in no changes to the generated binaries: ./util/compare_build.sh --board all BRANCH=none BUG=b:146447208 TEST=./util/compare_build.sh --board=all Change-Id: I13776bc3fd6e6ad635980476a35571c52b1767ac Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2036599 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Namyoon Woo <namyoon@chromium.org>
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