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* keyscan: decouple keyboard_raw functionality from the presence of TASK_KEYSCANAlexandru M Stan2019-11-191-0/+2
| | | | | | | | | | | | | | | | | | | | | | With the addition of external i2c keyboard controllers, chips that don't necessarly have gpios going to a keyboard can now still have a TASK_KEYSCAN. Therefore it's wrong to assume we want the chip/*/keyboard_raw code included. There was no easy way to make an ways on option (eg: CONFIG_KEYBOARD_RAW) that could get #undefd in strategic places. The place that would always define it would be in include/config.h but I don't believe that executes before the build.mk rules. BUG=b:135895590 TEST=Other boards with keyboards still happy. TEST=No compile errors (regarding missing keyboard GPIOS) when declaring TASK_KEYSCAN on a fresh stm32 board. BRANCH=master Change-Id: I061812a6941a11784950280648912edd5844bd79 Signed-off-by: Alexandru M Stan <amstan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1693862 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* LICENSE: remove unnecessary (c) after CopyrightTom Hughes2019-06-191-1/+1
| | | | | | | | | | | | | | | | Ran the following command: git grep -l 'Copyright (c)' | \ xargs sed -i 's/Copyright (c)/Copyright/g' BRANCH=none BUG=none TEST=make buildall -j Change-Id: I6cc4a0f7e8b30d5b5f97d53c031c299f3e164ca7 Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1663262 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* Makefile: Replace flag -DX with -DX= to be supported by IS_ENABLED().Yilun Lin2019-06-031-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | IS_ENABLED works for an empty-string-defined macro. However, -D options default to define the macro to 1. This CL forces those macros, such as BOARD_* CHIP_*, CORE_*, CHIP_VARIANT_* and CHIP_FAMILIY_*, to be defined as an empty string, so that it can be supported by IS_ENABLED macro. TEST=use if(IS_ENABLED(BOARD_KRANE)) and see compilation success. TEST=compares build directory w/ and w/o this CL, and see the .smap are the same: ls build/*/*/ec.*.smap | sed -e 's|build/||' | \ xargs -I{} diff -u -a build/{} build.new/{} BUG=none BRANCH=None Change-Id: I96e2aa1cb5f3369e5e445a674595a9234f26707a Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/1627840 Commit-Ready: Yilun Lin <yllin@chromium.org> Tested-by: Yilun Lin <yllin@chromium.org> Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* lpc/espi: convert ec chip code to use granular optionJett Rink2018-05-221-1/+1
| | | | | | | | | | | | | | Break the ec chip code up with the more granular CONFIG_HOSTCMD_(X86|LPC|ESPI) options. BRANCH=none BUG=chromium:818804 TEST=Full stack builds and works on yorp (espi) and grunt (lpc) Change-Id: Ie272787b2425175fe36b06fcdeeee90ec5ccbe95 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1067502 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cleanup: Remove jtag_pre_init()Shawn Nematbakhsh2017-09-071-1/+1
| | | | | | | | | | | | | | | Use our newly-created chip_pre_init() for doing JTAG initialization. BUG=chromium:747629 BRANCH=None TEST=`make buildall -j` Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Ic5771895a214a9f1aa9bd289eef576f52adf973f Reviewed-on: https://chromium-review.googlesource.com/629676 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* g: CONFIG_FLASH should be optionalBill Richardson2016-10-021-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The application may need to read/write/erase the flash memory, but we not want console users to do so. This CL adds CONFIG_FLASH_PHYSICAL, which allows the higher-level CONFIG_FLASH to be undefined while still providing the chip-specific flash_physical_* accessor functions. There aren't many board.h files that needed changes, since CONFIG_FLASH_PHYSICAL is enabled by default, just like CONFIG_FLASH. BUG=chrome-os-partner:57408 BRANCH=none TEST=make buildall; try on Gru with and without CR50_DEV=1 See that it still boots, updates, wipes, restores, etc. without linking common/flash.o in the production image; and that the flash commands are still there in the dev build. Signed-off-by: Bill Richardson <wfrichar@chromium.org> Change-Id: I7eb1bbcb414b1c70ee427c4fcb5cea899dbb9e93 Reviewed-on: https://chromium-review.googlesource.com/391188 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* GLaDOS: Kunimitsu: Enable link-time optimization.Aseda Aboagye2015-11-091-0/+9
| | | | | | | | | | | | | | | | | | | | Turn on LTO for GLaDOS and Kunimitsu. This saves about 5k from the image on GLaDOS. Also, LTO is disabled for the loader since it actually causes it to bloat in size for some reason. BUG=chrome-os-partner:46063 BRANCH=None TEST=Build and flash on GLaDOS with charger inserted. Verify that EC boot is successful. sysjump to RW and verify that the jump is successful. TEST=make -j buildall tests Change-Id: I9892edfc724f290acaf6cceba181c177702d63bf Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/311208 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* mec1322: Change the Port 80 task to a timer IRQ.Aseda Aboagye2015-10-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | The port 80 task just polls every 1ms until disabled when the system goes into suspend. Therefore, this commit configures a 1ms timer interrupt that will be used for the port 80 writes instead of using an entire task. This saves task stack space as well as context switches. BUG=chrome-os-partner:46062 BUG=chrome-os-partner:46063 BRANCH=None TEST=Flash GLaDOS and verify using the `port80' console comamnd that there are bytes in the port80 history. TEST=make -j buildall tests Change-Id: I65b48217a638c1f6ae1ac86471f9a98e0ec4533a Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/305591 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* glados: kunimitsu: Change image size to 100K.stabilize-smaug-7547.BAseda Aboagye2015-10-131-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MEC1322 is optimized for 96k code RAM and 32k data RAM, therefore the default MEC1322 boards should follow this. On GLaDOS and Kunimitsu, we cannot fit all of the data in data RAM, therefore we adjust this boundary slightly. This should not be moved further as this represents when we are truly out of space. 128k image: -3k loader -1k for shmem/panic info -24k RAM for RO/RW -100k for RO/RW .text and .rodata BUG=chrome-os-partner:46058 BUG=chrome-os-partner:46063 BUG=chrome-os-partner:45690 BRANCH=None TEST=make -j buildall tests TEST=Flash GLaDOS, verify AP and EC boot. Change-Id: Ie53ef6dc607333968bee8f296e7c21ed629e357b Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/305362 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Allow for private board configurationsBill Richardson2015-08-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The public sources look for board configurations in directories named board/$BOARD/ Sometimes it's necessary to keep sensitive projects out of the public view for a bit. This CL allows board configurations to also appear in directories named private*/board/$BOARD/ BUG=none BRANCH=none TEST=manual First, ebuilds and "make buildall" seem to work just as before. Second, I copied 24 of the existing boards (those without board-specific #ifdefs in the code) into a private*/board/ directory, renamed them to something unique, and ran "make buildall" again. Both public and private boards compiled and passed their tests. Change-Id: I977c23cb8e73e40677c8f329abca8bbc51fd53df Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/292428 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* build-infr: Add support for shared RO library.Aseda Aboagye2015-07-171-7/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This commit introduces the build infrastructure changes needed for creating a shared RO library. (libsharedobjs). The end goal is for the library to contain various objects that can be shared with both the RO and RW EC images. Now, there are 3 make goals: ro, rw, and libsharedobjs. In order for changes that are only specific to a single image (ie: RW only) to be applied correctly, the object files are now built separately for the RO, RW, shared objects library targets. NOTE: Certain EC targets are incompatible with this model due to the fact that only one image is present within flash at a time. BRANCH=none BUG=None TEST=make -j buildall tests TEST=make -j BOARD=cr50 xrefs TEST=make BOARD=samus dis TEST=Built samus EC image and compared that the final EC image was identical to the upstream version (except for the git SHAs & version strings). CQ-DEPEND=CL:285934 Change-Id: I8e67f089710be9c6d7017718109262394bdad2f5 Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/274079 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* mec1322: protect spi_transcation() with mutexAndrey Petrov2015-07-011-1/+1
| | | | | | | | | | | | | | | | | | Concurrent SPI transactions are not possible, however in case of external SPI and flashrom update scenario both host command and vhash trigger transactions. This adds mutex for the SPI transcation BRANCH=None BUG=chrome-os-partner:38103 TEST=on Cyan, run hundreds of flashrom cycles to make sure there are no read, erase or write errors Change-Id: If346ebe635387d477dcea5f406a5c31579142e2d Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://chromium-review.googlesource.com/282113 Reviewed-by: Shawn N <shawnn@chromium.org> Commit-Queue: Bernie Thompson <bhthompson@chromium.org> Tested-by: Bernie Thompson <bhthompson@chromium.org>
* mec1322: lfw loader + RO/RW architectureDivya Jyothi2015-04-231-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mec1322 only has 96KB program memory, vs 256KB flash space on lm4.We no longer have enough program memory to load both RO and RW at boot. We'll want to implement a small loader program that will load either RO or RW from flash, and then jump to the loaded image. CONFIG_FW_INCLUDE_RO is enabled to include RO image into the build. pack.py script is altered to load the (lfw + R)O on boot. Software sync is not added.Distinguish between RO/RW is yet to be added. flash_ec is altered to support padding 0xFFs to 256k ec.bin to match the size of the SPI flash of the board. BUG=chromium:37510 BRANCH=None TEST=Make -j buildall,Verified ec.bin to be 256k. Verified RW image at offset 0h and (lfw + RO) at offset 2000h. On boot sysjump to lfw. lfw checks in shared SRAM (currently RO) and jumps to RO image. Change-Id: Ib9b114e2f24a615d5e5bd8b3803be621d1e5bd17 Signed-off-by: Divya Jyothi <divya.jyothi@intel.com> Reviewed-on: https://chromium-review.googlesource.com/265807 Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-by: Icarus W Sparry <icarus.w.sparry@intel.com>
* mec1322: initial version of lfw loaderAndrey Petrov2015-04-231-1/+28
| | | | | | | | | | | | | | | | | | | | | lfw is a customized boot loader with max targeted code size of 4k and data size of 2k.It supports minimal functionalities required to support chromebooks RO/RW architecture.It is placed in the write porected section with RO image . Capabilities include SPI,DMA,UART with minimal debugging support. Currently sysjump support is missing and exception handling is very basic. BUG=chromium:37510 TEST=make buildall -j, flashing and booting on strago BRANCH=None Change-Id: I803998d489297dfe0745dcccbb54412035d73f78 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Signed-off-by: Divya Jyothi <divya.jyothi@intel.com> Reviewed-on: https://chromium-review.googlesource.com/265904 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* mec1322: Changed to generate ec.bin for the firmware binary.Icarus Sparry2015-04-151-5/+9
| | | | | | | | | | | | | | | | | | | | | Previously for the mec1322 chip an ec.bin file was created in the normal way and then it was "packed" in a post-processing stage to produce ec.spi.bin. This change allows a chip or board build.mk file to specify the rules used to produce ec.bin, and uses this for the mec1322 to do the packing. This means that we can use the standard "ec.bin" name, and do not need to alter other scripts, such as the script which creates chromeos-firmwareupdate. BUG=None TEST=buildall -j, flash on strago and see it still works. BRANCH=NONE Change-Id: I3f880d64e60d14f82cb1d21c8b3f2d4ae5e0dfef Signed-off-by: Icarus Sparry <icarus.w.sparry@intel.com> Reviewed-on: https://chromium-review.googlesource.com/265544 Tested-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Kevin K Wong <kevin.k.wong@intel.com>
* mec1322: Add flash physical interface functionsShawn Nematbakhsh2015-03-121-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Add physical flash interface for read / write / protection of external SPI on mec1322. BUG=chrome-os-partner:36167 TEST=Manual on glower: flashread 0xf000 0x200 --> dumps 0xff flashwrite 0xf000 0x200 flashread 0xf000 0x200 --> dumps write pattern flasherase 0xf000 0x1000 flashread 0xf000 0x200 --> dumps 0xff spi_flash_prot 0 0x10000 flashinfo --> shows first 64KB protected spi_flashwrite 0xf000 0x200 --> access denied spi_flashwrite 0x1f000 0x200 --> OK flashread 0x1f000 0x200 --> dumps write pattern BRANCH=None Change-Id: I2cb20a49934999fc0dd9b3425eb99708711637c5 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/257132 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* mec1322: Specify SPI flash size in KBVic Yang2015-01-161-1/+1
| | | | | | | | | | | | | | | | For boards without a shared SPI, it's reasonable to use a SPI flash smaller than 1MB. Change the script to allow this. BRANCH=None BUG=chrome-os-partner:35308 TEST=Build strago and check the size of ec.spi.bin. Change-Id: Iabf7065d158be5f82c55e182e430858a12b18b6e Signed-off-by: Vic Yang <victoryang@google.com> Reviewed-on: https://chromium-review.googlesource.com/241111 Tested-by: Vic Yang <victoryang@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Vic Yang <victoryang@chromium.org>
* Strago: Automated build to generate ec.spi.bin.icarus sparry2014-11-121-0/+9
| | | | | | | | | | | | | | | | | | | | | | | Add another variable PROJECT_EXTRA which chips and boards can use to add additional prerequisites to the default all target Add rules for creating ec.spi.bin to package the ec firmware for strago BUG=None BRANCH=None TEST=Tested on Braswell Ref Design Board Signed-off-by: Divya Jyothi <divya.jyothi@intel.com> Signed-off-by: icarus sparry <icarus.w.sparry@intel.com> Change-Id: I4fb9f1275dc5bc2987b6abf5d45b0baf363c0d7a Reviewed-on: https://chromium-review.googlesource.com/226305 Reviewed-by: Vic Yang <victoryang@chromium.org> Reviewed-by: Icarus W Sparry <icarus.w.sparry@intel.com> Commit-Queue: Icarus W Sparry <icarus.w.sparry@intel.com> Tested-by: Icarus W Sparry <icarus.w.sparry@intel.com> Reviewed-by: Sheng-liang Song <ssl@chromium.org>
* mec1322: Add SPI master driverVic Yang2014-06-261-0/+1
| | | | | | | | | | | | | | This allows us to use the two SPI ports as SPI master. Also, to save CPU time on reading large amount of data, let's add an async interface for SPI transaction. BUG=chrome-os-partner:29805 TEST=Read manufacturer ID from SPI flash with sync/async interface BRANCH=None Change-Id: I427f4215602cccc55c4151f4116226b1e0ccc15e Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/204719
* mec1322: DMA driverVic Yang2014-06-261-0/+1
| | | | | | | | | | | | | | | This implements the DMA driver using the same DMA interface we are using now. BUG=chrome-os-partner:29805 TEST=Along with the following SPI driver, read manufacturer ID from SPI flash. BRANCH=None Change-Id: Ife3c0c8b414568ff1cab7d072901ba2d11142a17 Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/205067 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* mec1322: ADC driverVic (Chun-Ju) Yang2013-12-201-0/+1
| | | | | | | | | | | | | ADC driver for MEC1322 with ADC interrupt support. BUG=chrome-os-partner:24107 TEST=Read single channel TEST=Read all channels BRANCH=None Change-Id: I89d196c7fd78e736575e2c368b65cfb1ec651004 Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/180832
* mec1322: keyboard scan supportVic (Chun-Ju) Yang2013-12-131-0/+1
| | | | | | | | | | | | | | | | | | | | | This adds keyboard scan module driver. Keyboard scan task is not enabled yet as the LPC layer is not finished and thus i8042 protocol cannot be enabled. Since KSO00-KSO03 are used as JTAG, we use KSO04-KSO16 so as to preserve JTAG functionality. Unfortunately we don't have enough KSO pins, so trace debug port must be disabled, as done in this CL. BUG=chrome-os-partner:24107 TEST=Set 'ksstate on'. Short KSI pins and KSO pins, and see corresponding key shown as pressed. TEST=Check keypress is detected when console shows 'KB wait'. BRANCH=None Change-Id: I366a27453ef95030d251e525313eb4627eb4340f Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179319 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* mec1322: I2C driverVic (Chun-Ju) Yang2013-12-061-0/+1
| | | | | | | | | | | | | | | | | | This adds the driver for MEC1322 I2C controller. BUG=chrome-os-partner:24107 TEST=Hook up TSU6721 to eval board. Do the following tests: - 'i2cscan' and see TSU6721. - Read device ID register and get correct value. - Add 3 tasks randomly doing I2C read and writes. Check there is no error. BRANCH=None Change-Id: I465f73fe8177a8df6b56c57e594cd733caea37d4 Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/178591 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* mec1322: Fan control driverVic (Chun-Ju) Yang2013-12-041-0/+1
| | | | | | | | | | | | | | | | | | | | This adds the driver for PWM duty cycle based and RPM based fan control. BUG=chrome-os-partner:24107 TEST='fanset 5000' and fan spins up. 'fanset 8000' and fan spins faster. 'fanset 0' and fan stops. 'fanduty 30' and fan spins up. 'fanduty 50' and fan spins faster. 'fanduty 30' and fan slows down. 'fanset 6000' and fan goes to ~6000 RPM. Unplug fan power and see 'fan 0 stalled'. Plug power back and doesn't see stall warning anymore. BRANCH=None Change-Id: Ice3e5c03686cde57894e888e34ae2070c33b4e4d Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/178402
* mec1322: LPC host command supportVic (Chun-Ju) Yang2013-12-041-0/+1
| | | | | | | | | | | | | | | | | | | With this, basic host command functionality is working. We don't have the correct description of LPC memory BAR register yet, so we have to use EMI (embedded memory interface) module for 0x800-0x9ff region. This requires a slightly different protocol, which is in the next CL. BUG=chrome-os-partner:24107 TEST=Wire EVB to Stumpy. 'ectool hello' and 'ectool version' working. BRANCH=None Change-Id: I873b4a455cf692e479321a5c6e18c8f33df60e66 Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/178250 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* mec1322: Add PWM driverVic (Chun-Ju) Yang2013-12-021-0/+1
| | | | | | | | | | | | | | | | This adds a PWM driver, which now generates 30KHz PWM output. Note that this is different from fan control module driver. BUG=chrome-os-partner:24107 TEST=Set GPIO136 to PWM1. Attach logic analyzer to monitor its output. - Set to active high and 30%, see 30% duty PWM at ~29.1KHz. - Set to active low and 20%, see 80% duty PWM at ~29.1KHz. BRANCH=None Change-Id: I5f1001d5a4701e19fa87c4cabfd4ae5ae7ccb30c Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/178391 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* mec1322: Add watchdog supportVic (Chun-Ju) Yang2013-11-261-0/+1
| | | | | | | | | | | | | | | This implements the basic watchdog support. For now, the watchdog doesn't warn us before it expires. This functionality will be added later using a basic timer. BUG=chrome-os-partner:24107 TEST='waitms 700' and the EC stays alive. TEST='waitms 1200' and the EC reboots. BRANCH=None Change-Id: I1cc48978ed09577ae88cc2f7a6087867e5854973 Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/177736
* mec1322: initial commitVic (Chun-Ju) Yang2013-11-211-0/+15
This is the initial commit of mec1322 support. This includes: - Basic GPIO driver. Interrupt not supported yet. - Microsecond timer - UART driver The script to pack the firmware binary will be checked in in following-up CL. BUG=chrome-os-partner:24107 TEST=Build and boot on eval board BRANCH=None Change-Id: I9013c908049d1f740f84bb56abca51b779f39eef Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175716 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
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