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* LICENSE: remove unnecessary (c) after CopyrightTom Hughes2019-06-191-1/+1
| | | | | | | | | | | | | | | | Ran the following command: git grep -l 'Copyright (c)' | \ xargs sed -i 's/Copyright (c)/Copyright/g' BRANCH=none BUG=none TEST=make buildall -j Change-Id: I6cc4a0f7e8b30d5b5f97d53c031c299f3e164ca7 Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1663262 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* gpio: extend flags size to accommodate GPIO_ flagsJett Rink2018-06-111-1/+1
| | | | | | | | | | | | | | | | | | | Widen the flags field from 16-bit to 32-bit to fit all of the current GPIO_flags. Also reorder fields within struct to allow arm compiler to use 16-bit instructions instead of 32-bit instructions when accessing fields (which is important for kevin board, otherwise it runs out of space) Lastly, re-tool macros to all reordering of gpio_alt_func struct fields. BRANCH=none BUG=b:109884927 TEST=builds on all boards Change-Id: I20b136c94a607c19031a88bddd255cc34cc57bbd Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1096018 Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* lpc/espi: convert ec chip code to use granular optionJett Rink2018-05-221-1/+1
| | | | | | | | | | | | | | Break the ec chip code up with the more granular CONFIG_HOSTCMD_(X86|LPC|ESPI) options. BRANCH=none BUG=chromium:818804 TEST=Full stack builds and works on yorp (espi) and grunt (lpc) Change-Id: Ie272787b2425175fe36b06fcdeeee90ec5ccbe95 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1067502 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Deferred: Remove hard coded number of deferredsAnton Staaf2016-04-191-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | Previously the maximum number of deferred routines was specified by the the default maximum number of deferred routines you had to override this, and if you wanted fewer, you still payed the price of having the defer_until array statically allocated to be the maximum size. This change removes that define and instead creates the RAM state of the deferred routine (the time to wait until to call the deferred) when the deferred is declared. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j manually test on discovery-stm32f072 Change-Id: Id3db84ee1795226b7818c57f68c1f637567831dc Reviewed-on: https://chromium-review.googlesource.com/335597 Commit-Ready: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* kunimitsu: increase stack size for PD_C0, PD_C1, and PD_CMDKevin K Wong2016-01-111-0/+6
| | | | | | | | | | | | | | | If I2C unwedge is called, an additioanl 220+ bytes of stack space will be needed. BUG=none BRANCH=none TEST=make buildall Change-Id: Ib0e6716e400e5993df2cdb48186ffc7776d523f0 Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-on: https://chromium-review.googlesource.com/320840 Reviewed-by: Icarus W Sparry <icarus.w.sparry@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* mec1322: reduce system stack sizeli feng2015-11-041-9/+8
| | | | | | | | | | | | | | | | | | | | | | | Reduce system stack size from 4096 to 1024. Increase code RAM size to 104K and reduce data RAM size to 20K. BUG=chrome-os-partner:45690 BRANCH=None TEST=Tested on Kunimitsu 1. Flash EC, boot up, force to S5/G3, back to S0; and powerd_dbus_suspend to S3, all work fine. 2. Use console command to dump system stack memory values, the size used is around 350, >600 still available. Change-Id: Ib004678cc16f10c94c333063b728a2816ed5b3c5 Signed-off-by: li feng <li1.feng@intel.com> Reviewed-on: https://chromium-review.googlesource.com/310581 Commit-Ready: Li1 Feng <li1.feng@intel.com> Tested-by: Li1 Feng <li1.feng@intel.com> Tested-by: Kyoung Il Kim <kyoung.il.kim@intel.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
* cleanup: Standardize use of CONFIG_I2C and add MASTER/SLAVE CONFIGsShawn Nematbakhsh2015-11-031-1/+0
| | | | | | | | | | | | | | | | | | | Some chips previously defined CONFIG_I2C and others didn't. Standardize the usage by removing CONFIG_I2C from all config_chip files and force it to be defined at the board level. Also, make boards define CONFIG_I2C_MASTER and/or CONFIG_I2C_SLAVE based on the I2C interfaces they will use - this will assist with some later cleanup. BUG=chromium:550206 TEST=`make buildall -j` BRANCH=None Change-Id: I2f0970e494ea49611abc315587c7c9aa0bc2d14a Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/310070 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org>
* cleanup: Remove redundant CONFIG_RAM_* configsShawn Nematbakhsh2015-09-291-11/+4
| | | | | | | | | | | | | | | | | RAM need not be preserved between jumps from the loader to RO/RW images, so there is no need for a separate region of loader RAM. Remove redundant CONFIGs which define this unneeded region. BUG=None TEST=Verify glados boots and sysjumps successfully. BRANCH=None Change-Id: I2567f17a973c6f9f00bcfd97a4581d6c4b6fd6f0 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/302586 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* mec1322: More code space in RAMKyoung Kim2015-09-251-2/+2
| | | | | | | | | | | | | | | | | | | | | | 1. No need for loader data ram 2. 97K code size 3. shifting down RO/RW image location in RAM by 1Kbyte. (loader code space: 4k to 3k) BUG=none TEST=1. build image with big code additions.(like low power idle patch) and check if there is flash size related error message. 2. check if EC's RO image can boot from loader. 3. use EC console command, "sysjump RO/RW" and check if it works. 4. Verified in Cyan and Kunimitsu. BRANCH=none Change-Id: Ie4daf44cdba944e3e58894ca80183fcdb0fdbc7c Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com> Reviewed-on: https://chromium-review.googlesource.com/302149 Commit-Ready: Kyoung Il Kim <kyoung.il.kim@intel.com> Tested-by: Kyoung Il Kim <kyoung.il.kim@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* cleanup: Change meaning of storage offset CONFIGsShawn Nematbakhsh2015-09-161-4/+0
| | | | | | | | | | | | | | | | | | | | | | | In order to support architectures with non-contiguous writable and protected regions, change storage offsets to be relative to writable and protected regions, rather than relative to "the start of the region of storage belonging to the EC". Spec doc available at https://goo.gl/fnzTvr. BRANCH=None BUG=chrome-os-partner:23796 TEST=With entire patch series, on both Samus and Glados: - Verify 'version' EC console command is correct - Verify 'flashrom -p ec -r read.bin' reads back EC image - Verify software sync correctly flashes both EC and PD RW images Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I796f8e7305a6336495bd256a78774595cb16a2e4 Reviewed-on: https://chromium-review.googlesource.com/297823 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cleanup: Remove CDRAM / CODERAM CONFIGsShawn Nematbakhsh2015-09-161-1/+0
| | | | | | | | | | | | | | | | | | | | | | | CDRAM / CODERAM configs were previously used for chips which copied code from external SPI to program memory prior to execution, and were used inconsistently between npcx and mec1322. These CONFIGs are now completely redundant given new configs like CONFIG_MAPPED_STORAGE_BASE and CONFIG_EXTERNAL_STORAGE. BRANCH=None BUG=chrome-os-partner:23796 TEST=With entire patch series, on both Samus and Glados: - Verify 'version' EC console command is correct - Verify 'flashrom -p ec -r read.bin' reads back EC image - Verify software sync correctly flashes both EC and PD RW images Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I0e054ab4c939f9dcf54abee8e5ebd9b2e42fe9c4 Reviewed-on: https://chromium-review.googlesource.com/297804 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cleanup: Rename geometry constantsShawn Nematbakhsh2015-09-161-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Rename and add geometry constants to match spec doc - https://goo.gl/fnzTvr. CONFIG_FLASH_BASE becomes CONFIG_PROGRAM_MEMORY_BASE CONFIG_FLASH_MAPPED becomes CONFIG_MAPPED_STORAGE Add CONFIG_INTERNAL_STORAGE, CONFIG_EXTERNAL_STORAGE and CONFIG_MAPPED_STORAGE_BASE where appropriate. This CL leaves chip/npcx in a broken state -- it's fixed in a follow-up CL. BRANCH=None BUG=chrome-os-partner:23796 TEST=With entire patch series, on both Samus and Glados: - Verify 'version' EC console command is correct - Verify 'flashrom -p ec -r read.bin' reads back EC image - Verify software sync correctly flashes both EC and PD RW images Change-Id: Idb3c4ed9f7f6edd0a6d49ad11753eba713e67a80 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/297484 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* mec1322: Remove FPU support by defaultShawn Nematbakhsh2015-09-021-1/+0
| | | | | | | | | | | | | | | | | | Floating point is used in very few places in the code, none of which are needed by mec1322 boards (yet). If needed, individual boards can define CONFIG_FPU. BUG=None TEST=Verify glados continues to boot AP successfully and image is shrunk by 64 bytes. BRANCH=Strago Change-Id: I6ea46c15bedbc498e7baa96098b002d711ac20fb Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/297029 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org>
* cleanup: Clarify use of flash layout CONFIGsShawn Nematbakhsh2015-09-021-58/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Based on feedback from programmers, it's not clear when config_std_internal_flash should be used, and when non-standard chip-specific layouts need to be defined. Add clarity here with the following changes: - Explain in-depth the one config that config_std_internal_flash should be used for. - Move non-standard chip-level flash layout CONFIGs to their own new chip-level file, config_flash_layout. All chips should either include config_std_internal_flash.h OR define their own layout in their own config_flash_layout. Functionally, this change is a NOP. BUG=chrome-os-partner:23796 TEST=`make buildall -j` BRANCH=None Change-Id: I6037b68db9048d90fa2a2da4c9c9e09d1143fa68 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/296527 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* Fix stack overflow exception in host-command task.Chiranjeevi Rapolu2015-07-081-0/+1
| | | | | | | | | | | | | | | | Increase host-command task stack size by 128 to avoid stack overflow exception. BRANCH=None BUG=chrome-os-partner:42071 TEST=Test for general functionality and confirm that no stack overflow happens. Change-Id: I5513dbca84cf556357c25cddbcde00e0db6d271b Signed-off-by: Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.com> Reviewed-on: https://chromium-review.googlesource.com/282810 Reviewed-by: Shawn N <shawnn@chromium.org> Commit-Queue: Divya Jyothi <divya.jyothi@intel.com>
* mec1322: Added support for sysjump.stabilize-7173.BDivya Jyothi2015-06-141-5/+1
| | | | | | | | | | | | | | | | | | | | | | | | changes added to support flashrom are: sysjump support to be able to copy the RO/RW image and jump to it without causing AP to reboot while its alreday ON. LPC init should be reinitialized on sysjump corrected gpio_set_flags_by_mask to make sure we update the register only for GPIO_LOW condition and not all else conditions. BUG=chrome-os-partner:38103 TEST=commands : flashrom -p ec -w ec.bin flashrom -p ec -r ec.bin BRANCH=none Change-Id: I23892f0378d756052030e73034c3acdd41477e34 Signed-off-by: Divya Jyothi <divya.jyothi@intel.com> Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/272000 Reviewed-by: Shawn N <shawnn@chromium.org>
* Increase charger/console/hook stack sizes.Chiranjeevi Rapolu2015-06-041-0/+4
| | | | | | | | | | | | | | | | | | | | Charger task is overflowing and causing crash. Increased charger task stack size by 128 bytes. Also increased console/hook by 128 bytes as these are also close to its limit. BRANCH=None BUG=chrome-os-partner:40766 TEST=1.Program EC image. 2. Run various tests to verify charger stack doesn't overflow. Change-Id: I6e350584508fa3a47769982b1e0cf3e3aea9ded6 Signed-off-by: Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.com> Reviewed-on: https://chromium-review.googlesource.com/274204 Reviewed-by: Sheng-liang Song <ssl@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org> Commit-Queue: Divya Jyothi <divya.jyothi@intel.com>
* mec1322: Simplify GPIO listsSteven Jian2015-05-271-0/+3
| | | | | | | | | | | | | | | Our existing GPIO macros use port# / gpio#, but the concept of different GPIO ports does not exist on the mec1322. Therefore, add new GPIO macros for chips which do not have distinct GPIO ports. BUG=None BRANCH=None TEST=make buildall -j Change-Id: Ibda97c6563ad447d16dab39ecadab43ccb25174b Signed-off-by: Steven Jian <steven.jian@intel.com> Reviewed-on: https://chromium-review.googlesource.com/262841 Reviewed-by: Anton Staaf <robotboy@chromium.org>
* mec1322: Correct SPI image offsetsShawn Nematbakhsh2015-05-161-55/+68
| | | | | | | | | | | | | | Correct image offsets to reflect our actual layout. BUG=chrome-os-partner:39741 TEST=Manual on Cyan. Verify EC image boots and FMAP RO_FRID and RW_FWID point to our actual IDs. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: If0c4e44f45cac1cdc0a99cf0ae4c17e0ead95486 Reviewed-on: https://chromium-review.googlesource.com/270353 Reviewed-by: Bernie Thompson <bhthompson@chromium.org>
* cleanup: Use appropriate image geometry CONFIGsShawn Nematbakhsh2015-05-151-1/+0
| | | | | | | | | | | | | | | | - Use CONFIG_*_MEM when dealing with images in program memory. - Use CONFIG_*_STORAGE when dealing with images on storage. - Use CONFIG_WP when dealing with the entire WP RO region. BUG=chrome-os-partner:39741,chrome-os-partner:23796 TEST=Manual on Cyan with subsequent commit. Verify that FMAP matches actual layout of image. Verify flashrom succeeds flashing + verifying EC image using host command interface. BRANCH=None Change-Id: Iadc02daa89fe3bf07b083ed0f7be2e60702a1867 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/270269
* cleanup: Rename image geometry CONFIGsShawn Nematbakhsh2015-05-121-10/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | Rename image geometry configs with a uniform naming scheme to make their purposes more clear. CONFIG_RO_MEM_OFF (was CONFIG_FW_RO_OFF) - RO image offset in program memory CONFIG_RO_STORAGE_OFF (was CONFIG_RO_SPI_OFF) - RO image offset on storage CONFIG_RO_SIZE (was CONFIG_FW_RO_SIZE) - Size of RO image CONFIG_RW_MEM_OFF (was CONFIG_FW_RW_OFF) - RW image offset in program memory CONFIG_RW_STORAGE_OFF (was CONFIG_RW_SPI_OFF) - RW image offset on storage CONFIG_RW_SIZE (was CONFIG_FW_RW_SIZE) - Size of RW image CONFIG_WP_OFF (was CONFIG_FW_WP_RO_OFF) - Offset of WP region on storage CONFIG_WP_SIZE (was CONFIG_FW_WP_RO_SIZE) - Size of WP region on storage BUG=chrome-os-partner:39741,chrome-os-partner:23796 TEST=Set date / version strings to constants then `make buildall -j`. Verify that each ec.bin image is identical pre- and post-change. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I6ea0a4e456dae71c266fa917a309b9f6fa4b50cd Reviewed-on: https://chromium-review.googlesource.com/270189 Reviewed-by: Anton Staaf <robotboy@chromium.org>
* mec1322:Flasherase, flashread, flashwrite offsets adjusted.Divya Jyothi2015-05-051-2/+2
| | | | | | | | | | | | | | | | | | | | | Flash read,erase and write should access SPI flash and not read SRAM MAPPED location. flashrom -p and Software sync use the same flash functions to perform flashread,flashearse and flashwrite.So these functions should be reading RW image starting address offset.Address offset sent by host should not depend on the actual SPI flash as the EC code handles the right offset to program the ec.bin(via flashrom -p) and RW image only via software sync. BUG=chrome-os-partner:38103 BRANCH=None TEST=flashrom -p options tested to read and update ec.bin Change-Id: I3fb16accf3e05eaa3469a8a589962164574d5fb2 Signed-off-by: Divya Jyothi <divya.jyothi@intel.com> Reviewed-on: https://chromium-review.googlesource.com/269231 Reviewed-by: Shawn N <shawnn@chromium.org>
* mec1322: lfw loader + RO/RW architectureDivya Jyothi2015-04-231-36/+60
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | mec1322 only has 96KB program memory, vs 256KB flash space on lm4.We no longer have enough program memory to load both RO and RW at boot. We'll want to implement a small loader program that will load either RO or RW from flash, and then jump to the loaded image. CONFIG_FW_INCLUDE_RO is enabled to include RO image into the build. pack.py script is altered to load the (lfw + R)O on boot. Software sync is not added.Distinguish between RO/RW is yet to be added. flash_ec is altered to support padding 0xFFs to 256k ec.bin to match the size of the SPI flash of the board. BUG=chromium:37510 BRANCH=None TEST=Make -j buildall,Verified ec.bin to be 256k. Verified RW image at offset 0h and (lfw + RO) at offset 2000h. On boot sysjump to lfw. lfw checks in shared SRAM (currently RO) and jumps to RO image. Change-Id: Ib9b114e2f24a615d5e5bd8b3803be621d1e5bd17 Signed-off-by: Divya Jyothi <divya.jyothi@intel.com> Reviewed-on: https://chromium-review.googlesource.com/265807 Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-by: Icarus W Sparry <icarus.w.sparry@intel.com>
* mec1322: Add SPI flash layout for lfw / ro / rw architectureDivya Jyothi2015-04-231-1/+24
| | | | | | | | | | | | | | | | | mec1322 bootloader looks for a CRC TAG at the xFF00 boundary of the flash before it loads the ec onto SRAM for execution. Code for EC will be packed to occupy the last 256k of Flash. That way the binay generation is independent of the flash size. The last 20000h is RO + lfw followed by 20000h space for RW. BUG=chromium:37510 TEST=make -j buildall BRANCH=None Change-Id: Ie75bd8a40826d630b3022b5b3ecb2d6ad3aa2471 Signed-off-by: Divya Jyothi <divya.jyothi@intel.com> Reviewed-on: https://chromium-review.googlesource.com/265885 Reviewed-by: Shawn N <shawnn@chromium.org>
* mec1322: i2c: Support multiple I2C ports on the same controllerShawn Nematbakhsh2015-04-221-2/+8
| | | | | | | | | | | | | | | mec1322 I2C controller 0 has two attached ports. Modify the I2C driver so that both ports are usable. BUG=chrome-os-partner:38335,chrome-os-partner:38945 TEST=Manual on strago. Verify that i2cscan is functional. BRANCH=None Change-Id: I18d9d516984d041a38c86fd4ec1b0bfa4e885c9f Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/265951 Reviewed-by: Divya Jyothi <divya.jyothi@intel.com> Reviewed-by: Alec Berg <alecaberg@chromium.org>
* mec1322: Added CONFIG_SWITCH support.Kevin K Wong2015-04-131-1/+1
| | | | | | | | | | | | | This allows switch status to be updated to EC MemMap. BUG=none TEST=Verified mmapinfo console command is reporting the correct info. BRANCH=none Change-Id: I3b6683be8b92b59dffb3227e0a72a122dcda56a2 Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-on: https://chromium-review.googlesource.com/265493 Reviewed-by: Shawn N <shawnn@chromium.org>
* mec1322: Add flash physical interface functionsShawn Nematbakhsh2015-03-121-18/+31
| | | | | | | | | | | | | | | | | | | | | | | | Add physical flash interface for read / write / protection of external SPI on mec1322. BUG=chrome-os-partner:36167 TEST=Manual on glower: flashread 0xf000 0x200 --> dumps 0xff flashwrite 0xf000 0x200 flashread 0xf000 0x200 --> dumps write pattern flasherase 0xf000 0x1000 flashread 0xf000 0x200 --> dumps 0xff spi_flash_prot 0 0x10000 flashinfo --> shows first 64KB protected spi_flashwrite 0xf000 0x200 --> access denied spi_flashwrite 0x1f000 0x200 --> OK flashread 0x1f000 0x200 --> dumps write pattern BRANCH=None Change-Id: I2cb20a49934999fc0dd9b3425eb99708711637c5 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/257132 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* mec1322: Remove RO image to save program memoryShawn Nematbakhsh2015-03-061-3/+8
| | | | | | | | | | | | | | | | mec1322 projects are running very low on flash space. We don't yet have a loader to load either RO or RW at runtime, so remove the RO image entirely. This is a temporary change and should be reverted once we have a working loader. BUG=chrome-os-partner:37510 TEST=make buildall -j BRANCH=None Change-Id: I8c502ec2bcabf246d5a3ea939f1a8d0c366acd9f Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/256381 Reviewed-by: Vic Yang <victoryang@chromium.org>
* mec1322: Add SPI master driverVic Yang2014-06-261-0/+1
| | | | | | | | | | | | | | This allows us to use the two SPI ports as SPI master. Also, to save CPU time on reading large amount of data, let's add an async interface for SPI transaction. BUG=chrome-os-partner:29805 TEST=Read manufacturer ID from SPI flash with sync/async interface BRANCH=None Change-Id: I427f4215602cccc55c4151f4116226b1e0ccc15e Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/204719
* mec1322: DMA driverVic Yang2014-06-261-0/+1
| | | | | | | | | | | | | | | This implements the DMA driver using the same DMA interface we are using now. BUG=chrome-os-partner:29805 TEST=Along with the following SPI driver, read manufacturer ID from SPI flash. BRANCH=None Change-Id: Ife3c0c8b414568ff1cab7d072901ba2d11142a17 Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/205067 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* watchdog: Give more leeway to the independent watchdogDoug Anderson2014-06-231-1/+2
| | | | | | | | | | | | | | | | | | | | | | It would be really nice to be guaranteed to see watchdog warnings before we actually hit a watchdog reset even if something strange is going on with the CPU. Let's increase the margin between the timer and the independent so that the hardware watchdog is really hit as a last resort. It seems like a 1.6 second hardware watchdog wouldn't be the end of the world so let's bump that way rather than increasing the number of warnings. BRANCH=ToT BUG=chrome-os-partner:29162 TEST="waitms 1000" on EC console no longer ever reboots and "waitms 2000" usually does. Change-Id: Ic5e5ddec22fb8484cc7c552b19d3f2043c105d0c Signed-off-by: Doug Anderson <dianders@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/204895 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* mec1322: I2C driverVic (Chun-Ju) Yang2013-12-061-1/+1
| | | | | | | | | | | | | | | | | | This adds the driver for MEC1322 I2C controller. BUG=chrome-os-partner:24107 TEST=Hook up TSU6721 to eval board. Do the following tests: - 'i2cscan' and see TSU6721. - Read device ID register and get correct value. - Add 3 tasks randomly doing I2C read and writes. Check there is no error. BRANCH=None Change-Id: I465f73fe8177a8df6b56c57e594cd733caea37d4 Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/178591 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* mec1322: LPC host command supportVic (Chun-Ju) Yang2013-12-041-1/+1
| | | | | | | | | | | | | | | | | | | With this, basic host command functionality is working. We don't have the correct description of LPC memory BAR register yet, so we have to use EMI (embedded memory interface) module for 0x800-0x9ff region. This requires a slightly different protocol, which is in the next CL. BUG=chrome-os-partner:24107 TEST=Wire EVB to Stumpy. 'ectool hello' and 'ectool version' working. BRANCH=None Change-Id: I873b4a455cf692e479321a5c6e18c8f33df60e66 Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/178250 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* mec1322: initial commitVic (Chun-Ju) Yang2013-11-211-0/+94
This is the initial commit of mec1322 support. This includes: - Basic GPIO driver. Interrupt not supported yet. - Microsecond timer - UART driver The script to pack the firmware binary will be checked in in following-up CL. BUG=chrome-os-partner:24107 TEST=Build and boot on eval board BRANCH=None Change-Id: I9013c908049d1f740f84bb56abca51b779f39eef Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175716 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
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