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* ec: change usage of dummySam Hurst2020-08-051-2/+2
| | | | | | | | | | | | | | | | | | Google is working to change its source code to use more inclusive language. To that end, replace the term "dummy" with inclusive alternatives. BUG=b:162781382 BRANCH=None TEST=make -j buildall `grep -ir dummy *` The only results are in "private/nordic_keyboard/sdk8.0.0" which is not our code. Signed-off-by: Sam Hurst <shurst@google.com> Change-Id: I6a42183d998e4db4bb61625f962867fda10722e2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2335737 Reviewed-by: Tom Hughes <tomhughes@chromium.org>
* host_command: Change host command return value to enum ec_statusTom Hughes2019-10-021-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the host command handler callback function returns an int, it's easy to accidentally mix up the enum ec_error_list and enum ec_status types. The host commands always expect an enum ec_status type, so we change the return value to be of that explicit type. Compilation will then fail if you accidentally try to return an enum ec_error_list value. Ran the following commands and then manually fixed up a few remaining instances that were not caught: git grep --name-only 'static int .*(struct host_cmd_handler_args \*args)' |\ xargs sed -i 's#static int \(.*\)(struct host_cmd_handler_args \*args)#\ static enum ec_status \1(struct host_cmd_handler_args \*args)##' git grep --name-only 'int .*(struct host_cmd_handler_args \*args)' |\ xargs sed -i 's#int \(.*\)(struct host_cmd_handler_args \*args)#\ enum ec_status \1(struct host_cmd_handler_args \*args)##' BRANCH=none BUG=chromium:1004831 TEST=make buildall -j Cq-Depend: chrome-internal:1872675 Change-Id: Id93df9387ac53d016a1594dba86c6642babbfd1e Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1816865 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* LICENSE: remove unnecessary (c) after CopyrightTom Hughes2019-06-191-1/+1
| | | | | | | | | | | | | | | | Ran the following command: git grep -l 'Copyright (c)' | \ xargs sed -i 's/Copyright (c)/Copyright/g' BRANCH=none BUG=none TEST=make buildall -j Change-Id: I6cc4a0f7e8b30d5b5f97d53c031c299f3e164ca7 Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1663262 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* common: replace 1 << digits, with BIT(digits)Gwendal Grignou2019-03-261-19/+19
| | | | | | | | | | | | | | | | Requested for linux integration, use BIT instead of 1 << First step replace bit operation with operand containing only digits. Fix an error in motion_lid try to set bit 31 of a signed integer. BUG=None BRANCH=None TEST=compile Change-Id: Ie843611f2f68e241f0f40d4067f7ade726951d29 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1518659 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* host_events: Bump up host events and masks to 64-bitFurquan Shaikh2017-11-211-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | With the upcoming change to add a new command to get/set/clear host events and masks, it seems to be the right time to bump up the host events and masks to 64-bit. We are already out of available host events. This change opens up at least 32 bits for new host events. Old EC commands to operate on host events/masks will still deal with lower 32-bits of the events/mask. On the other hand, the new command being added will take care of the entire 64-bit events/masks. This ensures that old BIOS and kernel versions can still work with the newer EC versions. BUG=b:69329196 BRANCH=None TEST=make -j buildall. Verified: 1. hostevent set 0x4000 ==> Sets correct bit in host events 2. hostevent clear 0x4000 ==> Clears correct bit in host events 3. Kernel is able to query and read correct host event bits from EC. Verified using evtest. 4. Coreboot is able to read correct wake reason from EC. Verified using mosys eventlog list. Change-Id: Idcb24ea364ac6c491efc2f8dd9e29a9df6149e07 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/770925 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* port80: Provide default routine for logging port80 resumeFurquan Shaikh2017-10-311-7/+0
| | | | | | | | | | | | | | Add a common hook handler on CHIPSET_RESUME to log port80 resume message instead of duplicating the same code in all chip lpc_resume. BUG=b:68669668 BRANCH=None TEST=Verified that port80 resume is logged on S0ix and S3 resume. Change-Id: I313692f5499717d0d8f62be2ba3b8566c46e4dde Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/745362 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* lpc: Add and use lpc_resume_clear_masksFurquan Shaikh2017-10-311-9/+0
| | | | | | | | | | | | | | | | | | | | | Add a new LPC helper routine lpc_resume_clear_masks that can be used to clear SCI, SMI and wake masks upon resume from S3. This is done to mask the events until host explicitly unmasks them. It also ensures that these masks do not get reset on resume from S0ix where the host does not re-configure these masks. BUG=b:68669668 BRANCH=None TEST=Verified following: 1. make -j buildall 2. On resume from S0ix, SCI mask is not reset. 3. On resume from S3, SCI mask is reset and then set again by host request. Change-Id: I17a86bd60ef066b3716fb79ecce62f311eb45509 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/745533 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* host_event: Move host events and mask handling into common codeFurquan Shaikh2017-10-171-91/+7
| | | | | | | | | | | | | | | | | | | | Instead of duplicating the handling of host events and host event masks in chip lpc drivers, add routines in common code to provide basic functions like setting/getting of masks, setting/getting of events and handling of masks transitions across sysjump. BUG=None BRANCH=None TEST=make -j buildall. Verified following: 1. Event masks are correctly retained across sysjumps. 2. Wake from S3 works fine. 3. Wake from S0ix works fine. 4. SCI generated correctly. Change-Id: Ie409f91b12788e4b902b2627e31ba5ce40ff1d27 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/707771 Reviewed-by: Shawn N <shawnn@chromium.org>
* intel_x86: Make common code for LPC S0 <-> S0ix transitionsVijay Hiremath2017-01-211-47/+0
| | | | | | | | | | | | | | BUG=chrome-os-partner:59141 BRANCH=none TEST=Manually tested on Reef. System can enter and exit from S0iX when LID is closed & opened respectively. Change-Id: I5892da327c2dcdd400d5a7ade867bec1b80cbaa4 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/407047 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* Fix various misspellings in commentsMartin Roth2016-11-151-2/+2
| | | | | | | | | | | | | No functional changes. BUG=none BRANCH=none TEST=make buildall passes Change-Id: Ie852feb8e3951975d99dce5a49c17f5f0e8bc791 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/403417 Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
* cleanup: DECLARE_CONSOLE_COMMAND only needs 4 argsBill Richardson2016-08-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Since pretty much always, we've declared console commands to take a "longhelp" argument with detailed explanations of what the command does. But since almost as long, we've never actually used that argument for anything - we just silently throw it away in the macro. There's only one command (usbchargemode) that even thinks it defines that argument. We're never going to use this, let's just get rid of it. BUG=none BRANCH=none CQ-DEPEND=CL:*279060 CQ-DEPEND=CL:*279158 CQ-DEPEND=CL:*279037 TEST=make buildall; tested on Cr50 hardware Everything builds. Since we never used this arg anyway, there had better not be any difference in the result. Change-Id: Id3f71a53d02e3dc625cfcc12aa71ecb50e35eb9f Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/374163 Reviewed-by: Myles Watson <mylesgw@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Deferred: Use deferred_data instead of function pointerAnton Staaf2016-04-181-1/+1
| | | | | | | | | | | | | | | | | | | | | Previously calls to hook_call_deferred were passed the function to call, which was then looked up in the .rodata.deferred section with a linear search. This linear search can be replaced with a subtract by passing the pointer to the deferred_data object created when DECLARE_DEFERRED was invoked. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None CQ-DEPEND=CL:*255812 TEST=make buildall -j Change-Id: I951dd1541302875b102dd086154cf05591694440 Reviewed-on: https://chromium-review.googlesource.com/334315 Commit-Ready: Bill Richardson <wfrichar@chromium.org> Tested-by: Bill Richardson <wfrichar@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* mec1322: Do not shutdown LPC in deepsleep.Divya Jyothi2016-03-171-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | During the resume sequence of S0ix EC can receive host commands early in the resume path when LPC is still disabled in EC. Host messages will be lost if the LPC interface with the kernel is down. Clock control was programed to 2 which means ring oscillator is shut down after completion of everty LPC transaction.To restart the oscillator EC should enable a wake interrupt on LPC LFRAME number and this mode can cause an increase in the time to respond to the LPC transactions. Keeping LPC always on shows minimal power impact as per datasheet Pg.390. The impact is < 0.45mW. BUG=chrome-os-partner:50627 TEST=Enter into S0ix and exit reliably. BRANCH=firmware-glados-7820.B Change-Id: I670b9b45c3a85c9bca249312a73a25dca52b313a Signed-off-by: Divya Jyothi <divya.jyothi@intel.com> Reviewed-on: https://chromium-review.googlesource.com/332333 Reviewed-by: Shobhit Srivastava <shobhit.srivastava@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org> (cherry picked from commit c03fd6e0eaa6ecd3205214f901facb9896a798b4) Reviewed-on: https://chromium-review.googlesource.com/332791
* skylake: do not clear masks in S0ix -> S0 transitionArchana Patni2016-02-221-5/+9
| | | | | | | | | | | | | | | | | | | | | | | | EC clears the SCI/SMI/Wake masks in the resume sequence for S3 and S0ix. This works in the S3 case because Coreboot reprograms the masks after EC. But in S0ix, these masks stay cleared forever. This means that no further events are sent to the host. This patch conditionally clears the masks only in the S3 transition. BRANCH=glados BUG=chrome-os-partner:48834 TEST=hostevent in EC console before and after S0ix to ensure SCI masks are preserved Change-Id: I23751680788ee7a239e321309a1334d37adc4f43 Signed-off-by: Archana Patni <archana.patni@intel.com> Signed-off-by: Subramony Sesha <subramony.sesha@intel.com> Signed-off-by: Jenny TC <jenny.tc@intel.com> Reviewed-on: https://chromium-review.googlesource.com/320191 Commit-Ready: Jenny Tc <jenny.tc@intel.com> Tested-by: Jenny Tc <jenny.tc@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* skylake: set and clear wake masks in S0 <-> S0ix transitionsArchana Patni2016-02-101-0/+48
| | | | | | | | | | | | | | | | | | | | | | In the S0 <-> S3 transition, Coreboot sends EC messages to set/clear the wake masks when the SMI is invoked. For S0ix, EC sets and clears the wake mask via this patch. These functions are directly invoked from the state machine transition states. During S0ix entry, the wake mask for lid open is enabled. During S0ix exit, the wake mask for lid open is cleared. All pending events are also cleared BRANCH=none BUG=chrome-os-partner:48834 TEST=test lidopen in S0ix Signed-off-by: Archana Patni <archana.patni@intel.com> Signed-off-by: Subramony Sesha <subramony.sesha@intel.com> Change-Id: I52a15f502ef637f7b7e4b559820deecb831d818f Reviewed-on: https://chromium-review.googlesource.com/320190 Commit-Ready: Divya Jyothi <divya.jyothi@intel.com> Tested-by: Divya Jyothi <divya.jyothi@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* ec: Add a chipset reset hookDuncan Laurie2016-01-251-0/+13
| | | | | | | | | | | | | | | | | | | | | | There are hooks for chipset power sequencing but not one to indicate that the system has reset at runtime. Add a hook for this and implement for lm4 and mec1322. The hook is notified on any platform reset, including those that happen on the way into S3/S5 state. There is a new config variable added because the hook is notified in the interrupt handler and needs a deferrable function that needs to be added to every board. BUG=chrome-os-partner:46049 BRANCH=none TEST=tested on glados and samus Change-Id: I3be639414e18586344e0ec84632a50dfc1df586b Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/315221 Commit-Ready: Aaron Durbin <adurbin@chromium.org> Tested-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* mec1322: lpc: Clear STATUS_PROCESSING LPC status bit on initShawn Nematbakhsh2016-01-191-0/+3
| | | | | | | | | | | | | | | | | | | | | | When a sysjump host command is received, there is a (usually) small period of time when the EC has sent a reply packet back to the host, but interrupts are still enabled. If the host sends a new host command, STATUS_PROCESSING will be set by the EC ISR, but the host command will never be handled due to pending sysjump. In this case, STATUS_PROCESSING will still be set, so we need to clear it on LPC post-sysjump re-init. BUG=chrome-os-partner:49318 TEST=Add 200ms msleep before call to interrupt_disable() in jump_to_image(), boot to software sync, and verify host commands are handled successfully post-sysjump and system continues to boot. BRANCH=glados, cyan Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Id0878df738541f7d5d158821a68988a8e6dc6759 Reviewed-on: https://chromium-review.googlesource.com/322431 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* mec1322: Change the Port 80 task to a timer IRQ.Aseda Aboagye2015-10-191-2/+0
| | | | | | | | | | | | | | | | | | | | | | The port 80 task just polls every 1ms until disabled when the system goes into suspend. Therefore, this commit configures a 1ms timer interrupt that will be used for the port 80 writes instead of using an entire task. This saves task stack space as well as context switches. BUG=chrome-os-partner:46062 BUG=chrome-os-partner:46063 BRANCH=None TEST=Flash GLaDOS and verify using the `port80' console comamnd that there are bytes in the port80 history. TEST=make -j buildall tests Change-Id: I65b48217a638c1f6ae1ac86471f9a98e0ec4533a Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/305591 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* Fix assertion crash in __wait_evt()Chiranjeevi Rapolu2015-06-251-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | mutex_lock() is called from MEC1322_IRQ_ACPIEC0_IBF interrupt context, causing deadlock and assertion in __wait_evt(). In the interrupt context it now checks for mutex lock first. If the mutex is already locked,, it will disable ACPI interrupts and defer the memmap mutex lock. Added LPC interrupt disable/enable functions as needed. Increased deferred function count where needed. BRANCH=None BUG=chrome-os-partner:40820 TEST=Test for suspend-resume, cold, warm reboots and other general stability. Change-Id: I3dda0d4635a6b6281faf200c8c7b6fcba8877254 Signed-off-by: Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.com> Reviewed-on: https://chromium-review.googlesource.com/280418 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org> Commit-Queue: Divya Jyothi <divya.jyothi@intel.com> Tested-by: Divya Jyothi <divya.jyothi@intel.com>
* mec1322: Added support for sysjump.stabilize-7173.BDivya Jyothi2015-06-141-1/+53
| | | | | | | | | | | | | | | | | | | | | | | | changes added to support flashrom are: sysjump support to be able to copy the RO/RW image and jump to it without causing AP to reboot while its alreday ON. LPC init should be reinitialized on sysjump corrected gpio_set_flags_by_mask to make sure we update the register only for GPIO_LOW condition and not all else conditions. BUG=chrome-os-partner:38103 TEST=commands : flashrom -p ec -w ec.bin flashrom -p ec -r ec.bin BRANCH=none Change-Id: I23892f0378d756052030e73034c3acdd41477e34 Signed-off-by: Divya Jyothi <divya.jyothi@intel.com> Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/272000 Reviewed-by: Shawn N <shawnn@chromium.org>
* mec1322: Added KBD SERIRQ supportKevin K Wong2015-05-281-7/+8
| | | | | | | | | | | | | | BUG=chrome-os-partner:24107 TEST=Keyboard keys are printed correctly on Kunimitsu. BRANCH=none Change-Id: Ia4ed6c1166fa20dc8623ea8d7147b6f587cbf993 Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-on: https://chromium-review.googlesource.com/272504 Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org> Commit-Queue: Vijay P Hiremath <vijay.p.hiremath@intel.com>
* mec1322: Added task-based Port80 POST code support.Kevin K Wong2015-04-271-0/+27
| | | | | | | | | | | | | | | | | | | | | | With mec1322's EMI set to decode IO 0x800, it does not have any other interfaces to support POST code via IO 0x80. This change is to enable Port80 POST code support via polling method. Limitation: - POST Code 0xFF will be ignored. - POST Code frequency is greater than 1 msec. BUG=chrome-os-partner:39386 TEST=Verified Port80 POST code is captured in EC console. Verified "port80 task" console command will disable/enable Port80 task. Verified "port80 poll" will get the last Port80 POST code. BRANCH=none Change-Id: I27e53e84b5be1fd98464a44407dd58b93d8c798d Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-on: https://chromium-review.googlesource.com/266783 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* mec1322: Updated code to only clear the interrupt status bit of LPC_RESET#.Kevin K Wong2015-04-141-2/+2
| | | | | | | | | | | | | Interrupt Source register is R/WC, so |= should not be used. BUG=none TEST=Verified LPC_RESET# is detected by interrupt handler via EC console. BRANCH=none Change-Id: Ib553c839e1311538b17a4d9fbc10c9df5b7e6b44 Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-on: https://chromium-review.googlesource.com/265502 Reviewed-by: Shawn N <shawnn@chromium.org>
* mec1322: Add EC_CMD_GET_PROTOCOL_INFO handlerShawn Nematbakhsh2015-04-101-0/+19
| | | | | | | | | | | | | | | Add EC_CMD_GET_PROTOCOL_INFO handler to return info about supported EC protocols. BUG=chrome-os-partner:38224 TEST=Manual on Glower. Verify EC driver successfully loads on 3.14 kernel. BRANCH=None Change-Id: Ib5195ed720875320e9bd07c1c92a198fd34b842e Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/264455 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* mec1322: Setup EMI unit at base address 0x800Shawn Nematbakhsh2015-04-101-3/+12
| | | | | | | | | | | | | Use EMI unit for access to host command / memmap data. BUG=chrome-os-partner:38224 TEST=Manual on glower. Verify system boots + ectool works. BRANCH=None Change-Id: I06768a68fdf43f09d5e7425c293efff6a69a8878 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/264454 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* mec1322: Enable HW control of KBC aux bufferShamile Khan2015-04-091-0/+4
| | | | | | | | | | | | | | | | This turns on hardware controlled update of bit 5 (AUXOBF) in Keyboard Status Read Register. Previously, this bit was in user-defined mode and not reliable. BUG=None TEST=Tested that keyboard becomes functional on Braswell Ref Design. BRANCH=None Change-Id: I192383ebebb25a027d58da9fc1ef7f3bb3e8da66 Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/263948 Reviewed-by: Shawn N <shawnn@chromium.org> Commit-Queue: Kevin K Wong <kevin.k.wong@intel.com>
* mec1322: Fix the ACPI EC0 BAR settingSteven Jian2015-03-261-1/+1
| | | | | | | | | | | | | Per datasheet, it should be 304. BUG=None BRANCH=None TEST=None Change-Id: I3f7b82bf2f63ed011183cd72f4e19daa7dd0dcf0 Signed-off-by: Steven Jian <steven.jian@intel.com> Reviewed-on: https://chromium-review.googlesource.com/262283 Reviewed-by: Shawn N <shawnn@chromium.org>
* ACPI: Support accessing memmap data over ACPI CMD / DATA portsstabilize-6915.BShawn Nematbakhsh2015-03-251-0/+10
| | | | | | | | | | | | | | | | | | | | | | | Some platforms are unable to access the 900h-9ffh region over LPC and must instead access memmap data through the ACPI CMD / DATA ports. To avoid racing with data updates, disallow changes to multi-byte memmap data while in burst mode. Linux currently enables burst mode when accessing multi-byte data and disables it immediately afterward, though the ACPI spec defines burst mode in a more general way. BUG=chrome-os-partner:38224 TEST=Manual on Samus. Undefine LPC_MEMMAP and modify asl to move memmap data to ERAM at offset 0x20. Verify system boots cleanly and battery status is updated immediately on plug / unplug. BRANCH=None Change-Id: Ib848bdb491fdfece96ad0cee7a44ba85b4a1a50b Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/262072 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* Revert "mec1322: Fix LPC interrupt bit mask"stabilize-6835.BVic Yang2015-02-281-4/+4
| | | | | | | | | | | | | | | | | | This reverts commit 9ed4434ad8770ca3edd6bccd456738019c9e08b0. According to MEC1322 errata, LRESET# interrupt is indeed GIRQ 19 bit 1. BRANCH=None BUG=chrome-os-partner:36326 TEST=None Change-Id: I9d0dc0ef3abac1ace59b46eafae04f6b9e5c0b9b Reviewed-on: https://chromium-review.googlesource.com/254771 Reviewed-by: Divya Jyothi <divya.jyothi@intel.com> Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org> Commit-Queue: Vic Yang <victoryang@chromium.org> Tested-by: Vic Yang <victoryang@chromium.org>
* mec1322: Fix LPC interrupt bit maskVic Yang2015-02-101-4/+4
| | | | | | | | | | | | | | | LRESET# interrupt should be GIRQ19 bit 0 instead of bit 1. BRANCH=None BUG=chrome-os-partner:36326 TEST=Run on Glower and doesn't see LRESET# interrupt storm. Change-Id: I1adedea63e9ec2851e1e09fc8c0eb8185070dad1 Signed-off-by: Vic Yang <victoryang@google.com> Reviewed-on: https://chromium-review.googlesource.com/247790 Tested-by: Vic Yang <victoryang@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org> Commit-Queue: Vic Yang <victoryang@chromium.org>
* Strago: Initial Version of Strago Board added.Divya Jyothi2014-11-061-16/+77
| | | | | | | | | | | | | | | | | | | Modules that are enabled are listed below: - Power Sequencing - Keyboard Scan and Protocol - LPC to support Keyboard - Power Button Task ec.spi.bin has to be generated manualy using pack_ec.py BUG=None BRANCH=None TEST=Tested on Stargo-Proto board Change-Id: Ic5d504c3d6e9c7c5f3482fb7e9e37800b6274824 Signed-off-by: Divya Jyothi <divya.jyothi@intel.com> Reviewed-on: https://chromium-review.googlesource.com/226303 Reviewed-by: Vic Yang <victoryang@chromium.org>
* lpc: ACPI query-next-event drops masked eventsRandall Spangler2014-04-171-3/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously, you could use EC_CMD_ACPI_QUERY_EVENT to read events that were masked off (that is, events which would not generate SCI/SMI/wake signals). The handlers for those signals on the host would still act on the masked-off events - for example, causing unwanted power button keypresses/releases. Now, EC_CMD_ACPI_QUERY_EVENT will only return events which are unmasked. This does not affect storing of events at event generation time. Events are still queued; they won't be dropped until the host attempts to read the next event. This gives the host a chance to set a mask later in boot (but before querying any events) to capture events which happened early in the boot process. BUG=chrome-os-partner:26574 BRANCH=rambi TEST=At EC console, type 'hostevent set 0x80' but don't press enter. Hold down the power button; UI starts fading to white. Press enter at the EC console to issue the hostevent command. System should continue shutting down, not fade back as if the power button were released. Change-Id: Id2cb14b0979f49cdd42424b9a61b310a2bb506f5 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/194935 Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* force the compiler to use a valid register allocation for irq handlersVincent Palatin2014-03-111-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When we are calling the re-scheduling routine at the end of an irq handling routine, we need to ensure that the high registers are not currently saved on the system stack. On Cortex-M3/M4, the compiler is normally doing tail-call optimization there and behaving properly, but this fixes the fact that insanely large interrupt handling routines where sometimes not compile and not running properly (aka issue 24515). This also prepares for one more core-specific DECLARE_IRQ routine on Cortex-M0. Note: now on, the IRQ handling routines should no longer be "static". Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=chrome-os-partner:24515 TEST=make -j buildall revert the workaround for 24515, see the issue happening only without this CL. Change-Id: Ic419369231925568df05815fd079ed191a5446db Reviewed-on: https://chromium-review.googlesource.com/189153 Reviewed-by: Vic Yang <victoryang@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
* mec1322: Use EMI module for port 80Vic (Chun-Ju) Yang2014-01-171-6/+13
| | | | | | | | | | | | | | | EMI module is the only LPC module suitable for port 80 implementation, and thus let's move it to 0x80. Consequently the EMI mapped memory is moved to 0x82-0x87. BUG=chrome-os-partner:24107 TEST=Write to port 80 and see the data printed to console BRANCH=None Change-Id: I7d749650d6d109af2941a1db6e6c4a32e7482f61 Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182796 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* mec1322: disable host write to mapped memoryVic (Chun-Ju) Yang2014-01-171-1/+1
| | | | | | | | | | | | | | EMI module has the ability to set different read and write ranges. Let's disable write on mapped memory. BUG=chrome-os-partner:24107 TEST=Write to mapped memory has no effect BRANCH=None Change-Id: I88654bde9208376103d3c084ee54991d886ea4cc Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182795 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* mec1322: Use internal SCI pin controlVic (Chun-Ju) Yang2014-01-091-3/+10
| | | | | | | | | | | | | | | Instead of requiring a GPIO definition, default to using the internal SCI pin control. BUG=chrome-os-partner:24550 TEST=Trigger SCI and verify with logic analyzer BRANCH=None Change-Id: I13ac3b8f1031d3c56ea0b8f6a6ed0c1aa4e77bb1 Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182010 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cleanup: Remove checkpatch warningsRandall Spangler2013-12-191-1/+1
| | | | | | | | | | | | | | | | This make minor syntactic changes and renames some camel-cased symbols to keep checkpatch from complaining. The goal is to reduce the temptation to use 'repo upload --no-verify'. This is a big furball of find/replace, but no functional changes. BUG=chromium:322144 BRANCH=none TEST=build all boards; pass unit tests Change-Id: I0269b7dd95836ef9a6e33f88c003ab0f24f842a0 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/180495
* mec1322: i8042 interfaceVic (Chun-Ju) Yang2013-12-171-0/+51
| | | | | | | | | | | | | This implements i8042 keyboard interface at LPC 0x60/0x64. BUG=chrome-os-partner:21407 TEST=Enable keyboard and keystroke from host ACPI commands. Short KSO pins and KSI pins, and read different key codes from host. BRANCH=None Change-Id: Ie4e5e236bdeefd7e44974f92fcbafab5e4af2b30 Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179940
* mec1322: ACPI and host event supportVic (Chun-Ju) Yang2013-12-141-6/+157
| | | | | | | | | | | | | | | | | This wires 0x62/0x66 to ACPI module and also implements the host event functions. BUG=chrome-os-partner:24107 TEST=ACPI memory test and compliment memory test. TEST=Set SCI mask and host event to trigger SCI. Check SCI pin pulse low. TEST=Query host event from ACPI. BRANCH=None Change-Id: Ib1f557e995a861c92a603491229ad361e17d2129 Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179942 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Move ACPI stuff out of chip/lm4 and into commonBill Richardson2013-12-121-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The port 62/66 ACPI commands were implemented in chip/lm4/lpc.c. They should be handled in common instead of being tied to a particular EC. BUG=chrome-os-partner:23774 BRANCH=none TEST=manual read EC_ACPI_MEM_VERSION # iotools io_write8 0x66 0x80; iotools io_write8 0x62 0; iotools io_read8 0x62 0x01 write & read EC_ACPI_MEM_TEST # iotools io_write8 0x66 0x81; iotools io_write8 0x62 1; iotools io_write8 0x62 0xa5 # iotools io_write8 0x66 0x80; iotools io_write8 0x62 1; iotools io_read8 0x62 0xa5 # iotools io_write8 0x66 0x80; iotools io_write8 0x62 2; iotools io_read8 0x62 0x5a # iotools io_write8 0x66 0x81; iotools io_write8 0x62 1; iotools io_write8 0x62 0xbb # iotools io_write8 0x66 0x80; iotools io_write8 0x62 1; iotools io_read8 0x62 0xbb # iotools io_write8 0x66 0x80; iotools io_write8 0x62 2; iotools io_read8 0x62 0x44 read & write EC_ACPI_MEM_KEYBOARD_BACKLIGHT # iotools io_write8 0x66 0x81; iotools io_write8 0x62 3; iotools io_write8 0x62 100 (keyboard lights up) # iotools io_write8 0x66 0x80; iotools io_write8 0x62 3; iotools io_read8 0x62 0x64 # iotools io_write8 0x66 0x81; iotools io_write8 0x62 3; iotools io_write8 0x62 50 (keyboard dimmer) # iotools io_write8 0x66 0x80; iotools io_write8 0x62 3; iotools io_read8 0x62 0x32 # iotools io_write8 0x66 0x81; iotools io_write8 0x62 3; iotools io_write8 0x62 0 (keyboard goes dark) # iotools io_write8 0x66 0x80; iotools io_write8 0x62 3; iotools io_read8 0x62 0x00 read & write EC_ACPI_MEM_FAN_DUTY # iotools io_write8 0x66 0x81; iotools io_write8 0x62 4; iotools io_write8 0x62 100 (fan on full) # iotools io_write8 0x66 0x80; iotools io_write8 0x62 4; iotools io_read8 0x62 0x64 # iotools io_write8 0x66 0x81; iotools io_write8 0x62 4; iotools io_write8 0x62 50 (fan on half speed) # iotools io_write8 0x66 0x80; iotools io_write8 0x62 4; iotools io_read8 0x62 0x32 # iotools io_write8 0x66 0x81; iotools io_write8 0x62 4; iotools io_write8 0x62 0 (fan off) # iotools io_write8 0x66 0x80; iotools io_write8 0x62 4; iotools io_read8 0x62 0x00 # iotools io_write8 0x66 0x81; iotools io_write8 0x62 4; iotools io_write8 0x62 0xff (fan back to EC control) # iotools io_write8 0x66 0x80; iotools io_write8 0x62 4; iotools io_read8 0x62 0xff test EC_CMD_ACPI_QUERY_EVENT # iotools io_write8 0x66 0x84; iotools io_read8 0x62 0x00 On EC console: > hostevent set 0x0f000000 # ectool eventget Current host events: 0x0f000000 # iotools io_write8 0x66 0x84; iotools io_read8 0x62 0x19 # iotools io_write8 0x66 0x84; iotools io_read8 0x62 0x1a # iotools io_write8 0x66 0x84; iotools io_read8 0x62 0x1b # iotools io_write8 0x66 0x84; iotools io_read8 0x62 0x1c # iotools io_write8 0x66 0x84; iotools io_read8 0x62 0x00 # ectool eventget Current host events: 0x00000000 Change-Id: I011a5a2051171ec1d37e55ce03e1ce74b93a7e14 Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179692
* mec1322: LPC host command supportVic (Chun-Ju) Yang2013-12-041-0/+168
With this, basic host command functionality is working. We don't have the correct description of LPC memory BAR register yet, so we have to use EMI (embedded memory interface) module for 0x800-0x9ff region. This requires a slightly different protocol, which is in the next CL. BUG=chrome-os-partner:24107 TEST=Wire EVB to Stumpy. 'ectool hello' and 'ectool version' working. BRANCH=None Change-Id: I873b4a455cf692e479321a5c6e18c8f33df60e66 Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/178250 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
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