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* ish: Trim down the release branchstabilize-wristpin-14469.59.B-ishstabilize-voshyr-14637.B-ishstabilize-quickfix-14695.187.B-ishstabilize-quickfix-14695.124.B-ishstabilize-quickfix-14526.91.B-ishstabilize-14695.85.B-ishstabilize-14695.107.B-ishstabilize-14682.B-ishstabilize-14633.B-ishstabilize-14616.B-ishstabilize-14589.B-ishstabilize-14588.98.B-ishstabilize-14588.14.B-ishstabilize-14588.123.B-ishstabilize-14536.B-ishstabilize-14532.B-ishstabilize-14528.B-ishstabilize-14526.89.B-ishstabilize-14526.84.B-ishstabilize-14526.73.B-ishstabilize-14526.67.B-ishstabilize-14526.57.B-ishstabilize-14498.B-ishstabilize-14496.B-ishstabilize-14477.B-ishstabilize-14469.9.B-ishstabilize-14469.8.B-ishstabilize-14469.58.B-ishstabilize-14469.41.B-ishstabilize-14442.B-ishstabilize-14438.B-ishstabilize-14411.B-ishstabilize-14396.B-ishstabilize-14395.B-ishstabilize-14388.62.B-ishstabilize-14388.61.B-ishstabilize-14388.52.B-ishstabilize-14385.B-ishstabilize-14345.B-ishstabilize-14336.B-ishstabilize-14333.B-ishrelease-R99-14469.B-ishrelease-R98-14388.B-ishrelease-R102-14695.B-ishrelease-R101-14588.B-ishrelease-R100-14526.B-ishfirmware-cherry-14454.B-ishfirmware-brya-14505.B-ishfirmware-brya-14505.71.B-ishfactory-kukui-14374.B-ishfactory-guybrush-14600.B-ishfactory-cherry-14455.B-ishfactory-brya-14517.B-ishJack Rosenthal2021-11-051-510/+0
| | | | | | | | | | | | | | | | | | | | | | In the interest of making long-term branch maintenance incur as little technical debt on us as possible, we should not maintain any files on the branch we are not actually using. This has the added effect of making it extremely clear when merging CLs from the main branch when changes have the possibility to affect us. The follow-on CL adds a convenience script to actually pull updates from the main branch and generate a CL for the update. BUG=b:204206272 BRANCH=ish TEST=make BOARD=arcada_ish && make BOARD=drallion_ish Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I17e4694c38219b5a0823e0a3e55a28d1348f4b18 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3262038 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Tom Hughes <tomhughes@chromium.org>
* chip: support dynamic hibernate_wake_pins configTing Shen2020-08-061-0/+5
| | | | | | | | | | | | | | | | Add CONFIG_HIBERNATE_WAKE_PINS_DYNAMIC to let board config their wake pins at runtime. BUG=b:162814191 TEST=make BRANCH=master Signed-off-by: Ting Shen <phoenixshen@google.com> Change-Id: Iae2072ec7239a0daa84222c23733b90153e732f1 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2340730 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Commit-Queue: Ting Shen <phoenixshen@chromium.org> Tested-by: Ting Shen <phoenixshen@chromium.org>
* ec: change usage of dummySam Hurst2020-08-051-1/+1
| | | | | | | | | | | | | | | | | | Google is working to change its source code to use more inclusive language. To that end, replace the term "dummy" with inclusive alternatives. BUG=b:162781382 BRANCH=None TEST=make -j buildall `grep -ir dummy *` The only results are in "private/nordic_keyboard/sdk8.0.0" which is not our code. Signed-off-by: Sam Hurst <shurst@google.com> Change-Id: I6a42183d998e4db4bb61625f962867fda10722e2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2335737 Reviewed-by: Tom Hughes <tomhughes@chromium.org>
* LICENSE: remove unnecessary (c) after CopyrightTom Hughes2019-06-191-1/+1
| | | | | | | | | | | | | | | | Ran the following command: git grep -l 'Copyright (c)' | \ xargs sed -i 's/Copyright (c)/Copyright/g' BRANCH=none BUG=none TEST=make buildall -j Change-Id: I6cc4a0f7e8b30d5b5f97d53c031c299f3e164ca7 Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1663262 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* common: replace 1 << digits, with BIT(digits)Gwendal Grignou2019-03-261-14/+14
| | | | | | | | | | | | | | | | Requested for linux integration, use BIT instead of 1 << First step replace bit operation with operand containing only digits. Fix an error in motion_lid try to set bit 31 of a signed integer. BUG=None BRANCH=None TEST=compile Change-Id: Ie843611f2f68e241f0f40d4067f7ade726951d29 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1518659 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* pwm: Add PWM_CONFIG_DSLEEP config flagShawn Nematbakhsh2016-04-271-0/+5
| | | | | | | | | | | | | | | | | | | Add PWM_CONFIG_DSLEEP PWM config flag, which can be set to keep a channel active during low-power idle / deep sleep. Currently it's supported by npcx and mec1322. BUG=chrome-os-partner:52783 BRANCH=glados TEST=Manual on chell w/ subsequent commit + CONFIG_LOW_POWER_S0. Verify KB backlight does not flicker during idle. Change-Id: Ib9df5879aaa7dfa5764de1583496de84d40d2bb5 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/341002 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Todd Broch <tbroch@chromium.org>
* mec1322: hibernate: Don't reconfigure all GPIOsShawn Nematbakhsh2016-01-251-8/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Configuring all GPIOs to INPUT / PULL_UP in hibernate is not a good idea: - INPUT / PULL_UP is not necessarially the lowest-power state (for example, if there is an onboard pull-down). - Most GPIOs should already be in lowest-power state when we're in S5. - For the few GPIOs that need to be in a different state for hibernate, we can use a board-level callback. In addition, remove mec1322 code related to restoring from hibernate state, since we always reset coming out of hibernate. BUG=chrome-os-partner:49608 BRANCH=glados, strago TEST=`hibernate` on chell console when in S5 and AC removed. Verify that EC power is roughly equivalent to low-power idle power. Attach Zinger, verify that device wakes and boots, and charges from charger. Change-Id: Ib00ef035bec32cea3847eb38d743f5c0cec896ca Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/322937 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Todd Broch <tbroch@chromium.org>
* mec1322: clocks: Don't squash reserved bits in sleep / wakeShawn Nematbakhsh2015-09-101-0/+12
| | | | | | | | | | | | | | | | | | Keep the state of reserved bits in SLP_EN registers when sleeping and waking from sleep. BUG=chrome-os-partner:45003 TEST=Manual on glados. Go to S3 and measure EC power. Go to deep sleep and wake. Re-measure power and verify that it is not ~60% higher than originally measured. BRANCH=Strago Change-Id: I6b6b0efcd146fe1a68b41b9b33b25740090dc08f Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/298655 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org>
* mec1322: Allow GPIO hibernate state to be specified at board-levelShawn Nematbakhsh2015-08-111-0/+7
| | | | | | | | | | | | | | | | Add a new board-level function board_get_gpio_hibernate_state which can optionally be defined to set the desired state of a GPIO during hibernate. BUG=chrome-os-partner:43807 TEST=Manual on Glados with subsequent commit. Run 'hibernate' on console, verify that LED remains off. Press power button, verify that board wakes. BRANCH=None Change-Id: Ica11554e231e88773c3e139fea4622377ebe1e42 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/292471 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* mec1322: heavysleep in idle task and console deepsleepKyoung Kim2015-07-171-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Implemented mec1322's heavysleep in idle task to reduce further EC power down on S3. MEC1322 needs sleep-enabled for all blocks to acheive max power down including UART. Real heavysleep will be effective only when console/uart is not active. To enable this commit, board-specific commit is required. For example, check commit, "Enabling heavysleep idle task at S3". Test: 1. Put device into S3 mode by typing 'powerd_dbus_suspend" in Linux shell. 2. wait at least 1 min till EC console sleeps 3. measure EC power. Since idle task is continuously scheduled, EC will enters/exits to/from heavy sleep mode frequently in S3 and power consumption will be changed dynamically. For acurate power measurement, high-sampling-rate measurement system might be required and using DMM might not give accurate number. BUG=None TEST=Tested on evt1p0/evt1p7/DVT BRANCH=None Change-Id: I435ca347cab2f4d51cefeee802c3bf30fb393fa1 Signed-off-by: Kyoung Kim <kyoung.il.kim@intel.com> Reviewed-on: https://chromium-review.googlesource.com/283603 Reviewed-by: Alec Berg <alecaberg@chromium.org> Tested-by: Alec Berg <alecaberg@chromium.org> Commit-Queue: Alec Berg <alecaberg@chromium.org>
* mec1322: Allow multiple hibernate wake sourcesShawn Nematbakhsh2015-07-161-0/+4
| | | | | | | | | | | | | | | | | Allow multiple GPIOs to wake the EC from hibernate by requiring boards to define hibernate_wake_pins and hibernate_wake_pins_used. In addition, clean up the GPIO-skipping hibernate code, and skip setting PCH_RTCRST as an input due to a bug on certain boards. BUG=chrome-os-partner:42104 TEST=Manual on Glados. Run 'hibernate' from EC console, verify that EC wakes with power button press or with "dut-control lid_open:no". BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I13a6e062393cab8ed7129eda253585951f771109 Reviewed-on: https://chromium-review.googlesource.com/285924 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* mec1322: Fix reset cause detectionDivya Jyothi2015-07-131-0/+3
| | | | | | | | | | | | | | | | | | | | | | | Mec1322 cannot distinguish between Power-on and reset condition. MEC1322_EC_WDT_CNT was used to determine the power-on condition. VBAT_POR cannot not be used to distinguish no battery condition. All of the feautures that need support need to determine VCC1_REST which is used for reset considion. lfw and main code use the same condition. When VCC1_RESET is asserted we need to set the image type to RO image for sysjump to work correctly. This in turn will affect Recovery mode,software sync and Flashrom. All of these conditions were tested with this patch. BUG=chrome-os-partner:40526 TEST=Recovery mode,Software Sync,Flashrom BRANCH=None Change-Id: I65f2aa9f56863597116b875ea436d4413887b92b Signed-off-by: Divya Jyothi <divya.jyothi@intel.com> Reviewed-on: https://chromium-review.googlesource.com/283605 Reviewed-by: Shawn N <shawnn@chromium.org>
* mec1322: Correctly get reset causeDivya Jyothi2015-06-241-0/+3
| | | | | | | | | | | | | | | | | | Since the reset cause was not recorded correctly recovery mode(Esc+Refresh+Power) was not working. With this change power-on reset state and VCC1_RST# only state are distinguinshed. BUG=chrome-os-partner:41479 BRANCH=none TEST=Esc+Refresh+Power boots to recovery screen Refresh+Power reboots the system Change-Id: I63eff488c970302e7afe8a677a57ad27d4d9918e Signed-off-by: Divya Jyothi <divya.jyothi@intel.com> Signed-off-by: Freddy Paul <freddy.paul@intel.com> Reviewed-on: https://chromium-review.googlesource.com/280782 Reviewed-by: Shawn N <shawnn@chromium.org>
* mec1322: Added support for sysjump.stabilize-7173.BDivya Jyothi2015-06-141-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | changes added to support flashrom are: sysjump support to be able to copy the RO/RW image and jump to it without causing AP to reboot while its alreday ON. LPC init should be reinitialized on sysjump corrected gpio_set_flags_by_mask to make sure we update the register only for GPIO_LOW condition and not all else conditions. BUG=chrome-os-partner:38103 TEST=commands : flashrom -p ec -w ec.bin flashrom -p ec -r ec.bin BRANCH=none Change-Id: I23892f0378d756052030e73034c3acdd41477e34 Signed-off-by: Divya Jyothi <divya.jyothi@intel.com> Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/272000 Reviewed-by: Shawn N <shawnn@chromium.org>
* mec1322: Simplify GPIO listsSteven Jian2015-05-271-3/+2
| | | | | | | | | | | | | | | Our existing GPIO macros use port# / gpio#, but the concept of different GPIO ports does not exist on the mec1322. Therefore, add new GPIO macros for chips which do not have distinct GPIO ports. BUG=None BRANCH=None TEST=make buildall -j Change-Id: Ibda97c6563ad447d16dab39ecadab43ccb25174b Signed-off-by: Steven Jian <steven.jian@intel.com> Reviewed-on: https://chromium-review.googlesource.com/262841 Reviewed-by: Anton Staaf <robotboy@chromium.org>
* mec1322: Added task-based Port80 POST code support.Kevin K Wong2015-04-271-0/+4
| | | | | | | | | | | | | | | | | | | | | | With mec1322's EMI set to decode IO 0x800, it does not have any other interfaces to support POST code via IO 0x80. This change is to enable Port80 POST code support via polling method. Limitation: - POST Code 0xFF will be ignored. - POST Code frequency is greater than 1 msec. BUG=chrome-os-partner:39386 TEST=Verified Port80 POST code is captured in EC console. Verified "port80 task" console command will disable/enable Port80 task. Verified "port80 poll" will get the last Port80 POST code. BRANCH=none Change-Id: I27e53e84b5be1fd98464a44407dd58b93d8c798d Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-on: https://chromium-review.googlesource.com/266783 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* mec1322: i2c: Support multiple I2C ports on the same controllerShawn Nematbakhsh2015-04-221-25/+38
| | | | | | | | | | | | | | | mec1322 I2C controller 0 has two attached ports. Modify the I2C driver so that both ports are usable. BUG=chrome-os-partner:38335,chrome-os-partner:38945 TEST=Manual on strago. Verify that i2cscan is functional. BRANCH=None Change-Id: I18d9d516984d041a38c86fd4ec1b0bfa4e885c9f Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/265951 Reviewed-by: Divya Jyothi <divya.jyothi@intel.com> Reviewed-by: Alec Berg <alecaberg@chromium.org>
* Strago: Initial Version of Strago Board added.Divya Jyothi2014-11-061-0/+1
| | | | | | | | | | | | | | | | | | | Modules that are enabled are listed below: - Power Sequencing - Keyboard Scan and Protocol - LPC to support Keyboard - Power Button Task ec.spi.bin has to be generated manualy using pack_ec.py BUG=None BRANCH=None TEST=Tested on Stargo-Proto board Change-Id: Ic5d504c3d6e9c7c5f3482fb7e9e37800b6274824 Signed-off-by: Divya Jyothi <divya.jyothi@intel.com> Reviewed-on: https://chromium-review.googlesource.com/226303 Reviewed-by: Vic Yang <victoryang@chromium.org>
* mec1322: Add SPI master driverVic Yang2014-06-261-0/+11
| | | | | | | | | | | | | | This allows us to use the two SPI ports as SPI master. Also, to save CPU time on reading large amount of data, let's add an async interface for SPI transaction. BUG=chrome-os-partner:29805 TEST=Read manufacturer ID from SPI flash with sync/async interface BRANCH=None Change-Id: I427f4215602cccc55c4151f4116226b1e0ccc15e Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/204719
* mec1322: DMA driverVic Yang2014-06-261-0/+75
| | | | | | | | | | | | | | | This implements the DMA driver using the same DMA interface we are using now. BUG=chrome-os-partner:29805 TEST=Along with the following SPI driver, read manufacturer ID from SPI flash. BRANCH=None Change-Id: Ife3c0c8b414568ff1cab7d072901ba2d11142a17 Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/205067 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* mec1322: hibernation supportstabilize-5339.BVic (Chun-Ju) Yang2014-01-281-0/+8
| | | | | | | | | | | | | | | This adds hibernation support. The chip can be waken by either GPIO or a timer. The maximum delay allowed is ~2 hours. BUG=chrome-os-partner:24107 TEST=hibernate and wake by GPIO TEST=hibernate and wake by timer BRANCH=None Change-Id: I1e064638a5008894a002a06a738bf6104f18636d Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/181202 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* mec1322: Refine reset cause detectionVic (Chun-Ju) Yang2014-01-111-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | The VBAT POR indication is unreliable for detecting a power-on reset, and thus we often see "unknown" reset cause when we should see "power-on". A better indication is to check for VCC1 POR, which manifests by clearing watchdog count. The catch is that we still cannot tell power-on reset from reset-pin reset. Also, to distinguish soft/hard reset from actual watchdog reset, we need to explicitly save soft/hard reset flag before triggering watchdog reset. BUG=chrome-os-partner:24107 TEST=Power cycle EVB and see 'power-on' reset cause. TEST='reboot' and see 'soft' reset cause. TEST='reboot hard' and see 'hard' reset cause. TEST='waitms 2000' and see 'watchdog' reset cause. BRANCH=None Change-Id: I0075f5bf5cdb032d206c4a53c586b75b69093235 Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182120 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* mec1322: Use internal SCI pin controlVic (Chun-Ju) Yang2014-01-091-0/+12
| | | | | | | | | | | | | | | Instead of requiring a GPIO definition, default to using the internal SCI pin control. BUG=chrome-os-partner:24550 TEST=Trigger SCI and verify with logic analyzer BRANCH=None Change-Id: I13ac3b8f1031d3c56ea0b8f6a6ed0c1aa4e77bb1 Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182010 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* mec1322: ADC driverVic (Chun-Ju) Yang2013-12-201-0/+10
| | | | | | | | | | | | | ADC driver for MEC1322 with ADC interrupt support. BUG=chrome-os-partner:24107 TEST=Read single channel TEST=Read all channels BRANCH=None Change-Id: I89d196c7fd78e736575e2c368b65cfb1ec651004 Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/180832
* mec1322: i8042 interfaceVic (Chun-Ju) Yang2013-12-171-0/+11
| | | | | | | | | | | | | This implements i8042 keyboard interface at LPC 0x60/0x64. BUG=chrome-os-partner:21407 TEST=Enable keyboard and keystroke from host ACPI commands. Short KSO pins and KSI pins, and read different key codes from host. BRANCH=None Change-Id: Ie4e5e236bdeefd7e44974f92fcbafab5e4af2b30 Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179940
* mec1322: keyboard scan supportVic (Chun-Ju) Yang2013-12-131-0/+11
| | | | | | | | | | | | | | | | | | | | | This adds keyboard scan module driver. Keyboard scan task is not enabled yet as the LPC layer is not finished and thus i8042 protocol cannot be enabled. Since KSO00-KSO03 are used as JTAG, we use KSO04-KSO16 so as to preserve JTAG functionality. Unfortunately we don't have enough KSO pins, so trace debug port must be disabled, as done in this CL. BUG=chrome-os-partner:24107 TEST=Set 'ksstate on'. Short KSI pins and KSO pins, and see corresponding key shown as pressed. TEST=Check keypress is detected when console shows 'KB wait'. BRANCH=None Change-Id: I366a27453ef95030d251e525313eb4627eb4340f Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179319 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* mec1322: I2C driverVic (Chun-Ju) Yang2013-12-061-0/+33
| | | | | | | | | | | | | | | | | | This adds the driver for MEC1322 I2C controller. BUG=chrome-os-partner:24107 TEST=Hook up TSU6721 to eval board. Do the following tests: - 'i2cscan' and see TSU6721. - Read device ID register and get correct value. - Add 3 tasks randomly doing I2C read and writes. Check there is no error. BRANCH=None Change-Id: I465f73fe8177a8df6b56c57e594cd733caea37d4 Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/178591 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* mec1322: Fan control driverVic (Chun-Ju) Yang2013-12-041-0/+18
| | | | | | | | | | | | | | | | | | | | This adds the driver for PWM duty cycle based and RPM based fan control. BUG=chrome-os-partner:24107 TEST='fanset 5000' and fan spins up. 'fanset 8000' and fan spins faster. 'fanset 0' and fan stops. 'fanduty 30' and fan spins up. 'fanduty 50' and fan spins faster. 'fanduty 30' and fan slows down. 'fanset 6000' and fan goes to ~6000 RPM. Unplug fan power and see 'fan 0 stalled'. Plug power back and doesn't see stall warning anymore. BRANCH=None Change-Id: Ice3e5c03686cde57894e888e34ae2070c33b4e4d Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/178402
* mec1322: LPC host command supportVic (Chun-Ju) Yang2013-12-041-0/+8
| | | | | | | | | | | | | | | | | | | With this, basic host command functionality is working. We don't have the correct description of LPC memory BAR register yet, so we have to use EMI (embedded memory interface) module for 0x800-0x9ff region. This requires a slightly different protocol, which is in the next CL. BUG=chrome-os-partner:24107 TEST=Wire EVB to Stumpy. 'ectool hello' and 'ectool version' working. BRANCH=None Change-Id: I873b4a455cf692e479321a5c6e18c8f33df60e66 Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/178250 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* mec1322: Add PWM driverVic (Chun-Ju) Yang2013-12-021-0/+8
| | | | | | | | | | | | | | | | This adds a PWM driver, which now generates 30KHz PWM output. Note that this is different from fan control module driver. BUG=chrome-os-partner:24107 TEST=Set GPIO136 to PWM1. Attach logic analyzer to monitor its output. - Set to active high and 30%, see 30% duty PWM at ~29.1KHz. - Set to active low and 20%, see 80% duty PWM at ~29.1KHz. BRANCH=None Change-Id: I5f1001d5a4701e19fa87c4cabfd4ae5ae7ccb30c Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/178391 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* mec1322: Add support for VBAT backed RAMVic (Chun-Ju) Yang2013-12-021-0/+1
| | | | | | | | | | | | | | This will be used for saving data across reboots. BUG=chrome-os-partner:24107 TEST=Enable scratchpad command and check value is preserved across watchdog reboot. BRANCH=None Change-Id: Ifd68541a3f842c466b6ff49bcc654c92df48aac6 Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/178276 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* mec1322: Add more register address and IRQ numbersVic (Chun-Ju) Yang2013-11-271-0/+95
| | | | | | | | | | | | | No functional changes. Just adding more chip-specific constants. BUG=chrome-os-partner:24107 TEST=Build mec1322_evb BRANCH=None Change-Id: I649ad2656da941c28a2a738007ced955cd25ea75 Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/178170 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* mec1322: initial commitVic (Chun-Ju) Yang2013-11-211-0/+152
This is the initial commit of mec1322 support. This includes: - Basic GPIO driver. Interrupt not supported yet. - Microsecond timer - UART driver The script to pack the firmware binary will be checked in in following-up CL. BUG=chrome-os-partner:24107 TEST=Build and boot on eval board BRANCH=None Change-Id: I9013c908049d1f740f84bb56abca51b779f39eef Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/175716 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
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