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* system: fix system_get_scratchpad APIYuval Peress2021-08-201-2/+3
| | | | | | | | | | | | | | | The current API for system_get_scratchpad mixes the status and the value being read. Update the signature to allow both. BRANCH=none BUG=b:195481980 TEST=make testall && zmake testall Signed-off-by: Yuval Peress <peress@chromium.org> Change-Id: I3a5f5ad523d507c53a5d474806f58afafb82e70c Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3074828 Commit-Queue: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Denis Brockus <dbrockus@chromium.org>
* spi: Pass in spi_device as argument to spi_enable instead of portTom Hughes2021-01-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | Rather than passing in the port and iterating over the global spi_devices variable, pass in the specific spi_device that is being enabled/disabled. The spi_device_t struct has the port. This change makes the functions in spi.h more consistent since they now all take a spi_device_t*. This change is the first step in making the SPI configuration more dynamic. BRANCH=none BUG=b:177908650 TEST=git grep 'spi_enable(CONFIG' => no results TEST=make buildall TEST=Flash dragonclaw v0.2 and view console to verify FP sensor ID Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: I64124e0ebcf898e88496acb77703b5f59ae931c2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2654081 Commit-Queue: Abe Levkoy <alevkoy@chromium.org> Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
* Replace __attribute__((noreturn)) with noreturnTom Hughes2020-08-171-1/+1
| | | | | | | | | | | | | | | _Noreturn was added in C11 and the convenience macro "noreturn" is specified by stdnoreturn.h: https://en.cppreference.com/w/c/language/_Noreturn. BRANCH=none BUG=none TEST=make buildall -j Signed-off-by: Tom Hughes <tomhughes@chromium.org> Change-Id: I30361bb5290cea1c776a7356f7e3a68edf1f8e39 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2324816 Reviewed-by: Ting Shen <phoenixshen@chromium.org>
* common/system: Unify ec_current_image and system_image_copy_tTom Hughes2020-02-281-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | "enum ec_current_image" is exposed in ec_commands.h (and used by non-EC code, such as biod). We also have an "enum system_image_copy_t" that is the exact same thing (though has a few more definitions). A followup CL (I714b6bd8c0d7192386404c25a831e38438fa5238) adds the "sysinfo" host command, so we want to be able to expose all the potential image variants. Rather than maintain two enums that can potentially get out of sync, unify the code to use a single enum. We choose to keep the "enum ec_current_image", since external code depends on it. To verify that this change results in no changes to the generated binaries: ./util/compare_build.sh --board all BRANCH=none BUG=b:146447208 TEST=./util/compare_build.sh --board=all Change-Id: I13776bc3fd6e6ad635980476a35571c52b1767ac Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2036599 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Namyoon Woo <namyoon@chromium.org>
* Add a board specific helper to return USB PD port countKarthikeyan Ramasubramanian2019-11-091-6/+20
| | | | | | | | | | | | | | | | | | | | | Certain SKUs of certain boards have less number of USB PD ports than configured in CONFIG_USB_PD_PORT_MAX_COUNT. Hence define an overrideable board specific helper to return the number of USB PD ports. This helps to avoid initiating a PD firmware update in SKUs where there are less number of USB PD ports. Also update charge manager to ensure that absent/ invalid PD ports are skipped during port initialization and management. BUG=b:140816510, b:143196487 BRANCH=octopus TEST=make -j buildall; Boot to ChromeOS in bobba(2A + 2C config) and garg(2A + 1C + 1HDMI config). Change-Id: Ie345cef470ad878ec443ddf4797e5d17cfe1f61e Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1879338 Tested-by: Karthikeyan Ramasubramanian <kramasub@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Commit-Queue: Karthikeyan Ramasubramanian <kramasub@chromium.org>
* Rename CONFIG_USB_PD_PORT_COUNT as CONFIG_USB_PD_PORT_MAX_COUNTKarthikeyan Ramasubramanian2019-11-011-4/+4
| | | | | | | | | | | | | | | | | Certain SKUs of certain boards have lesser number of USB PD ports than defined by CONFIG_USB_PD_PORT_COUNT. Hence rename CONFIG_USB_PD_PORT_COUNT as CONFIG_USB_PD_PORT_MAX_COUNT. BUG=b:140816510, b:143196487 BRANCH=octopus TEST=make -j buildall; Boot to ChromeOS Change-Id: I7c33b27150730a1a3b5813b7b4a72fd24ab73c6a Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1879337 Tested-by: Karthikeyan Ramasubramanian <kramasub@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Commit-Queue: Jett Rink <jettrink@chromium.org>
* cleanup: fix byte access and ifdefs for BBRAM_PD2Jett Rink2019-09-301-2/+3
| | | | | | | | | | | | | | Ensure that PD2 is accessed as a single byte instead of 4 bytes and remove unnecessary ifdef guards in all chip implementations. BRANCH=none BUG=none TEST=builds Change-Id: I319d8d6a8456662235ab4d8dcda6bda7e8ed7c15 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1809938 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* include: Move RESET_FLAG_* into ec_commands.h as EC_RESET_FLAG_*You-Cheng Syu2019-08-261-16/+16
| | | | | | | | | | | | | | | | | | | | | | | RESET_FLAGS_* are used when setting/reading the field ec_reset_flags of struct ec_response_uptime_info, which is defined in ec_commands.h. So it might be better to put those macros there. To be consistent with the other macros in the file, add "EC_" prefixes to them. BUG=b:109900671,b:118654976 BRANCH=none TEST=make buildall -j Cq-Depend: chrome-internal:1054910, chrome-internal:1054911, chrome-internal:1045539 Change-Id: If72ec25f1b34d8d46b74479fb4cd09252102aafa Signed-off-by: You-Cheng Syu <youcheng@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1520574 Tested-by: Yu-Ping Wu <yupingso@chromium.org> Commit-Ready: Yu-Ping Wu <yupingso@chromium.org> Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org> Reviewed-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* LICENSE: remove unnecessary (c) after CopyrightTom Hughes2019-06-191-1/+1
| | | | | | | | | | | | | | | | Ran the following command: git grep -l 'Copyright (c)' | \ xargs sed -i 's/Copyright (c)/Copyright/g' BRANCH=none BUG=none TEST=make buildall -j Change-Id: I6cc4a0f7e8b30d5b5f97d53c031c299f3e164ca7 Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1663262 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* common: chip_save_reset_flags takes uint32_tJack Rosenthal2019-05-171-1/+1
| | | | | | | | | | | | | | | The getters and setters for the reset flags should take and return the same type. `uint32_t' seems the more appropraiate type than `int', so change the setter to take `uint32_t'. BUG=none BRANCH=none TEST=make buildall -j Change-Id: I50928a114858dd51034a048520efa849f5182bd0 Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1615648 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* common: replace 1 << digits, with BIT(digits)Gwendal Grignou2019-03-261-3/+3
| | | | | | | | | | | | | | | | Requested for linux integration, use BIT instead of 1 << First step replace bit operation with operand containing only digits. Fix an error in motion_lid try to set bit 31 of a signed integer. BUG=None BRANCH=None TEST=compile Change-Id: Ie843611f2f68e241f0f40d4067f7ade726951d29 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1518659 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* system: Allow hibernate to clear AP_OFF flagDaisuke Nojiri2017-12-051-0/+5
| | | | | | | | | | | | | | | | | | | After firmware update, cr50 toggles the EC's reset line, expecting the system will boot. This isn't the case for Chromebox because it sets AP_OFF flag on a clean shutdown (to restore the previous power state after power loss & restore). This patch adds EC_REBOOT_HIBERNATE_CLEAR_AP_OFF to EC reboot command. It makes EC first clear AP_OFF then hibernate. BUG=b:69721737 BRANCH=none TEST=Verify Fizz reboot after cr50 update. Change-Id: If3207d7284f244ca1adf0d516ef744dbc739a9c1 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/802632 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* Mark reset and panic functions as noreturnPatrick Georgi2017-11-071-0/+1
| | | | | | | | | | | | | | | | | | | gcc 6.3 (as provided by coreboot-sdk) needs that to know which code paths end early. Also add a loop after the command that is "supposed" to reset the machine so that the compiler believes it (and in case that assumption fails). BRANCH=none BUG=b:65441143 TEST=none Change-Id: Idb87253ec7880d66ffec30d75f4d007f02f63aab Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://chromium-review.googlesource.com/742916 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
* Revert "system: Shutdown AP before entering hibernate mode"Duncan Laurie2017-04-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 20c439be209a9cc0bb949ad21f289c453126395f. Reason for revert: This breaks hibernate on skylake boards and needs to be tested on more than just kevin before submitting. BUG=chromium:702451 BRANCH=none TEST=power down and successfully hibernate on Eve Original change's description: > system: Shutdown AP before entering hibernate mode > > BUG=chromium:702451 > BRANCH=none > TEST=manually test on gru: confirm > 'Alt+VolUp+h' puts gru in hibernate mode and > AC plug-in wakes it up. > > Change-Id: I3e1134b866dea5d3cc61f9b3dad31c3ff0bd9096 > Reviewed-on: https://chromium-review.googlesource.com/470787 > Commit-Ready: Philip Chen <philipchen@chromium.org> > Tested-by: Philip Chen <philipchen@chromium.org> > Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> > TBR=rspangler@chromium.org,aaboagye@chromium.org,philipchen@chromium.org # Not skipping CQ checks because original CL landed > 1 day ago. BUG=chromium:702451 Change-Id: Ie847a5e3efb28256b00ddc6534d8ae6bbbba7121 Reviewed-on: https://chromium-review.googlesource.com/482989 Commit-Ready: Duncan Laurie <dlaurie@chromium.org> Tested-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* system: Shutdown AP before entering hibernate modePhilip Chen2017-04-141-1/+1
| | | | | | | | | | | | | | BUG=chromium:702451 BRANCH=none TEST=manually test on gru: confirm 'Alt+VolUp+h' puts gru in hibernate mode and AC plug-in wakes it up. Change-Id: I3e1134b866dea5d3cc61f9b3dad31c3ff0bd9096 Reviewed-on: https://chromium-review.googlesource.com/470787 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* pd: Store PD active state in battery-backed memoryShawn Nematbakhsh2017-02-251-8/+20
| | | | | | | | | | | | | | | | | | | | | | | | Our previous idea to cut Rd for many reset cases cannot work if cr50 consistently resets the EC by asserting the reset pin shortly after power-on. Therefore, make a decision based upon whether battery-backed memory indicates we previously negotiated a PD power contract as a sink. If we previously did not negotiate a contract, or if power was removed from the device (causing battery-backed memory to wipe) then we can assume that we don't have an active power contract. BUG=chrome-os-partner:62952 BRANCH=reef TEST=On reef, run "cutoff" on the console, reattach AC, and verify device successfully wakes. Also verify Rp is dropped on console 'reboot' and F3 + power from RW. Change-Id: Ie300b9589cac6be7a69b77678bea6b1b6b25578c Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/443356 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* system: Add generic bbram read / write routinesShawn Nematbakhsh2017-02-241-5/+21
| | | | | | | | | | | | | | | | | | Add generic routines to read or write a byte to battery-backed RAM, and implement vbnvcontext get/set using these routines. BUG=chrome-os-partner:62952 BRANCH=reef TEST=On reef, with subsequent commit, run "cutoff" on the console, reattach AC, and verify device successfully wakes. Also verify Rp is dropped on console 'reboot' and F3 + power from RW. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I14691923f2e5198e901b6b5199e92c58c68cd18d Reviewed-on: https://chromium-review.googlesource.com/444444 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* hibernate: Re-init GPIO levels on hibernate wakeShawn Nematbakhsh2016-10-071-1/+2
| | | | | | | | | | | | | | | | | | Reset-on-hibernate wake performs a soft-reset, which re-initializes GPIO states to ROM POR values. Therefore, it is necessary to re-init GPIO states once again based on board-level GPIO settings. BUG=chrome-os-partner:58077 BRANCH=gru TEST=Run `hibernate` on gru, wake, then run `bd99955_dump`. Verify actual register values are printed rather than zeros. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Ib3eb1dd6aa264d00d42d8e386bfd1ef7f6cf7717 Reviewed-on: https://chromium-review.googlesource.com/395426 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* GPIO: Rename and move board_set_gpio_hibernate_stateAnton Staaf2016-03-211-2/+2
| | | | | | | | | | | | | | | | | This function is no longer GPIO specific and fits better as part of the system API, so this moves it there and renames it board_hibernate_late. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Change-Id: I39d3ecedadaaa22142cc82c79f5d25c891f3f38c Reviewed-on: https://chromium-review.googlesource.com/330124 Commit-Ready: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* hibernate: Inform PD MCU before calling board hibernate callbackShawn Nematbakhsh2016-02-171-3/+3
| | | | | | | | | | | | | | | | | | board_hibernate() may take alternate actions to place the chip into hibernate, so inform the PD MCU that we're going to hibernate before calling the function. BUG=None TEST=Run 'hibernate' on chell, verify that PD MCU goes to hibernate and wakes when AC is attached. BRANCH=glados Change-Id: I71c12dcb416d54c79ac7d40e9bf430e268071fb2 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/327613 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* system: Add hibernate board-level callbackShawn Nematbakhsh2016-01-281-0/+3
| | | | | | | | | | | | | | | | | Allow boards to take action (such as entering a custom low-power hibernate-like state) before putting the chip into hibernate state. BUG=chrome-os-partner:48835 BRANCH=glados TEST=Manual with subsequent commit on chell. Verify board-level hibernate callback is called when "hibernate" is run on EC console. Change-Id: Ie1da044037a74ff8bce5c822f28ce837c62ceec0 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/324086 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* GPIO: Use gpio_reset in a few more placesAnton Staaf2016-01-271-7/+4
| | | | | | | | | | | | | | | | | | The new gpio_reset function simplifies the pattern used in this code, that of returning a GPIO to its original configured state. It also removes a few instances of using port/mask pairs. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Change-Id: I6e411aaf2f0fbc18aca0ed8742c400a0efe5690d Reviewed-on: https://chromium-review.googlesource.com/324059 Commit-Ready: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* mec1322: hibernate: Don't reconfigure all GPIOsShawn Nematbakhsh2016-01-251-151/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Configuring all GPIOs to INPUT / PULL_UP in hibernate is not a good idea: - INPUT / PULL_UP is not necessarially the lowest-power state (for example, if there is an onboard pull-down). - Most GPIOs should already be in lowest-power state when we're in S5. - For the few GPIOs that need to be in a different state for hibernate, we can use a board-level callback. In addition, remove mec1322 code related to restoring from hibernate state, since we always reset coming out of hibernate. BUG=chrome-os-partner:49608 BRANCH=glados, strago TEST=`hibernate` on chell console when in S5 and AC removed. Verify that EC power is roughly equivalent to low-power idle power. Attach Zinger, verify that device wakes and boots, and charges from charger. Change-Id: Ib00ef035bec32cea3847eb38d743f5c0cec896ca Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/322937 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Todd Broch <tbroch@chromium.org>
* mec1322: Do not set mux mode to GPIO in gpio_set_flags_by_mask()Shamile Khan2015-10-071-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | gpio_set_flags_by_mask() should only set the GPIO flags for a pin. gpio_set_alternate_function() should set all mux modes including GPIO mode for a pin. This bug was uncovered when a glitch was observed on EC's LRESET# pin which reset the LPC bus. The glitch was caused when the LPC interface was re-initialized during execution of EC RW image. While programming the EC pins for LPC interface, LRESET# pin was temporarily converted from LRESET# mode to GPIO mode by gpio_set_flags_by_mask() before it got set back to LRESET# mode by gpio_set_alternate_function() BUG=chrome-os-partner:44993 BRANCH=none TEST=Manually tested on Kunimitsu FAB3. Flashed a coreboot image in which LPC SERIRQ is set to quiet mode and Clock Run is enabled and than confirmed that keyboard is functional. Change-Id: I25865d38bd6b6b5785e4247831722c5a02032138 Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/304146 Reviewed-by: Shawn N <shawnn@chromium.org>
* pd: Allow EC to request PD hibernate via host commandShawn Nematbakhsh2015-10-051-0/+7
| | | | | | | | | | | | | | | | | | | On some systems, we may wish to have the PD follow the EC into hibernate. Add a status field to EC_CMD_PD_EXCHANGE_STATUS to support this. BUG=chrome-os-partner:45010 TEST=Manual on glados with subsequent commit. Run 'hibernate' on EC console, verify that both EC and PD go to hibernate. Plug zinger and verify that both EC and PD wake, AP boots, and battery begins charging. BRANCH=None Change-Id: I0476bc8a47ffb0fe113dccda9d4f8074105c1c84 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/302712 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* Rename gpio_is_reboot_warm() to system_is_reboot_warm()Vijay Hiremath2015-09-291-2/+1
| | | | | | | | | | | | | BUG=chrome-os-partner:40788 TEST=make buildall -j BRANCH=none Change-Id: I4fb248da4656374e1218af98678cfb694f4c9176 Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/302674 Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com> Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* cleanup: Rename geometry constantsShawn Nematbakhsh2015-09-161-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Rename and add geometry constants to match spec doc - https://goo.gl/fnzTvr. CONFIG_FLASH_BASE becomes CONFIG_PROGRAM_MEMORY_BASE CONFIG_FLASH_MAPPED becomes CONFIG_MAPPED_STORAGE Add CONFIG_INTERNAL_STORAGE, CONFIG_EXTERNAL_STORAGE and CONFIG_MAPPED_STORAGE_BASE where appropriate. This CL leaves chip/npcx in a broken state -- it's fixed in a follow-up CL. BRANCH=None BUG=chrome-os-partner:23796 TEST=With entire patch series, on both Samus and Glados: - Verify 'version' EC console command is correct - Verify 'flashrom -p ec -r read.bin' reads back EC image - Verify software sync correctly flashes both EC and PD RW images Change-Id: Idb3c4ed9f7f6edd0a6d49ad11753eba713e67a80 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/297484 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* mec1322: clocks: Don't squash reserved bits in sleep / wakeShawn Nematbakhsh2015-09-101-6/+6
| | | | | | | | | | | | | | | | | | Keep the state of reserved bits in SLP_EN registers when sleeping and waking from sleep. BUG=chrome-os-partner:45003 TEST=Manual on glados. Go to S3 and measure EC power. Go to deep sleep and wake. Re-measure power and verify that it is not ~60% higher than originally measured. BRANCH=Strago Change-Id: I6b6b0efcd146fe1a68b41b9b33b25740090dc08f Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/298655 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org>
* system: provide optional chip_save_reset_flags()Aaron Durbin2015-08-261-1/+6
| | | | | | | | | | | | | | | | | | | Certain boards may need to handle fixing up the RESET_FLAG_s because of the boards' designs. Provide an optional per-chip implementation to save the reset flags. Note that this function is not protected by a CONFIG_ option as it can just be implemented by the chip if a board requires it. Lastly, implement chip_save_reset_flags() for mec1322 for future use. BUG=chrome-os-partner:44527 BRANCH=None TEST=Built and booted on glados. Change-Id: I604fe4e6a069f31727bab52288595a349e3dbe72 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/295115 Reviewed-by: Robbie Zhang <robbie.zhang@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* glados: Turn off LEDs in hibernateShawn Nematbakhsh2015-08-111-8/+0
| | | | | | | | | | | | | | | Use new board-level hibernate GPIO state function to turn off LEDs in hibernate. BUG=chrome-os-partner:43807 TEST=Manual on Glados with subsequent commit. Run 'hibernate' on console, verify that LED remains off. Press power button, verify that board wakes. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Id695df9b5e75514f8f807a894b63f71676b66f92 Reviewed-on: https://chromium-review.googlesource.com/292317 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* mec1322: Allow GPIO hibernate state to be specified at board-levelShawn Nematbakhsh2015-08-111-37/+36
| | | | | | | | | | | | | | | | Add a new board-level function board_get_gpio_hibernate_state which can optionally be defined to set the desired state of a GPIO during hibernate. BUG=chrome-os-partner:43807 TEST=Manual on Glados with subsequent commit. Run 'hibernate' on console, verify that LED remains off. Press power button, verify that board wakes. BRANCH=None Change-Id: Ica11554e231e88773c3e139fea4622377ebe1e42 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/292471 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* common: change interface to SPI flashGwendal Grignou2015-07-301-1/+1
| | | | | | | | | | | | | | | | Allow more than one SPI master. Add CONFIG variables to address the system SPI flash. To have SPI master ports, spi_ports array must be defined. BRANCH=smaug TEST=compile BUG=chrome-os-partner:42304 Change-Id: Id43869f648965c1582b7be1c7fb3a38f175fda95 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/288512 Commit-Queue: David James <davidjames@chromium.org>
* glados: V2 Board ChangesShawn Nematbakhsh2015-07-241-1/+1
| | | | | | | | | | | | | | | Changes for glados proto 2 build. These changes are behind GLADOS_BOARD_V2, which is not defined by default in order to support existing boards. BUG=chrome-os-partner:42933 TEST=Verify that Glados v1 board continues to boot AP. Verify compilation on GLADOS_BOARD_V2. BRANCH=None Change-Id: I68634f95f94d3d37f18d676c01219f92b6ddfc45 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/287291 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* mec1322: hibernate: Fix wake-on-AC for USB-CShawn Nematbakhsh2015-07-201-7/+55
| | | | | | | | | | | | | | | | | Fix hibernate so that plugging a USB-C charger properly wakes the system. In addition, change the default hibernate behavior to restart after wake. BUG=chrome-os-partner:42104 TEST=Run 'hibernate' on Glados. Verify that wakes occur when power button is pressed, lid switch is toggled, or when a charger is attached to either USB-C port. BRANCH=None Change-Id: I54b8d58e20c35f25883238df24e7f23bb743abaa Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/286660 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* mec1322: Allow multiple hibernate wake sourcesShawn Nematbakhsh2015-07-161-23/+33
| | | | | | | | | | | | | | | | | Allow multiple GPIOs to wake the EC from hibernate by requiring boards to define hibernate_wake_pins and hibernate_wake_pins_used. In addition, clean up the GPIO-skipping hibernate code, and skip setting PCH_RTCRST as an input due to a bug on certain boards. BUG=chrome-os-partner:42104 TEST=Manual on Glados. Run 'hibernate' from EC console, verify that EC wakes with power button press or with "dut-control lid_open:no". BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I13a6e062393cab8ed7129eda253585951f771109 Reviewed-on: https://chromium-review.googlesource.com/285924 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* mec1322: Fix reset cause detectionDivya Jyothi2015-07-131-35/+3
| | | | | | | | | | | | | | | | | | | | | | | Mec1322 cannot distinguish between Power-on and reset condition. MEC1322_EC_WDT_CNT was used to determine the power-on condition. VBAT_POR cannot not be used to distinguish no battery condition. All of the feautures that need support need to determine VCC1_REST which is used for reset considion. lfw and main code use the same condition. When VCC1_RESET is asserted we need to set the image type to RO image for sysjump to work correctly. This in turn will affect Recovery mode,software sync and Flashrom. All of these conditions were tested with this patch. BUG=chrome-os-partner:40526 TEST=Recovery mode,Software Sync,Flashrom BRANCH=None Change-Id: I65f2aa9f56863597116b875ea436d4413887b92b Signed-off-by: Divya Jyothi <divya.jyothi@intel.com> Reviewed-on: https://chromium-review.googlesource.com/283605 Reviewed-by: Shawn N <shawnn@chromium.org>
* mec1322: fix flash_physical_read()Andrey Petrov2015-07-011-0/+3
| | | | | | | | | | | | | | | | | | | | | | | flashrom on target issues a salvo of flash read commands with small buffer size (128 bytes). Since there is no yield this starves other tasks/events including hooks and as result watchdog is never reloaded. This change makes read function yield to other tasks. In addition, spi_enable()/disable chaining leads to situations where a SPI can be disabled in the middle of transcation. This is addressed by keeping SPI permanently enabled in LFW entry function, as well as in RW/RO early init functions. BRANCH=None BUG=chrome-os-partner:38103 TEST=manual on Cyan, run flashrom -p ec -w xx in cycles, swaping xx so that flashrom does flash. Make sure there is no watchdog triggered Change-Id: Id5c50239a1d5c64054d7c660dd03b2be4678221c Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://chromium-review.googlesource.com/282111 Reviewed-by: Bernie Thompson <bhthompson@chromium.org> Commit-Queue: Bernie Thompson <bhthompson@chromium.org> Tested-by: Bernie Thompson <bhthompson@chromium.org>
* mec1322: Correctly get reset causeDivya Jyothi2015-06-241-2/+22
| | | | | | | | | | | | | | | | | | Since the reset cause was not recorded correctly recovery mode(Esc+Refresh+Power) was not working. With this change power-on reset state and VCC1_RST# only state are distinguinshed. BUG=chrome-os-partner:41479 BRANCH=none TEST=Esc+Refresh+Power boots to recovery screen Refresh+Power reboots the system Change-Id: I63eff488c970302e7afe8a677a57ad27d4d9918e Signed-off-by: Divya Jyothi <divya.jyothi@intel.com> Signed-off-by: Freddy Paul <freddy.paul@intel.com> Reviewed-on: https://chromium-review.googlesource.com/280782 Reviewed-by: Shawn N <shawnn@chromium.org>
* mec1322: Added support for sysjump.stabilize-7173.BDivya Jyothi2015-06-141-5/+37
| | | | | | | | | | | | | | | | | | | | | | | | changes added to support flashrom are: sysjump support to be able to copy the RO/RW image and jump to it without causing AP to reboot while its alreday ON. LPC init should be reinitialized on sysjump corrected gpio_set_flags_by_mask to make sure we update the register only for GPIO_LOW condition and not all else conditions. BUG=chrome-os-partner:38103 TEST=commands : flashrom -p ec -w ec.bin flashrom -p ec -r ec.bin BRANCH=none Change-Id: I23892f0378d756052030e73034c3acdd41477e34 Signed-off-by: Divya Jyothi <divya.jyothi@intel.com> Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://chromium-review.googlesource.com/272000 Reviewed-by: Shawn N <shawnn@chromium.org>
* cleanup: Rename image geometry CONFIGsShawn Nematbakhsh2015-05-121-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Rename image geometry configs with a uniform naming scheme to make their purposes more clear. CONFIG_RO_MEM_OFF (was CONFIG_FW_RO_OFF) - RO image offset in program memory CONFIG_RO_STORAGE_OFF (was CONFIG_RO_SPI_OFF) - RO image offset on storage CONFIG_RO_SIZE (was CONFIG_FW_RO_SIZE) - Size of RO image CONFIG_RW_MEM_OFF (was CONFIG_FW_RW_OFF) - RW image offset in program memory CONFIG_RW_STORAGE_OFF (was CONFIG_RW_SPI_OFF) - RW image offset on storage CONFIG_RW_SIZE (was CONFIG_FW_RW_SIZE) - Size of RW image CONFIG_WP_OFF (was CONFIG_FW_WP_RO_OFF) - Offset of WP region on storage CONFIG_WP_SIZE (was CONFIG_FW_WP_RO_SIZE) - Size of WP region on storage BUG=chrome-os-partner:39741,chrome-os-partner:23796 TEST=Set date / version strings to constants then `make buildall -j`. Verify that each ec.bin image is identical pre- and post-change. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I6ea0a4e456dae71c266fa917a309b9f6fa4b50cd Reviewed-on: https://chromium-review.googlesource.com/270189 Reviewed-by: Anton Staaf <robotboy@chromium.org>
* mec1322: Add flash physical interface functionsShawn Nematbakhsh2015-03-121-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | Add physical flash interface for read / write / protection of external SPI on mec1322. BUG=chrome-os-partner:36167 TEST=Manual on glower: flashread 0xf000 0x200 --> dumps 0xff flashwrite 0xf000 0x200 flashread 0xf000 0x200 --> dumps write pattern flasherase 0xf000 0x1000 flashread 0xf000 0x200 --> dumps 0xff spi_flash_prot 0 0x10000 flashinfo --> shows first 64KB protected spi_flashwrite 0xf000 0x200 --> access denied spi_flashwrite 0x1f000 0x200 --> OK flashread 0x1f000 0x200 --> dumps write pattern BRANCH=None Change-Id: I2cb20a49934999fc0dd9b3425eb99708711637c5 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/257132 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Fix errors discovered by new compiler.Bill Richardson2014-11-211-1/+1
| | | | | | | | | | | | | | The latest gcc picked up a couple out-of-bounds issues, so "make buildall" was failing. This fixes them. BUG=none BRANCH=ToT TEST=make buildall -j Signed-off-by: Bill Richardson <wfrichar@chromium.org> Change-Id: Idcd6a3358ecbb0e0d2a610e1cd28c2f138ce520b Reviewed-on: https://chromium-review.googlesource.com/231156 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* mec1322: Keep CPU at high clock frequency to speed up hibernateVic Yang2014-07-031-6/+6
| | | | | | | | | | | | | | | | | | | | | When going into and waking from hibernation, we should keep CPU at high clock frequency so that we can save and restore chip state faster. This is especially true for the wake-up case as it affects AP boot time. This CL keeps the CPU at 12MHz for saving state and clocks it up to 48MHz for restoring. With this, the wake-up time (time from GPIO interrupt to completely restoring chip state) reduces from 11ms to 0.85ms. BUG=None TEST=Measure wake-up time with logic analyzer BRANCH=None Change-Id: Ib470a3d38959247b082cc7a5fd2d889cdc2a15ca Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/206308 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* mec1322: restore system states after hibernateVic Yang2014-07-021-18/+81
| | | | | | | | | | | | | | Save system states before hibernating and restore them after waking up. This saves us from needing to reboot every time we wake up. BUG=None TEST=wake from hibernate. Check UART, ADC, and timer are working. BRANCH=None Change-Id: I044fb8a796e1560c0f748d766f4aeee4dda23342 Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/205954 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* force the compiler to use a valid register allocation for irq handlersVincent Palatin2014-03-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When we are calling the re-scheduling routine at the end of an irq handling routine, we need to ensure that the high registers are not currently saved on the system stack. On Cortex-M3/M4, the compiler is normally doing tail-call optimization there and behaving properly, but this fixes the fact that insanely large interrupt handling routines where sometimes not compile and not running properly (aka issue 24515). This also prepares for one more core-specific DECLARE_IRQ routine on Cortex-M0. Note: now on, the IRQ handling routines should no longer be "static". Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=chrome-os-partner:24515 TEST=make -j buildall revert the workaround for 24515, see the issue happening only without this CL. Change-Id: Ic419369231925568df05815fd079ed191a5446db Reviewed-on: https://chromium-review.googlesource.com/189153 Reviewed-by: Vic Yang <victoryang@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
* mec1322: hibernation supportstabilize-5339.BVic (Chun-Ju) Yang2014-01-281-4/+152
| | | | | | | | | | | | | | | This adds hibernation support. The chip can be waken by either GPIO or a timer. The maximum delay allowed is ~2 hours. BUG=chrome-os-partner:24107 TEST=hibernate and wake by GPIO TEST=hibernate and wake by timer BRANCH=None Change-Id: I1e064638a5008894a002a06a738bf6104f18636d Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/181202 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* mec1322: Refine reset cause detectionVic (Chun-Ju) Yang2014-01-111-4/+23
| | | | | | | | | | | | | | | | | | | | | | | | The VBAT POR indication is unreliable for detecting a power-on reset, and thus we often see "unknown" reset cause when we should see "power-on". A better indication is to check for VCC1 POR, which manifests by clearing watchdog count. The catch is that we still cannot tell power-on reset from reset-pin reset. Also, to distinguish soft/hard reset from actual watchdog reset, we need to explicitly save soft/hard reset flag before triggering watchdog reset. BUG=chrome-os-partner:24107 TEST=Power cycle EVB and see 'power-on' reset cause. TEST='reboot' and see 'soft' reset cause. TEST='reboot hard' and see 'hard' reset cause. TEST='waitms 2000' and see 'watchdog' reset cause. BRANCH=None Change-Id: I0075f5bf5cdb032d206c4a53c586b75b69093235 Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182120 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* mec1322: keyboard scan supportVic (Chun-Ju) Yang2013-12-131-0/+3
| | | | | | | | | | | | | | | | | | | | | This adds keyboard scan module driver. Keyboard scan task is not enabled yet as the LPC layer is not finished and thus i8042 protocol cannot be enabled. Since KSO00-KSO03 are used as JTAG, we use KSO04-KSO16 so as to preserve JTAG functionality. Unfortunately we don't have enough KSO pins, so trace debug port must be disabled, as done in this CL. BUG=chrome-os-partner:24107 TEST=Set 'ksstate on'. Short KSI pins and KSO pins, and see corresponding key shown as pressed. TEST=Check keypress is detected when console shows 'KB wait'. BRANCH=None Change-Id: I366a27453ef95030d251e525313eb4627eb4340f Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/179319 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* mec1322: Check/save reset causeVic (Chun-Ju) Yang2013-12-021-0/+38
| | | | | | | | | | | | | | | | So far we can only reliably sense a watchdog reset, but this saving/checking reset cause will at least make 'ap-off' flag work. BUG=chrome-os-partner:24107 TEST='waitms 2000' and see reset cause = 'watchdog' TEST='reboot ap-off' and see reset cause includes 'ap-off' TEST='reboot preserve' and see previous reset cause is preserved. BRANCH=None Change-Id: Id47a72d615489c9d9cd0b8761cfa699f08c724df Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/178277 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* mec1322: Add support for VBAT backed RAMVic (Chun-Ju) Yang2013-12-021-0/+16
| | | | | | | | | | | | | | This will be used for saving data across reboots. BUG=chrome-os-partner:24107 TEST=Enable scratchpad command and check value is preserved across watchdog reboot. BRANCH=None Change-Id: Ifd68541a3f842c466b6ff49bcc654c92df48aac6 Signed-off-by: Vic (Chun-Ju) Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/178276 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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