summaryrefslogtreecommitdiff
path: root/chip/mt8192_scp
Commit message (Expand)AuthorAgeFilesLines
* chip/mt8192_scp: add memory barrierTzung-Bi Shih2021-01-142-0/+2
* chip/mt8192_scp: add memory barrier after writing to cacheTzung-Bi Shih2020-12-161-2/+12
* chip/mt8192_scp: make all cache operations inlineTzung-Bi Shih2020-12-162-110/+97
* chip/mt8192_scp: set CONFIG_PROGRAM_MEMORY_BASE_LOADTzung-Bi Shih2020-12-161-0/+1
* chip/mt8192_scp: expose PMU-related functionsTzung-Bi Shih2020-12-101-0/+6
* chip/mt8192_scp: invalidate all I/D cache when resetting PMUTzung-Bi Shih2020-12-101-0/+3
* chip/mt8192_scp: support PMU counterTzung-Bi Shih2020-11-272-0/+182
* chip/mt8192_scp: update memory mapTzung-Bi Shih2020-11-171-5/+5
* chip/mt8192_scp: remove confusing commentsTzung-Bi Shih2020-11-171-2/+1
* chip/mt8192_scp: support RAM cacheTzung-Bi Shih2020-11-175-0/+212
* tree: Use new atomic_* implementationDawid Niedzwiecki2020-10-271-2/+2
* core/riscv-rv32i: rename atomic inc and decDawid Niedzwiecki2020-10-071-2/+2
* tree: rename atomic_* functions to deprecated_atomic_*Jack Rosenthal2020-09-291-2/+2
* chip/mt8192_scp: support ULPOSCTzung-Bi Shih2020-09-294-0/+478
* it83xx: read_clear_int_mask() read and clear interrupt bit.Dino Li2020-09-241-4/+2
* chip/mt8192_scp: remove chip_disable_irqTzung-Bi Shih2020-09-031-12/+8
* chip/mt8192_scp: do not handle pending IPI interruptsTzung-Bi Shih2020-08-261-7/+1
* chip/mt8192_scp: do not switch INTC_IRQ_EN in runtimeTzung-Bi Shih2020-08-261-4/+6
* chip/mt8192_scp: add address location of MIEMASK_G0Tzung-Bi Shih2020-08-261-0/+1
* chip/mt8192_scp: enlarge the stack size of idle taskTzung-Bi Shih2020-08-121-1/+1
* chip/mt8192_scp: add missing guard for TASK_HOSTCMDTzung-Bi Shih2020-08-121-0/+2
* ec: change usage of dummySam Hurst2020-08-052-3/+3
* chip/mt8192_scp: don't unset the THRI flag unless we are in the UART ISRTzung-Bi Shih2020-08-021-2/+15
* chip/mt8192_scp: add memory mapsTzung-Bi Shih2020-07-214-28/+145
* chip/mt8192_scp: support hostcmd over IPITzung-Bi Shih2020-07-164-0/+147
* chip/mt8192_scp: support IPI handlerTzung-Bi Shih2020-07-146-2/+155
* EC: Add additional stack sizesSam Hurst2020-07-071-0/+2
* chip/mt8192_scp: support ipi_send()Tzung-Bi Shih2020-07-034-0/+193
* chip/mt8192_scp: use 0 for dummy priority numberTzung-Bi Shih2020-07-022-2/+2
* chip/mt8192_scp: add static for non-exposed functionsTzung-Bi Shih2020-07-021-2/+2
* chip/mt8192_scp: read MRV micause for interrupt sourceTzung-Bi Shih2020-06-101-1/+1
* chip/mt8192_scp: use in_soft_interrupt_context()Tzung-Bi Shih2020-06-101-1/+1
* chip/mt8192_scp: support WDTTzung-Bi Shih2020-06-104-1/+44
* chip/mt8192_scp: add system tick timersTzung-Bi Shih2020-06-103-9/+209
* chip/mt8192_scp: support UARTTzung-Bi Shih2020-06-044-8/+262
* chip/mt8192_scp: support INTCTzung-Bi Shih2020-06-043-9/+435
* chip/mt8192_scp: add basic system settingsTzung-Bi Shih2020-06-032-0/+40
* chip/mt8192_scp: add dummy chip implementationsTzung-Bi Shih2020-06-039-0/+293
View Lorry Controller Status