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* Revert "kukui: scp: calibrate ULPOSC1&2"Yilun Lin2019-04-261-181/+66
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit e08a71fd05bfc9e32dd64b7e15840e7232d72788. Reason for revert: SCP will hang with this CL. Original change's description: > kukui: scp: calibrate ULPOSC1&2 > > ULPOSC generates clock for SCP core and peripherals. The calibration > process adjust 2 values, div and cali. Both values are positive > correlated to OSC frequency. The frequency function is: > f(div, cali) = k1 * (div + k2) / R(cali) * C > Where: > R(cali) = k3 / (1 + k4 * (cali - k4)) > > The actual frequency is not linear to cali parameter. This change > selects the div that generates closest frequency when cali == 32. And > then adjust cali to get better output. > > BRANCH=none > BUG=b:120176040,b:120169529 > TEST=manual > check SCP console command: > > ulposc > ULPOSC1 frequency: 248 MHz > ULPOSC2 frequency: 330 MHz > > Change-Id: Ifac9d481e654064ee60d84819added5e164ed7c2 > Signed-off-by: Rong Chang <rongchang@chromium.org> > Reviewed-on: https://chromium-review.googlesource.com/1520571 > Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Bug: b:120176040, b:120169529, b:131273034 Change-Id: Ifaeb9a7835a35556587fac4c039b9fde6d66504d Reviewed-on: https://chromium-review.googlesource.com/1583481 Commit-Ready: Yilun Lin <yllin@chromium.org> Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Yilun Lin <yllin@chromium.org>
* kukui: scp: calibrate ULPOSC1&2Rong Chang2019-04-241-66/+181
| | | | | | | | | | | | | | | | | | | | | | | | | | ULPOSC generates clock for SCP core and peripherals. The calibration process adjust 2 values, div and cali. Both values are positive correlated to OSC frequency. The frequency function is: f(div, cali) = k1 * (div + k2) / R(cali) * C Where: R(cali) = k3 / (1 + k4 * (cali - k4)) The actual frequency is not linear to cali parameter. This change selects the div that generates closest frequency when cali == 32. And then adjust cali to get better output. BRANCH=none BUG=b:120176040,b:120169529 TEST=manual check SCP console command: > ulposc ULPOSC1 frequency: 248 MHz ULPOSC2 frequency: 330 MHz Change-Id: Ifac9d481e654064ee60d84819added5e164ed7c2 Signed-off-by: Rong Chang <rongchang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1520571 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* kukui: scp: move CPU clock selection to clock moduleRong Chang2019-04-231-0/+6
| | | | | | | | | | | | | | | | CPU clock management should be in clock module. BUG=b:120169529 BRANCH=none TEST=manual build and load on kukui, check SCP console command: > rw 0x405C4000 read 0x405c4000 = 0x00000803 Change-Id: Ic13e9a51cf682af33799b713849fd3a445e6cfdb Signed-off-by: Rong Chang <rongchang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1538097 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* kukui: scp: fix udelay hangs the system in clock enable.Pi-Hsun Shih2019-04-041-2/+15
| | | | | | | | | | | | | | | | | It seems that udelay doesn't work before the clock is properly configured and enabled, causing the SCP image not able to boot. Remove the udelay in scp_clock_high_enable. BUG=b:128877063 TEST=manually, make sure SCP firmware works on boot. BRANCH=none Change-Id: Idc505a33a7e88d136a5b50f2e5bd52bd5213393b Signed-off-by: Pi-Hsun Shih <pihsun@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1530410 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Rong Chang <rongchang@chromium.org>
* kukui: scp: fix ULPOSC index using 0 base numberingRong Chang2019-03-161-15/+14
| | | | | | | | | | | | | | | | | | Where ULPOSC1 should be 0 and ULPOSC2 is 1. BRANCH=none BUG=b:125616659 TEST=manual Check scp console comamnd: > ulposc still output correct ULPOSC1 and ULPOSC2 clock in MHz. Change-Id: I3730ebb83bbe5e0021360116dbd37bcccdbc77aa Signed-off-by: Rong Chang <rongchang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1520570 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* kukui: scp: fix ULPOSC configuration and add OSC clock measurementRong Chang2019-03-161-48/+91
| | | | | | | | | | | | | | | | | | | | The initial clock change turned on wrong clock gate while enabling ULPOSC2. This change fixed clock gate and ULPOSC configuration. A clock measuring console command is added to check clock speed. BRANCH=none BUG=b:120176040,b:125616659,b:124472114 TEST=manual Build and load on kukui. Check console command out: > ulposc ULPOSC1 frequency: 210 MHz ULPOSC2 frequency: 271 MHz Change-Id: I19e637d97bc125a1bbfd102a5fc5ec24573d9e09 Signed-off-by: Rong Chang <rongchang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1485040 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* kukui: scp: fix wrong logic on checking ULPOSC numberRong Chang2019-03-161-1/+1
| | | | | | | | | | | | | | | | | The logic should be either OSC1 or OSC2. BRANCH=none BUG=b:125616659 TEST=manual rw 0xA000C708 bit 23 should be 1 Change-Id: I15f75f37b09bde04e7d23aebe549f3ec49767783 Signed-off-by: Rong Chang <rongchang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1488636 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* kukui: scp: move clock and oscillator configuration code to clock.cRong Chang2019-03-161-0/+103
| | | | | | | | | | | | | | | | To implement ULPOSC calibration, clock and oscillator APIs are moved from system to its own module. BRANCH=none BUG=b:120176040 TEST=manual make BOARD=kukui_scp -j Change-Id: I143b331f5d36cd0d0964920a9b7e7fe00afb6e3b Signed-off-by: Rong Chang <rongchang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1488635 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* scp: Add mt_scp chipRong Chang2018-12-201-0/+78
SCP is a Cortex-M4 based sensor hub in Mediatek SoC. This change adds the chip folder and system level drivers. BRANCH=none BUG=b:114326670 TEST=manual make BOARD=kukui_scp -j copy ec.bin to /lib/firmware/scp.img echo 'stop' > /sys/class/remoteproc/remoteproc0/state echo 'start' > /sys/class/remoteproc/remoteproc0/state check EC uart console Change-Id: I6629149f352184108fa520e80b59fd2ce94c76f7 Signed-off-by: Rong Chang <rongchang@chromium.org> Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/1208770 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
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