| Commit message (Collapse) | Author | Age | Files | Lines |
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In the interest of making long-term branch maintenance incur as little
technical debt on us as possible, we should not maintain any files on
the branch we are not actually using.
This has the added effect of making it extremely clear when merging CLs
from the main branch when changes have the possibility to affect us.
The follow-on CL adds a convenience script to actually pull updates from
the main branch and generate a CL for the update.
BUG=b:204206272
BRANCH=ish
TEST=make BOARD=arcada_ish && make BOARD=drallion_ish
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I17e4694c38219b5a0823e0a3e55a28d1348f4b18
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3262038
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Tom Hughes <tomhughes@chromium.org>
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Use 32k clock instead of ULPOSC can significantly reduce the power
consumption of SCP under S3 stage, and still able to kick SCP WDT.
BRANCH=none
BUG=b:197937562
TEST=low scp power in S3 stage
Change-Id: If2f68a5b11e93c7e6badf2e4893f649700b5af2e
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3131409
Reviewed-by: Tzung-Bi Shih <tzungbi@chromium.org>
Commit-Queue: Tzung-Bi Shih <tzungbi@chromium.org>
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Fmeter is used to measure the clock speed on SoC.
SCP uses the fmeter with different config compared to kernel side clock
driver.
Restore the fmeter value to prevent wrong fmeter result for clock driver.
BUG=b:184793035
TEST=check fmeter result by following commands
echo 0 > /proc/sys/kernel/printk
clkdbg() { echo $@ > /proc/clkdbg; cat /proc/clkdbg; }
clkdbg set_parent vdec_sel mainpll_d4
clkdbg set_parent venc_sel univpll_d4
clkdbg fmeter
WAS:
64: hf_fvenc_ck : 312000
65: hf_fvdec_ck : 273000
IS:
64: hf_fvenc_ck : 624000
65: hf_fvdec_ck : 546000
Change-Id: If4d93b9b4e05258d0ad5f96953a99fd74acb6070
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3063107
Reviewed-by: Tzung-Bi Shih <tzungbi@chromium.org>
Commit-Queue: Tzung-Bi Shih <tzungbi@chromium.org>
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BRANCH=none
BUG=b:185977882
TEST=make BOARD=asurada_scp -j &&
make BOARD=cherry_scp -j
Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org>
Change-Id: Id5eaa5ddc0e21c9b33a1a4197393de6c6ef331e6
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3080541
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BRANCH=none
BUG=b:189300514
TEST=video_decode_accelerator_tests test-25fps.h264
Change-Id: Ia6e777fe7a349586c676b6991643676019598d7a
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3038014
Reviewed-by: Tzung-Bi Shih <tzungbi@chromium.org>
Commit-Queue: Tzung-Bi Shih <tzungbi@chromium.org>
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Update IRQ definition for mt8195 and move IRQ definitions to
chip-specific folder.
BRANCH=none
BUG=b:189300514
TEST=make BOARD=asurada_scp &&
make BOARD=cherry_scp
Change-Id: I3bb4d97e374328fbe86d537b14cce11322365c10
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2940337
Tested-by: Tzung-Bi Shih <tzungbi@chromium.org>
Reviewed-by: Tzung-Bi Shih <tzungbi@chromium.org>
Commit-Queue: Tzung-Bi Shih <tzungbi@chromium.org>
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Change UART clock to ULPOSC to keep SCP console alive when system
suspend.
BRANCH=none
BUG=b:189300514
TEST=make BOARD=cherry_scp
Change-Id: I144354fe946808c7ec68da4ea33e4ad11a7bf11f
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3003345
Tested-by: Tzung-Bi Shih <tzungbi@chromium.org>
Reviewed-by: Tzung-Bi Shih <tzungbi@chromium.org>
Commit-Queue: Tzung-Bi Shih <tzungbi@chromium.org>
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Supports mt8195 clock and move chip-specific clock registers from common
to chip-specific.
BRANCH=none
BUG=b:189300514
TEST=make BOARD=asurada_scp &&
make BOARD=cherry_scp
Change-Id: I8ef058f6314652050dead46e7f48d3420bbdd1d1
Signed-off-by: Roger Lu <roger.lu@mediatek.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2939167
Tested-by: tinghan shen <tinghan.shen@mediatek.com>
Tested-by: Tzung-Bi Shih <tzungbi@chromium.org>
Reviewed-by: Tzung-Bi Shih <tzungbi@chromium.org>
Commit-Queue: Tzung-Bi Shih <tzungbi@chromium.org>
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Supports MT8195 UART.
BRANCH=none
BUG=b:189300514
TEST=make BOARD=cherry_scp
Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org>
Change-Id: I948e0208f664de72de027357d4ba7336715e92fa
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2993789
Reviewed-by: Ting Shen <phoenixshen@chromium.org>
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The pinmux setting is chip-specific. Turns the common code into
chip-specific.
BRANCH=none
BUG=b:191835814
BUG=b:189300514
TEST=make BOARD=asurada_scp &&
make BOARD=cherry_scp
Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org>
Change-Id: I22b8171f42025f294392b0bf1a25a4153eb648f7
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2993788
Reviewed-by: Ting Shen <phoenixshen@chromium.org>
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