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* config: rename CONFIG_FLASH to CONFIG_FLASH_CROSJeremy Bettis2021-04-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 4ac1d81e1430dbfbfba1376a23ab19dfa845d7ef. The config name collides with the same config name in zephyr. Also, renames zephyr Kconfig CONFIG_PLATFORM_EC_FLASH to CONFIG_PLATFORM_EC_FLASH_CROS as the corresponding change at Kconfig side. BUG=chromium:1202406,b:180980668 TEST=make -j16 runhosttests buildall && zmake testall && \ /mnt/host/source/src/platform/ec/zephyr/firmware_builder.py --metrics \ /tmp/tmplt8ty8ci test ; echo $? BRANCH=none Signed-off-by: Jeremy Bettis <jbettis@google.com> Change-Id: I5b5e58b30d936b5232e049827f458d9a2ed06340 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2855320 Commit-Queue: Jeremy Bettis <jbettis@chromium.org> Commit-Queue: Keith Short <keithshort@chromium.org> Tested-by: Jeremy Bettis <jbettis@chromium.org> Auto-Submit: Jeremy Bettis <jbettis@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org>
* Revert "config: rename CONFIG_FLASH to CONFIG_FLASH_CROS"stabilize-13935.B-mainJack Rosenthal2021-04-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 4e074a16c5703f0cdd7b7d780a8ae1bea53a445a. Reason for revert: responsible for CQ failures (crbug.com/1202406) BUG=chromium:1202406 BRANCH=none TEST=CQ Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Original change's description: > config: rename CONFIG_FLASH to CONFIG_FLASH_CROS > > The config name collides with the same config name in zephyr. > > Also, renames zephyr Kconfig CONFIG_PLATFORM_EC_FLASH to > CONFIG_PLATFORM_EC_FLASH_CROS as the corresponding change at Kconfig > side. > > BUG=b:180980668 > TEST=make buildall > BRANCH=none > > Change-Id: Ibac008ddff8c041aae04dca0bbf973823abe7640 > Signed-off-by: Eric Yilun Lin <yllin@chromium.org> > Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2816622 > Tested-by: Eric Yilun Lin <yllin@google.com> > Reviewed-by: Keith Short <keithshort@chromium.org> > Commit-Queue: Keith Short <keithshort@chromium.org> Bug: b:180980668 Change-Id: Idc5e799d3b0ea8cc76dbbb49a91b3758ce6e9719 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2847274 Auto-Submit: Jack Rosenthal <jrosenth@chromium.org> Bot-Commit: Rubber Stamper <rubber-stamper@appspot.gserviceaccount.com> Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
* config: rename CONFIG_FLASH to CONFIG_FLASH_CROSEric Yilun Lin2021-04-231-1/+1
| | | | | | | | | | | | | | | | | | | The config name collides with the same config name in zephyr. Also, renames zephyr Kconfig CONFIG_PLATFORM_EC_FLASH to CONFIG_PLATFORM_EC_FLASH_CROS as the corresponding change at Kconfig side. BUG=b:180980668 TEST=make buildall BRANCH=none Change-Id: Ibac008ddff8c041aae04dca0bbf973823abe7640 Signed-off-by: Eric Yilun Lin <yllin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2816622 Tested-by: Eric Yilun Lin <yllin@google.com> Reviewed-by: Keith Short <keithshort@chromium.org> Commit-Queue: Keith Short <keithshort@chromium.org>
* version: Rename version.h to cros_version.hYuval Peress2021-01-071-1/+1
| | | | | | | | | | | | | | | This change simply moves the include/version.h file over to avoid a naming collision with zephyr's version.h. BRANCH=none BUG=b:167392037 TEST=make buildall -j Signed-off-by: Yuval Peress <peress@chromium.org> Change-Id: Ib41b3c21817d5f81e713d3b550bc46a0d1c55cf8 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2612772 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
* ec: change usage of dummySam Hurst2020-08-053-8/+8
| | | | | | | | | | | | | | | | | | Google is working to change its source code to use more inclusive language. To that end, replace the term "dummy" with inclusive alternatives. BUG=b:162781382 BRANCH=None TEST=make -j buildall `grep -ir dummy *` The only results are in "private/nordic_keyboard/sdk8.0.0" which is not our code. Signed-off-by: Sam Hurst <shurst@google.com> Change-Id: I6a42183d998e4db4bb61625f962867fda10722e2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2335737 Reviewed-by: Tom Hughes <tomhughes@chromium.org>
* ec: Enlarged Task Stack size on platformsBrian J. Nemec2020-04-021-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The task stack size of is small enough that the process was triggering stack overflows when responding to commands. These actions had a small chance of causing EC hardfaults. This was apparent with the gpioget command which had the attributes of performing many calls to a printf function which also has many parameters. Since the structure of a printf with 10 or more parameters is common when constructing console responses, this enlarges the stack for that task. This is more important since the probability of it creating a hardfault is low. To reduce the chance of this issue on other platforms, the platforms with 488 byte tasks were also enlarged to 512 bytes. BUG=chromium:1056780 BRANCH=none TEST=Connected servod to servo_v4 looped the command 'dut-control servo_v4_uart_cmd:gpioget' 1000 times TEST=make buildall -j Verified free ram space remains over 60 bytes on impacted platforms Change-Id: I6b50b204c83a10068153f3e01bc134446047f235 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2133130 Tested-by: Brian Nemec <bnemec@chromium.org> Commit-Queue: Brian Nemec <bnemec@chromium.org> Reviewed-by: Ruben Rodriguez Buchillon <coconutruben@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* common/system: Unify ec_current_image and system_image_copy_tTom Hughes2020-02-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | "enum ec_current_image" is exposed in ec_commands.h (and used by non-EC code, such as biod). We also have an "enum system_image_copy_t" that is the exact same thing (though has a few more definitions). A followup CL (I714b6bd8c0d7192386404c25a831e38438fa5238) adds the "sysinfo" host command, so we want to be able to expose all the potential image variants. Rather than maintain two enums that can potentially get out of sync, unify the code to use a single enum. We choose to keep the "enum ec_current_image", since external code depends on it. To verify that this change results in no changes to the generated binaries: ./util/compare_build.sh --board all BRANCH=none BUG=b:146447208 TEST=./util/compare_build.sh --board=all Change-Id: I13776bc3fd6e6ad635980476a35571c52b1767ac Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2036599 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Namyoon Woo <namyoon@chromium.org>
* mt_scp/clock: Use ULPOSC1 when AP suspendEric Yilun Lin2020-01-074-2/+73
| | | | | | | | | | | | | | | | | | | This CL does: 1. Move power_chipset_handle_host_sleep_event from board to chip folder 2. Uses ULPOSC1(240/2MHz) when AP suspend. When AP in suspend, Vcore decreases from 0.8V to 0.6V and thus it shouldn't use ULPOSC2 (330Mhz) which needs at least 0.7V to clock. ULPOSC1 only needs 0.6V to clock. TEST=run suspend/resume test for 2500 runs and ensure the SCP won't trigger watchdog. BUG=b:144820026 BRANCH=kukui Change-Id: I7b317a70b6ed93ff83e9543b2fc6cdfede112fd3 Signed-off-by: Eric Yilun Lin <yllin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1985728 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Erin Lo <erin.lo@mediatek.corp-partner.google.com>
* mt_scp/gpio: set GPIO_ALT_FUNC_NONE to GPIO_ALT_FUNC_DEFAULTYilun Lin2019-11-021-1/+3
| | | | | | | | | | | | | | | | The common EC code expects that if the func parameter passed to gpio_set_alternate_function() is -1 (GPIO_ALT_FUNC_NONE), that the pin will be reassigned to a GPIO function. TEST=make buildall BUG=b:143710991 BRANCH=kukui Change-Id: I6ba3d3d323e4fb99617ce4baaec662ceab094ad4 Signed-off-by: Yilun Lin <yllin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1893026 Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* Cleanup: Correct GPIO alternate function parameterVijay Hiremath2019-11-011-2/+3
| | | | | | | | | | | | | | | Added code to correct the GPIO alternate function parameter at Chipset level. Optionally board level functions can cleanup the code in additional change lists. BUG=b:139427854 BRANCH=none TEST=make buildall -j Change-Id: I1171ca36a703291070fc89f972f84414adcf04fc Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1880974 Reviewed-by: Keith Short <keithshort@chromium.org>
* printf: Convert %l to %llEvan Green2019-10-051-2/+2
| | | | | | | | | | | | | | | | | | | | | In order to make our printf more standard, utilize %ll for long long arguments, rather than %l. This does cost a little bit in flash space for that extra l in a couple of places, but enables us to turn on compile-time printf format checking. For this commit only, the semantics are such that both %l and %ll take 64-bit arguments. In the next commit, %l goes to its correct behavior of taking a sizeof(long) argument. BUG=chromium:984041 TEST=make -j buildall BRANCH=none Cq-Depend:chrome-internal:1863686,chrome-internal:1860161,chrome-internal:1914029 Change-Id: I18081b55a8dbf5ef8ec15fc499ca75e59d31da58 Signed-off-by: Evan Green <evgreen@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1819652 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* host_command: Change host command return value to enum ec_statusTom Hughes2019-10-021-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the host command handler callback function returns an int, it's easy to accidentally mix up the enum ec_error_list and enum ec_status types. The host commands always expect an enum ec_status type, so we change the return value to be of that explicit type. Compilation will then fail if you accidentally try to return an enum ec_error_list value. Ran the following commands and then manually fixed up a few remaining instances that were not caught: git grep --name-only 'static int .*(struct host_cmd_handler_args \*args)' |\ xargs sed -i 's#static int \(.*\)(struct host_cmd_handler_args \*args)#\ static enum ec_status \1(struct host_cmd_handler_args \*args)##' git grep --name-only 'int .*(struct host_cmd_handler_args \*args)' |\ xargs sed -i 's#int \(.*\)(struct host_cmd_handler_args \*args)#\ enum ec_status \1(struct host_cmd_handler_args \*args)##' BRANCH=none BUG=chromium:1004831 TEST=make buildall -j Cq-Depend: chrome-internal:1872675 Change-Id: Id93df9387ac53d016a1594dba86c6642babbfd1e Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1816865 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* chip/mt_scp: support software gainTzung-Bi Shih2019-09-191-2/+11
| | | | | | | | | | | | | | | | | | | Multiply the audio data by a gain value. Note that it get muted when gain is 0. BRANCH=none BUG=b:122027734, b:123268236 TEST=1. define CONFIG_AUDIO_CODEC in board.h 2. define CONFIG_AUDIO_CODEC_DMIC in board.h 3. define CONFIG_AUDIO_CODEC_DMIC_SOFTWARE_GAIN in board.h 4. define CONFIG_AUDIO_CODEC_DMIC_MAX_SOFTWARE_GAIN in board.h 5. define CONFIG_AUDIO_CODEC_WOV in board.h 6. make BOARD=kukui_scp -j Change-Id: I8c308ffb6d7c8f5bd378524bdffc980d7b9948fa Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1683028 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* chip/mt_scp: support audio codec WoVTzung-Bi Shih2019-09-193-0/+141
| | | | | | | | | | | | | | | | BRANCH=none BUG=b:122027734, b:123268236 TEST=1. define CONFIG_AUDIO_CODEC in board.h 2. define CONFIG_AUDIO_CODEC_DMIC in board.h 3. define CONFIG_AUDIO_CODEC_DMIC_SOFTWARE_GAIN in board.h 4. define CONFIG_AUDIO_CODEC_DMIC_MAX_SOFTWARE_GAIN in board.h 5. define CONFIG_AUDIO_CODEC_WOV in board.h 6. make BOARD=kukui_scp -j Change-Id: I51e22947c3f535c9a504033c502ec2ff1c688e6a Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1490801 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* chip/mt_scp: support speech-microTzung-Bi Shih2019-09-191-0/+8
| | | | | | | | | | | | | | | | | | | | If CONFIG_AUDIO_CODEC_WOV is enabled and the builder can access the EC private repository, then compile with speech-micro. Otherwise, there are dummy implementations for speech-micro API. BRANCH=none BUG=b:122027734, b:123268236, b:132319180 TEST=1. define CONFIG_AUDIO_CODEC in board.h 2. define CONFIG_AUDIO_CODEC_DMIC in board.h 3. define CONFIG_AUDIO_CODEC_DMIC_SOFTWARE_GAIN in board.h 4. define CONFIG_AUDIO_CODEC_DMIC_MAX_SOFTWARE_GAIN in board.h 5. define CONFIG_AUDIO_CODEC_WOV in board.h 6. make BOARD=kukui_scp -j Change-Id: I175903867ed7e1885e9438e8ef0dee1a8b4881b6 Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1644894 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* mtk_vcodec: Add the service for h264 decoderYunfei Dong2019-08-262-1/+8
| | | | | | | | | | | | | | | Fix the service to support h264 decoder. BRANCH=none BUG=b:123551776 TEST=build kukui_scp pass. Change-Id: Iccd6389a40239a6d6791543eeb522cc3e5fc3991 Signed-off-by: Yunfei Dong <yunfei.dong@mediatek.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1644186 Commit-Queue: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Yilun Lin <yllin@chromium.org>
* include: Move RESET_FLAG_* into ec_commands.h as EC_RESET_FLAG_*You-Cheng Syu2019-08-261-13/+13
| | | | | | | | | | | | | | | | | | | | | | | RESET_FLAGS_* are used when setting/reading the field ec_reset_flags of struct ec_response_uptime_info, which is defined in ec_commands.h. So it might be better to put those macros there. To be consistent with the other macros in the file, add "EC_" prefixes to them. BUG=b:109900671,b:118654976 BRANCH=none TEST=make buildall -j Cq-Depend: chrome-internal:1054910, chrome-internal:1054911, chrome-internal:1045539 Change-Id: If72ec25f1b34d8d46b74479fb4cd09252102aafa Signed-off-by: You-Cheng Syu <youcheng@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1520574 Tested-by: Yu-Ping Wu <yupingso@chromium.org> Commit-Ready: Yu-Ping Wu <yupingso@chromium.org> Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org> Reviewed-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* mt_scp: Do not set cache-size in SCP FW.Yilun Lin2019-08-072-6/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | cache-size and way setting should be done in kernel driver side. Logical memory address will be shifted when cache size config changes. e.g. - 8 kb I-cache + 0 kb D-cache: logical address of I-cache 0x7e000~0x7ffff - 8 kb I-cache + 8 kb D-cache: logical address of I-cache 0x7c000~0x7bfff I-cache region moves starting address from 0x7e000 to 0x7c000, and it forces all the contents which was in 0x7c000~0x7dffff step back for 8KB. i.e. The logical address are changed by 8kb. This will break the loaded SCP firmware layout. As a result, we should configure the cache size before loading firmware and never re-configure it in SCP FW. BUG=b:137920815 TEST=Reboot kukui, and see SCP can successfully boot on first time. BRANCH=None Change-Id: I58342e8276b654a786864904cde980c6fc9ef781 Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1725384 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Commit-Queue: Yilun Lin <yllin@chromium.org> Tested-by: Yilun Lin <yllin@chromium.org>
* mt_scp/ipi: only invoke interrupt when ipi readyYilun Lin2019-08-071-1/+1
| | | | | | | | | | | | | | | | | IPC interrupt should only be invoked when the task inited and informing AP that SCP is ready. TEST=Boot SCP, and doesn't see the process stack overflow. BUG=b:137920815 BRANCH=none Change-Id: Ibe926b77705718a986c3b090227328b569cd9b59 Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1736411 Reviewed-by: Erin Lo <erin.lo@mediatek.com> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Commit-Queue: Yilun Lin <yllin@chromium.org> Tested-by: Yilun Lin <yllin@chromium.org>
* chip/mt_scp/clock.c: enable pwrap_scp clockHsin-Hsiung Wang2019-07-262-4/+20
| | | | | | | | | | | | | | | | | | | | | | | | | During suspend, pmic wrap will be waken up by scp which is due to hw design. However, the clock of pmic wrap is 26mhz which would be turned off in the suspend mode, so we needs to change the clock of pmic wrap from 26mhz to ULPOSC. BRANCH=none BUG=b:135985700 TEST=make BOARD=kukui_scp -j && \ bash board/kukui_scp/update_scp $IP alias rtcalm='echo "+15" > \ /sys/class/rtc/rtc0/wakealarm' rtcalm cat /proc/driver/rtc powerd_dbus_suspend TEST=Can resume in suspend. Change-Id: I07b9d76f574fe1007e20f185bb278e0884397176 Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1686990 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Yilun Lin <yllin@chromium.org> Commit-Queue: Nicolas Boichat <drinkcat@chromium.org>
* mt_scp: Trigger IRQ if has pending IPC when re-enable SCP_IRQ_IPC0.Yilun Lin2019-07-171-3/+18
| | | | | | | | | | | | | | | | | | | | Prevent a starved waiting IPC. IPC may be requested while SCP_IRQ_IPC0 is disabled, and this may result in AP dead waiting for a reply from SCP. This CL forces triggering the SCP_IRQ_IPC0 if seeing a pending IPC when re-enable the SCP_IRQ_IPC0. TEST=run factory front_camera_test for over 1 hr and see AP doesn't complains HC not respsonsed. BUG=b:136809224, b:136616282 BRANCH=None Change-Id: Ic36da774994f6c571c3b79fd6717562f8866b7df Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1697884 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Commit-Queue: Yilun Lin <yllin@chromium.org> Tested-by: Yilun Lin <yllin@chromium.org>
* mt_scp: Drop TCM and L1 cache setting.Yilun Lin2019-07-172-8/+11
| | | | | | | | | | | | | | | | | | | | This config has been moved to kernel https://crrev.com/c/1687454 to correctly initialize L1 cache. We should drop the config in SCP side. Also, update the comment for CM4_MOD registers. TEST=Boot SCP with kernel https://crrev.com/c/1627394/10 BUG=b:132658087 BRANCH=none Change-Id: I37613533563acc00017f96a3d3009383057f072b Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1703946 Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Erin Lo <erin.lo@mediatek.com> Commit-Queue: Yilun Lin <yllin@chromium.org> Auto-Submit: Yilun Lin <yllin@chromium.org>
* mt_scp/ipi: Add ref-counted API ipi_{en,dis}able_irq()Yilun Lin2019-07-022-4/+48
| | | | | | | | | | | | | | | | | | | | | | | Unify IPC IRQ accessing to prevent a wrong IRQ enabling status. An IPC IRQ could be shared across many IPI handlers. Those handlers would usually operate on disabling or enabling the IPC IRQ. This may disorder the actual timing to on/off the IRQ when there are many tasks try to operate on it. As a result, any access to the SCP_IRQ_* should go through ipi_{en,dis}able_irq(), which support a counter to enable/disable the IRQ at correct timeing. TEST=Boot scp. BUG=b:117917141 BRANCH=master Change-Id: I792849279dfeb5231f27fa7a9cf260e2059bbf4b Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1670650 Tested-by: Yilun Lin <yllin@chromium.org> Auto-Submit: Yilun Lin <yllin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Commit-Queue: Nicolas Boichat <drinkcat@chromium.org>
* mt_scp/ipi: Host command should not wake up AP.Yilun Lin2019-06-251-1/+1
| | | | | | | | | | | | | | | | | Host command doesn't have needs to be a wake-up source (yet). We should not register it as a wake-up IPI. TEST=powerd_dbus_suspend, AP does not wake back up immediately. BUG=b:133380592 BRANCH=none Change-Id: Ie4b63a9e45bda4cdcdd0c369d9dd7e3163750bdd Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1672657 Commit-Queue: Yilun Lin <yllin@chromium.org> Tested-by: Yilun Lin <yllin@chromium.org> Auto-Submit: Yilun Lin <yllin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* chip/mt_scp/uart: Switch to use ULPOSC1_DIV10 for UARTNicolas Boichat2019-06-253-2/+21
| | | | | | | | | | | | | | | | | | | | | | | | | The 26Mhz clock is not available in S3, so use ULPOSC-sourced clock for the SCP in suspend. Also, change ULPOSC1 frequency to 240 Mhz, as this allows for a better division of the clock to get 115200 bps: - 240*1000*1000/10/(115200*16.0) => 13.02 <<< lowest error - 248*1000*1000/10/(115200*16.0) => 13.45 - 256*1000*1000/10/(115200*16.0) => 13.89 - 264*1000*1000/10/(115200*16.0) => 14.32 BRANCH=none BUG=b:134035444 TEST=make BOARD=kukui_scp -j && \ bash board/kukui_scp/update_scp $IP powerd_dbus_suspend TEST=Can interract with console SCP in suspend. TEST=Measure UART frequency with an oscilloscope: 115.7 kHz Change-Id: I3bce4e94abaa97e20bef70f4f3ef3ca4e01d57b5 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1672646 Reviewed-by: Yilun Lin <yllin@chromium.org>
* chip/mt_scp/hrtimer: Switch hrtimer to use ULPOSC1/8Nicolas Boichat2019-06-243-8/+18
| | | | | | | | | | | | | | | | | | | To be able to use the SCP in S3, we cannot rely on the 26Mhz clock, as it's off in S3. Switch to using ULPOSC1 divided by 8 instead. Also, make sure the frequency is a multiple of 8Mhz for the timer to be accurate. BRANCH=none BUG=b:134035444 TEST=make BOARD=kukui_scp -j && \ bash board/kukui_scp/update_scp $IP powerd_dbus_suspend Change-Id: I048431cc062040caea70a5de3709ddd33550439c Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1672645 Reviewed-by: Yilun Lin <yllin@chromium.org>
* chip/mt_scp/hrtimer: Change 26Mhz to a defineNicolas Boichat2019-06-241-7/+10
| | | | | | | | | | | | | | | | Instead of hardcoding 25/26 all over the place, define the value at the top of the file. That'll make it easier to change the clock later. BRANCH=none BUG=b:134035444 TEST=make BOARD=kukui_scp -j && \ bash board/kukui_scp/update_scp $IP Change-Id: I32df164c172a624560c1299049269899211815ce Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1672644 Reviewed-by: Yilun Lin <yllin@chromium.org>
* chip/mt_scp/clock: Prefer closest frequency when calibratingNicolas Boichat2019-06-241-4/+7
| | | | | | | | | | | | | | | | It's better to chose the closest possible frequency, rather than the one above the target, as the system clock is now sourced from ULPOSC1 and we want to minimize errors. BRANCH=none BUG=b:120176040 TEST=Load kukui_scp, see that ULPOSC is calibrated to 247558 kHz, instead of 250148 kHz (0.18% error, instead of 0.87%) Change-Id: I068fa09b5fedaf795ee6171f0b88ab658d5792a9 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1672655 Reviewed-by: Yilun Lin <yllin@chromium.org>
* chip/mt_scp/clock: Fix frequency meter divider (1024, not 1000)Nicolas Boichat2019-06-241-10/+10
| | | | | | | | | | | | | | | | | The frequency meter measures at 26 Mhz / 1024, not 26 Mhz / 1000, and use DIV_ROUND_CLOSEST to get a closer frequency meter target. Also, print the frequencies in kHz, not Mhz. BRANCH=none BUG=b:120176040 TEST=Add new timer sourced from (precise) 32.768 kHz to tick every second, see that the interval is close to a second. Change-Id: I32a9265187ed2936a928f2c09da8f544d814b5ae Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1672650 Reviewed-by: Yilun Lin <yllin@chromium.org>
* chip/mt_scp/clock: Move ULPOSC1/2 frequency settings to clock_chip.hNicolas Boichat2019-06-242-15/+16
| | | | | | | | | | | | | | | | Refactor the code to make it easier for hrtimer to use ULPOSC1 frequency. BRANCH=none BUG=b:134035444 TEST=make BOARD=kukui_scp -j && \ bash board/kukui_scp/update_scp $IP powerd_dbus_suspend Change-Id: Ic1a7eab0f9075bf77c1b17ace9e3e95bee2924df Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1672656 Reviewed-by: Yilun Lin <yllin@chromium.org>
* chip/mt_scp/clock: Wait longer for clock measurement to completeNicolas Boichat2019-06-241-5/+11
| | | | | | | | | | | | | | | | Instead of a fixed-time wait, for in a loop (and a little longer) for the measurement to complete. This is useful when running ulposc in command line after the SCP has started, as the clock is then faster and the busy_udelay completes faster. BRANCH=none BUG=b:120176040 TEST=Deploy kukui_scp, ulposc works after boot. Change-Id: I2148ef6f6b7e7e673b035b9eee65cb6a83c9e9ae Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1672647 Reviewed-by: Yilun Lin <yllin@chromium.org>
* mt_scp/ipi: Do not support ipi_send in ISR contextYilun Lin2019-06-232-7/+5
| | | | | | | | | | | | | | | | | No one uses ipi_send in ISR, and removing this can simplify the ipi_send logic. TEST=runs SCP, and see it doesn't print it sends IPI in ISR. BUG=b:117917141 BRANCH=none Change-Id: I96115ffc4124331d864daff2d375021c76a74b0c Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1670649 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Commit-Queue: Yilun Lin <yllin@chromium.org> Tested-by: Yilun Lin <yllin@chromium.org> Auto-Submit: Yilun Lin <yllin@chromium.org>
* kukui: scp: calibrate ULPOSC1&2Rong Chang2019-06-222-66/+178
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ULPOSC generates clock for SCP core and peripherals. The calibration process adjust 2 values, div and cali. Both values are positive correlated to OSC frequency. The frequency function is: f(div, cali) = k1 * (div + k2) / R(cali) * C Where: R(cali) = k3 / (1 + k4 * (cali - k4)) The actual frequency is not linear to cali parameter. This change selects the div that generates closest frequency when cali == 32. And then adjust cali to get better output. [drinkcat: This relands e08a71fd0 "kukui: scp: calibrate ULPOSC1&2", with the following modifications: - Replace udelay by udelay_busy as the clock is not yet ready when calibrating - Simplify calibration logic. ] BRANCH=none BUG=b:120176040,b:120169529 TEST=manual check SCP console command: > ulposc ULPOSC1 frequency: 252 MHz ULPOSC2 frequency: 333 MHz Change-Id: I1a6b9d1ad140cd67b1fdecebf14b61cad88b2c4f Signed-off-by: Rong Chang <rongchang@chromium.org> Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1655221 Reviewed-by: Yilun Lin <yllin@chromium.org>
* chip/mt_scp: Add dummy read in D-cache invalidation functionsNicolas Boichat2019-06-141-5/+8
| | | | | | | | | | | | | | | | | With this, we only need to call cpu_invalidate_dcache once. Only tested thoroughly on boot, but the dummy reads should not hurt for the other operations. BRANCH=none BUG=b:123205971 TEST=See bug, check that cache is invalidated after first flush, on boot. Change-Id: I74f4fa89c0b9254c324955f4079b7db3832eaf43 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1632129 Reviewed-by: Yilun Lin <yllin@chromium.org>
* chip/mt_scp: Fix clock selection register values for ULPOSC_1/2Nicolas Boichat2019-06-141-4/+4
| | | | | | | | | | | | | | Values were incorrect, previously. BRANCH=none BUG=b:125616659 TEST=See bug. With CL:1475091, cycle count/time actually matches the expected frequency. Change-Id: Icdca1809dc202d527b708ce3df7ea19ac7f60532 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1657080 Reviewed-by: Yilun Lin <yllin@chromium.org>
* kukui_scp: Enable MPU to protect code RAM and data RAM in RW image.Yilun Lin2019-05-022-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | kukui_scp is loaded into SRAM. We would like to protect the memory from a modified code RAM content and executing injected code in data RAM. BRANCH=None BUG=b:123269246 TEST=Apply MPU test patch https://crrev.com/c/1530265. Test data ram XN: 1. mpu 0 # disable MPU 2. mpu_test # see it prints 3. mpu 1 # enable MPU 4. mpu_test # memory access violation, and reset. 5. mpu_test # memory access violation, and reset # again. (MPU enabled by default) Test code ram RO: 1. rw 0x8 0x5566 # Write to code RAM and see memory # access violation and reset. 2. mpu 0 # disable MPU 3. rw 0x8 0x5566 # Nothing happended 4. rw 0x8 # Read 0x5566 5. mpu 1 # enable MPU 6. rw 0x8 0x5566 # memory access violation. Change-Id: I6af5029d8c55d795543d4759b2c9168a06eb9ff1 Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/1530264 Commit-Ready: Yilun Lin <yllin@chromium.org> Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Rong Chang <rongchang@chromium.org>
* mt_scp: Generate IPI tables with util gen_ipi_table.Yilun Lin2019-04-302-25/+10
| | | | | | | | | | | | | | | | | | | | IPI table is board-specific. This CL removes the original IPI table in chip layer, and uses gen_ipi_table to generate the table for each board to reduce the maintenance effort. TEST=make BOARD=kukui_scp, and see build/kukui_scp/ipi_table_gen.inc exists. Push to Kukui, and see SCP boots. TEST=modify IPI_COUNT in board.h and see it generates a new ipi_table_gen.inc BUG=b:130508869 BRANCH=None Change-Id: I0c05319447d15917e8833aa80d61166c4e396370 Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/1568890 Commit-Ready: Yilun Lin <yllin@chromium.org> Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* Revert "kukui: scp: calibrate ULPOSC1&2"Yilun Lin2019-04-262-183/+66
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit e08a71fd05bfc9e32dd64b7e15840e7232d72788. Reason for revert: SCP will hang with this CL. Original change's description: > kukui: scp: calibrate ULPOSC1&2 > > ULPOSC generates clock for SCP core and peripherals. The calibration > process adjust 2 values, div and cali. Both values are positive > correlated to OSC frequency. The frequency function is: > f(div, cali) = k1 * (div + k2) / R(cali) * C > Where: > R(cali) = k3 / (1 + k4 * (cali - k4)) > > The actual frequency is not linear to cali parameter. This change > selects the div that generates closest frequency when cali == 32. And > then adjust cali to get better output. > > BRANCH=none > BUG=b:120176040,b:120169529 > TEST=manual > check SCP console command: > > ulposc > ULPOSC1 frequency: 248 MHz > ULPOSC2 frequency: 330 MHz > > Change-Id: Ifac9d481e654064ee60d84819added5e164ed7c2 > Signed-off-by: Rong Chang <rongchang@chromium.org> > Reviewed-on: https://chromium-review.googlesource.com/1520571 > Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Bug: b:120176040, b:120169529, b:131273034 Change-Id: Ifaeb9a7835a35556587fac4c039b9fde6d66504d Reviewed-on: https://chromium-review.googlesource.com/1583481 Commit-Ready: Yilun Lin <yllin@chromium.org> Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Yilun Lin <yllin@chromium.org>
* kukui: scp: calibrate ULPOSC1&2Rong Chang2019-04-242-66/+183
| | | | | | | | | | | | | | | | | | | | | | | | | | ULPOSC generates clock for SCP core and peripherals. The calibration process adjust 2 values, div and cali. Both values are positive correlated to OSC frequency. The frequency function is: f(div, cali) = k1 * (div + k2) / R(cali) * C Where: R(cali) = k3 / (1 + k4 * (cali - k4)) The actual frequency is not linear to cali parameter. This change selects the div that generates closest frequency when cali == 32. And then adjust cali to get better output. BRANCH=none BUG=b:120176040,b:120169529 TEST=manual check SCP console command: > ulposc ULPOSC1 frequency: 248 MHz ULPOSC2 frequency: 330 MHz Change-Id: Ifac9d481e654064ee60d84819added5e164ed7c2 Signed-off-by: Rong Chang <rongchang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1520571 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* mkbp: take timestamp closer to hardware interruptJett Rink2019-04-241-2/+10
| | | | | | | | | | | | | | | | | We want to ensure that the timestamp we take for last mkbp is as close to the actual hardware interrupt from EC->AP. BRANCH=none BUG=b:129159505 TEST=passing CTS sensor run (except test 133 nullptr) with this change Change-Id: I94b214f021f0b63ff2883e5fe8e32acc83ce208f Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1560390 Tested-by: Alexandru M Stan <amstan@chromium.org> Reviewed-by: Enrico Granata <egranata@chromium.org> Reviewed-by: Mathew King <mathewk@chromium.org> Commit-Queue: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
* kukui: scp: move CPU clock selection to clock moduleRong Chang2019-04-232-2/+6
| | | | | | | | | | | | | | | | CPU clock management should be in clock module. BUG=b:120169529 BRANCH=none TEST=manual build and load on kukui, check SCP console command: > rw 0x405C4000 read 0x405c4000 = 0x00000803 Change-Id: Ic13e9a51cf682af33799b713849fd3a445e6cfdb Signed-off-by: Rong Chang <rongchang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1538097 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* kukui: scp: Set CPU clock to default before ULPOSC calibrationRong Chang2019-04-231-0/+1
| | | | | | | | | | | | | | | | | | ULPOSC 1 & 2 calibration may fail if SCP CPU clock selection is configured to one of them. The SCP reset mechanism does not reset the clock selection. So before calibration, set CPU to default clock. BUG=b:125695639 BRANCH=none TEST=manual build and load on kukui, check remoteproc init correctly. check SCP uart console command 'ulposc', output non-zero clocks. Change-Id: I6807017808a663f8e80363dc0672748ab1957978 Signed-off-by: Rong Chang <rongchang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1538096 Reviewed-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* mt_scp: Move ROM_BASE to 0x0.Yilun Lin2019-04-134-25/+1
| | | | | | | | | | | | | | | | | | | | Removes stepping_stone regions, and move ROM_BASE from 0x800 to 0x0. stepping_stone region is to smooth SCP's bringing up stage for being compatible with both original and new implementation. Now that we have done the kernel side driver implementation, we can earn more SRAM space by removing the stepping_stone. TEST=run SCP on kukui, and see it boots. BRANCH=None BUG=b:120825336 Change-Id: I253904592fa0187f627b2eaa3f5d12a17db9960f Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/1563871 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* kukui: scp: fix udelay hangs the system in clock enable.Pi-Hsun Shih2019-04-041-2/+15
| | | | | | | | | | | | | | | | | It seems that udelay doesn't work before the clock is properly configured and enabled, causing the SCP image not able to boot. Remove the udelay in scp_clock_high_enable. BUG=b:128877063 TEST=manually, make sure SCP firmware works on boot. BRANCH=none Change-Id: Idc505a33a7e88d136a5b50f2e5bd52bd5213393b Signed-off-by: Pi-Hsun Shih <pihsun@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1530410 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Rong Chang <rongchang@chromium.org>
* kukui_scp: Enable CONFIG_LTONicolas Boichat2019-03-261-1/+1
| | | | | | | | | | | | | | | | | | | | | Fix the stepping stone code stack_end definition to match the one in vecttable.c (else LTO complains). Add __keep to SECTION_KEEP to prevent LTO from dropping the stepping stone. BRANCH=none BUG=b:129111699 TEST=kukui_scp boots, kernel recognizes it TEST=Saves ~1.5kb of RAM. Before/after: *** 459968 bytes in RAM still available on kukui_scp **** *** 461528 bytes in RAM still available on kukui_scp **** Change-Id: I07e9d9ac003bdc5fce2617aa3aad072b51f89b6b Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1535089 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Yilun Lin <yllin@chromium.org>
* common: bit change 1 << constants with BIT(constants)Gwendal Grignou2019-03-263-6/+6
| | | | | | | | | | | | | | | | | Mechanical replacement of bit operation where operand is a constant. More bit operation exist, but prone to errors. Reveal a bug in npcx: chip/npcx/system-npcx7.c:114:54: error: conversion from 'long unsigned int' to 'uint8_t' {aka 'volatile unsigned char'} changes value from '16777215' to '255' [-Werror=overflow] BUG=None BRANCH=None TEST=None Change-Id: I006614026143fa180702ac0d1cc2ceb1b3c6eeb0 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1518660 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* common: replace 1 << digits, with BIT(digits)Gwendal Grignou2019-03-263-93/+93
| | | | | | | | | | | | | | | | Requested for linux integration, use BIT instead of 1 << First step replace bit operation with operand containing only digits. Fix an error in motion_lid try to set bit 31 of a signed integer. BUG=None BRANCH=None TEST=compile Change-Id: Ie843611f2f68e241f0f40d4067f7ade726951d29 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1518659 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* common: Include compile_time_macros.h when neededGwendal Grignou2019-03-261-0/+1
| | | | | | | | | | | | | Include compile_time_macros.h to files that will use BIT macro. BUG=None BRANCH=None TEST=unit tests. Change-Id: I9d44f4b588620f6770f8d522d422f5dd0d237903 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1525156 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* mt_scp: Move some configs to board/config.h.Yilun Lin2019-03-211-26/+1
| | | | | | | | | | | | | | | | | The memory layout of mt_scp is highly configurable, and it may vary from board to board. We move RAM layout from chip config to board config. BRANCH=None TEST=make BOARD=kukui_scp -j -B BUG=b:123269246 Change-Id: I9780a0de50e380533a668fd99302c78cf5fc3e91 Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/1530262 Commit-Ready: Yilun Lin <yllin@chromium.org> Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* kukui: scp: fix ULPOSC index using 0 base numberingRong Chang2019-03-161-15/+14
| | | | | | | | | | | | | | | | | | Where ULPOSC1 should be 0 and ULPOSC2 is 1. BRANCH=none BUG=b:125616659 TEST=manual Check scp console comamnd: > ulposc still output correct ULPOSC1 and ULPOSC2 clock in MHz. Change-Id: I3730ebb83bbe5e0021360116dbd37bcccdbc77aa Signed-off-by: Rong Chang <rongchang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1520570 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
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