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* kukui: scp: calibrate ULPOSC1&2Rong Chang2019-06-222-66/+178
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ULPOSC generates clock for SCP core and peripherals. The calibration process adjust 2 values, div and cali. Both values are positive correlated to OSC frequency. The frequency function is: f(div, cali) = k1 * (div + k2) / R(cali) * C Where: R(cali) = k3 / (1 + k4 * (cali - k4)) The actual frequency is not linear to cali parameter. This change selects the div that generates closest frequency when cali == 32. And then adjust cali to get better output. [drinkcat: This relands e08a71fd0 "kukui: scp: calibrate ULPOSC1&2", with the following modifications: - Replace udelay by udelay_busy as the clock is not yet ready when calibrating - Simplify calibration logic. ] BRANCH=none BUG=b:120176040,b:120169529 TEST=manual check SCP console command: > ulposc ULPOSC1 frequency: 252 MHz ULPOSC2 frequency: 333 MHz Change-Id: I1a6b9d1ad140cd67b1fdecebf14b61cad88b2c4f Signed-off-by: Rong Chang <rongchang@chromium.org> Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1655221 Reviewed-by: Yilun Lin <yllin@chromium.org>
* chip/mt_scp: Add dummy read in D-cache invalidation functionsNicolas Boichat2019-06-141-5/+8
| | | | | | | | | | | | | | | | | With this, we only need to call cpu_invalidate_dcache once. Only tested thoroughly on boot, but the dummy reads should not hurt for the other operations. BRANCH=none BUG=b:123205971 TEST=See bug, check that cache is invalidated after first flush, on boot. Change-Id: I74f4fa89c0b9254c324955f4079b7db3832eaf43 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1632129 Reviewed-by: Yilun Lin <yllin@chromium.org>
* chip/mt_scp: Fix clock selection register values for ULPOSC_1/2Nicolas Boichat2019-06-141-4/+4
| | | | | | | | | | | | | | Values were incorrect, previously. BRANCH=none BUG=b:125616659 TEST=See bug. With CL:1475091, cycle count/time actually matches the expected frequency. Change-Id: Icdca1809dc202d527b708ce3df7ea19ac7f60532 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1657080 Reviewed-by: Yilun Lin <yllin@chromium.org>
* kukui_scp: Enable MPU to protect code RAM and data RAM in RW image.Yilun Lin2019-05-022-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | kukui_scp is loaded into SRAM. We would like to protect the memory from a modified code RAM content and executing injected code in data RAM. BRANCH=None BUG=b:123269246 TEST=Apply MPU test patch https://crrev.com/c/1530265. Test data ram XN: 1. mpu 0 # disable MPU 2. mpu_test # see it prints 3. mpu 1 # enable MPU 4. mpu_test # memory access violation, and reset. 5. mpu_test # memory access violation, and reset # again. (MPU enabled by default) Test code ram RO: 1. rw 0x8 0x5566 # Write to code RAM and see memory # access violation and reset. 2. mpu 0 # disable MPU 3. rw 0x8 0x5566 # Nothing happended 4. rw 0x8 # Read 0x5566 5. mpu 1 # enable MPU 6. rw 0x8 0x5566 # memory access violation. Change-Id: I6af5029d8c55d795543d4759b2c9168a06eb9ff1 Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/1530264 Commit-Ready: Yilun Lin <yllin@chromium.org> Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Rong Chang <rongchang@chromium.org>
* mt_scp: Generate IPI tables with util gen_ipi_table.Yilun Lin2019-04-302-25/+10
| | | | | | | | | | | | | | | | | | | | IPI table is board-specific. This CL removes the original IPI table in chip layer, and uses gen_ipi_table to generate the table for each board to reduce the maintenance effort. TEST=make BOARD=kukui_scp, and see build/kukui_scp/ipi_table_gen.inc exists. Push to Kukui, and see SCP boots. TEST=modify IPI_COUNT in board.h and see it generates a new ipi_table_gen.inc BUG=b:130508869 BRANCH=None Change-Id: I0c05319447d15917e8833aa80d61166c4e396370 Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/1568890 Commit-Ready: Yilun Lin <yllin@chromium.org> Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* Revert "kukui: scp: calibrate ULPOSC1&2"Yilun Lin2019-04-262-183/+66
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit e08a71fd05bfc9e32dd64b7e15840e7232d72788. Reason for revert: SCP will hang with this CL. Original change's description: > kukui: scp: calibrate ULPOSC1&2 > > ULPOSC generates clock for SCP core and peripherals. The calibration > process adjust 2 values, div and cali. Both values are positive > correlated to OSC frequency. The frequency function is: > f(div, cali) = k1 * (div + k2) / R(cali) * C > Where: > R(cali) = k3 / (1 + k4 * (cali - k4)) > > The actual frequency is not linear to cali parameter. This change > selects the div that generates closest frequency when cali == 32. And > then adjust cali to get better output. > > BRANCH=none > BUG=b:120176040,b:120169529 > TEST=manual > check SCP console command: > > ulposc > ULPOSC1 frequency: 248 MHz > ULPOSC2 frequency: 330 MHz > > Change-Id: Ifac9d481e654064ee60d84819added5e164ed7c2 > Signed-off-by: Rong Chang <rongchang@chromium.org> > Reviewed-on: https://chromium-review.googlesource.com/1520571 > Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Bug: b:120176040, b:120169529, b:131273034 Change-Id: Ifaeb9a7835a35556587fac4c039b9fde6d66504d Reviewed-on: https://chromium-review.googlesource.com/1583481 Commit-Ready: Yilun Lin <yllin@chromium.org> Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Yilun Lin <yllin@chromium.org>
* kukui: scp: calibrate ULPOSC1&2Rong Chang2019-04-242-66/+183
| | | | | | | | | | | | | | | | | | | | | | | | | | ULPOSC generates clock for SCP core and peripherals. The calibration process adjust 2 values, div and cali. Both values are positive correlated to OSC frequency. The frequency function is: f(div, cali) = k1 * (div + k2) / R(cali) * C Where: R(cali) = k3 / (1 + k4 * (cali - k4)) The actual frequency is not linear to cali parameter. This change selects the div that generates closest frequency when cali == 32. And then adjust cali to get better output. BRANCH=none BUG=b:120176040,b:120169529 TEST=manual check SCP console command: > ulposc ULPOSC1 frequency: 248 MHz ULPOSC2 frequency: 330 MHz Change-Id: Ifac9d481e654064ee60d84819added5e164ed7c2 Signed-off-by: Rong Chang <rongchang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1520571 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* mkbp: take timestamp closer to hardware interruptJett Rink2019-04-241-2/+10
| | | | | | | | | | | | | | | | | We want to ensure that the timestamp we take for last mkbp is as close to the actual hardware interrupt from EC->AP. BRANCH=none BUG=b:129159505 TEST=passing CTS sensor run (except test 133 nullptr) with this change Change-Id: I94b214f021f0b63ff2883e5fe8e32acc83ce208f Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1560390 Tested-by: Alexandru M Stan <amstan@chromium.org> Reviewed-by: Enrico Granata <egranata@chromium.org> Reviewed-by: Mathew King <mathewk@chromium.org> Commit-Queue: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
* kukui: scp: move CPU clock selection to clock moduleRong Chang2019-04-232-2/+6
| | | | | | | | | | | | | | | | CPU clock management should be in clock module. BUG=b:120169529 BRANCH=none TEST=manual build and load on kukui, check SCP console command: > rw 0x405C4000 read 0x405c4000 = 0x00000803 Change-Id: Ic13e9a51cf682af33799b713849fd3a445e6cfdb Signed-off-by: Rong Chang <rongchang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1538097 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* kukui: scp: Set CPU clock to default before ULPOSC calibrationRong Chang2019-04-231-0/+1
| | | | | | | | | | | | | | | | | | ULPOSC 1 & 2 calibration may fail if SCP CPU clock selection is configured to one of them. The SCP reset mechanism does not reset the clock selection. So before calibration, set CPU to default clock. BUG=b:125695639 BRANCH=none TEST=manual build and load on kukui, check remoteproc init correctly. check SCP uart console command 'ulposc', output non-zero clocks. Change-Id: I6807017808a663f8e80363dc0672748ab1957978 Signed-off-by: Rong Chang <rongchang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1538096 Reviewed-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* mt_scp: Move ROM_BASE to 0x0.Yilun Lin2019-04-134-25/+1
| | | | | | | | | | | | | | | | | | | | Removes stepping_stone regions, and move ROM_BASE from 0x800 to 0x0. stepping_stone region is to smooth SCP's bringing up stage for being compatible with both original and new implementation. Now that we have done the kernel side driver implementation, we can earn more SRAM space by removing the stepping_stone. TEST=run SCP on kukui, and see it boots. BRANCH=None BUG=b:120825336 Change-Id: I253904592fa0187f627b2eaa3f5d12a17db9960f Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/1563871 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* kukui: scp: fix udelay hangs the system in clock enable.Pi-Hsun Shih2019-04-041-2/+15
| | | | | | | | | | | | | | | | | It seems that udelay doesn't work before the clock is properly configured and enabled, causing the SCP image not able to boot. Remove the udelay in scp_clock_high_enable. BUG=b:128877063 TEST=manually, make sure SCP firmware works on boot. BRANCH=none Change-Id: Idc505a33a7e88d136a5b50f2e5bd52bd5213393b Signed-off-by: Pi-Hsun Shih <pihsun@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1530410 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Rong Chang <rongchang@chromium.org>
* kukui_scp: Enable CONFIG_LTONicolas Boichat2019-03-261-1/+1
| | | | | | | | | | | | | | | | | | | | | Fix the stepping stone code stack_end definition to match the one in vecttable.c (else LTO complains). Add __keep to SECTION_KEEP to prevent LTO from dropping the stepping stone. BRANCH=none BUG=b:129111699 TEST=kukui_scp boots, kernel recognizes it TEST=Saves ~1.5kb of RAM. Before/after: *** 459968 bytes in RAM still available on kukui_scp **** *** 461528 bytes in RAM still available on kukui_scp **** Change-Id: I07e9d9ac003bdc5fce2617aa3aad072b51f89b6b Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1535089 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Yilun Lin <yllin@chromium.org>
* common: bit change 1 << constants with BIT(constants)Gwendal Grignou2019-03-263-6/+6
| | | | | | | | | | | | | | | | | Mechanical replacement of bit operation where operand is a constant. More bit operation exist, but prone to errors. Reveal a bug in npcx: chip/npcx/system-npcx7.c:114:54: error: conversion from 'long unsigned int' to 'uint8_t' {aka 'volatile unsigned char'} changes value from '16777215' to '255' [-Werror=overflow] BUG=None BRANCH=None TEST=None Change-Id: I006614026143fa180702ac0d1cc2ceb1b3c6eeb0 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1518660 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* common: replace 1 << digits, with BIT(digits)Gwendal Grignou2019-03-263-93/+93
| | | | | | | | | | | | | | | | Requested for linux integration, use BIT instead of 1 << First step replace bit operation with operand containing only digits. Fix an error in motion_lid try to set bit 31 of a signed integer. BUG=None BRANCH=None TEST=compile Change-Id: Ie843611f2f68e241f0f40d4067f7ade726951d29 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1518659 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* common: Include compile_time_macros.h when neededGwendal Grignou2019-03-261-0/+1
| | | | | | | | | | | | | Include compile_time_macros.h to files that will use BIT macro. BUG=None BRANCH=None TEST=unit tests. Change-Id: I9d44f4b588620f6770f8d522d422f5dd0d237903 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1525156 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* mt_scp: Move some configs to board/config.h.Yilun Lin2019-03-211-26/+1
| | | | | | | | | | | | | | | | | The memory layout of mt_scp is highly configurable, and it may vary from board to board. We move RAM layout from chip config to board config. BRANCH=None TEST=make BOARD=kukui_scp -j -B BUG=b:123269246 Change-Id: I9780a0de50e380533a668fd99302c78cf5fc3e91 Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/1530262 Commit-Ready: Yilun Lin <yllin@chromium.org> Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* kukui: scp: fix ULPOSC index using 0 base numberingRong Chang2019-03-161-15/+14
| | | | | | | | | | | | | | | | | | Where ULPOSC1 should be 0 and ULPOSC2 is 1. BRANCH=none BUG=b:125616659 TEST=manual Check scp console comamnd: > ulposc still output correct ULPOSC1 and ULPOSC2 clock in MHz. Change-Id: I3730ebb83bbe5e0021360116dbd37bcccdbc77aa Signed-off-by: Rong Chang <rongchang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1520570 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* kukui: scp: fix ULPOSC configuration and add OSC clock measurementRong Chang2019-03-162-53/+113
| | | | | | | | | | | | | | | | | | | | The initial clock change turned on wrong clock gate while enabling ULPOSC2. This change fixed clock gate and ULPOSC configuration. A clock measuring console command is added to check clock speed. BRANCH=none BUG=b:120176040,b:125616659,b:124472114 TEST=manual Build and load on kukui. Check console command out: > ulposc ULPOSC1 frequency: 210 MHz ULPOSC2 frequency: 271 MHz Change-Id: I19e637d97bc125a1bbfd102a5fc5ec24573d9e09 Signed-off-by: Rong Chang <rongchang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1485040 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* kukui: scp: fix wrong logic on checking ULPOSC numberRong Chang2019-03-161-1/+1
| | | | | | | | | | | | | | | | | The logic should be either OSC1 or OSC2. BRANCH=none BUG=b:125616659 TEST=manual rw 0xA000C708 bit 23 should be 1 Change-Id: I15f75f37b09bde04e7d23aebe549f3ec49767783 Signed-off-by: Rong Chang <rongchang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1488636 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* kukui: scp: move clock and oscillator configuration code to clock.cRong Chang2019-03-163-109/+119
| | | | | | | | | | | | | | | | To implement ULPOSC calibration, clock and oscillator APIs are moved from system to its own module. BRANCH=none BUG=b:120176040 TEST=manual make BOARD=kukui_scp -j Change-Id: I143b331f5d36cd0d0964920a9b7e7fe00afb6e3b Signed-off-by: Rong Chang <rongchang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1488635 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* kukui: scp: set CPU clock to ULPOSC2Rong Chang2019-03-162-0/+6
| | | | | | | | | | | | | | | | | | | | SCP CPU clock source can be sourced from 26MHz system clock, 32K low speed clock, and 2 high speed sources ULPOSC1, ULPOSC2. ULPOSC2 is enabled to run at 330MHz by default. This CL switch CPU to ULPOSC2 after enabling the source. BRANCH=none BUG=b:125616659 TEST=manual check current clock source using console command: > rw 0x405C4000 read 0x405c4000 = 0x00000803 Change-Id: I11672e2eb5b5a3ebebdf2a21a6ebed83b4535ee5 Signed-off-by: Rong Chang <rongchang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1482631 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* mt_scp: Check for IPI_NS_SERVICE in ipi_send.Pi-Hsun Shih2019-03-121-0/+5
| | | | | | | | | | | | | | | | | Since the IPI_NS_SERVICE is send-only, there's no corresponding IPI handler on the SCP side, and the IPI ID is 0xFF which is outside of the table range. Check that the IPI ID is not IPI_NS_SERVICE before checking if the IPI is a wakeup source. BUG=b:126535633 TEST=build BRANCH=none Change-Id: Id8b67be235afd9606b8d09257c7938a2695bcc0b Signed-off-by: Pi-Hsun Shih <pihsun@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1498953 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Yilun Lin <yllin@chromium.org>
* mt_scp/ipi: Support host event over IPI.Yilun Lin2019-03-121-4/+37
| | | | | | | | | | | | | | | | | | | | mt_scp doesn't support GPIO-interrupt-based and mkbp_event-based host event. This CL enables host event over IPI, and shares the same IPI channel with host command, and use an extra byte to distinguish the host command and host event. BUG=b:120808999 TEST=run FW on kukui, and set host_event via hostevent set 0x111 and see AP sends host command: EC_CMD_GET_NEXT_EVENT [33.737487 HC 0x67] to querry event. BRANCH=None Change-Id: I741718e24aa107da3ec1733bdbb8482f16c8a38d Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/1411432 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* kukui_scp/ipi: Clarify ipi_send() signature.Yilun Lin2019-03-072-2/+2
| | | | | | | | | | | | | | | | ipi_send() shuold not modify the buffer argument. This CL changes argument type from 'void *' to 'const void *'. TEST=make BOARD=kukui_scp -j BUG=b:120808999 BRANCH=None Change-Id: I1e629c7d6ba6902df1e8e2a21b7ac29bf3dffebf Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/1490796 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Pi-Hsun Shih <pihsun@chromium.org>
* kukui_scp: Add rpmsg name service.Peter Shih2019-03-042-0/+25
| | | | | | | | | | | | | | | | rpmsg name service provide a way for firmware to announce available rpmsg channels and its IPI id to AP, without AP having to hard-code all the IPI ids. BUG=b:120953723 TEST=manually BRANCH=none Change-Id: I8ec539a45b58f20e70a798ede4abaad5a7bb4360 Signed-off-by: Pi-Hsun Shih <pihsun@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1389986 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Yilun Lin <yllin@chromium.org>
* mt_scp: Add functions to clean/invalidated selected ranges of D-cacheNicolas Boichat2019-02-202-11/+24
| | | | | | | | | | | | | | | | | | | | | The previous version could only work on single lines, let's add functions to work on ranges. BRANCH=none BUG=b:123676508 TEST=fill; flush; fill to generate incoherent DRAM/cache content TEST=flush 0x10000000 16 c => clean a single line flush 0x10000020 32 c => clean a single line flush 0x10000040 64 c => clean 2 lines TEST=flush 0x10000080 16 i => invalidate 1 line flush 0x100000a0 32 i => invalidate 1 line flush 0x100000c0 64 i => invalidate 2 lines Change-Id: Ib386eeb4ce5d2f64a23e558c7f562eba234e6b0d Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1475105 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Yilun Lin <yllin@chromium.org>
* mt_scp: Add functions to clean/invalidated selected lines of D-cacheNicolas Boichat2019-02-191-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For performance reasons, we want to be able to flush/invalidate only specific cache lines/addresses. BRANCH=none BUG=b:123676508 TEST=fill; flush; fill to generate incoherent DRAM/cache content: cached: 10000000: 89905d00 89905d01 89905d02 89905d03 89905d04 89905d05 89905d06 89905d07 10000020: 89905d08 89905d09 89905d0a 89905d0b 89905d0c 89905d0d 89905d0e 89905d0f direct: 30000000: 3848c300 3848c301 3848c302 3848c303 3848c304 3848c305 3848c306 3848c307 30000020: 3848c308 3848c309 3848c30a 3848c30b 3848c30c 3848c30d 3848c30e 3848c30f => Then clean a cache line > flush 0x10000000 c Clean cached: 10000000: 89905d00 89905d01 89905d02 89905d03 89905d04 89905d05 89905d06 89905d07 10000020: 89905d08 89905d09 89905d0a 89905d0b 89905d0c 89905d0d 89905d0e 89905d0f direct: 30000000: 89905d00 89905d01 89905d02 89905d03 89905d04 89905d05 89905d06 89905d07 30000020: 3848c308 3848c309 3848c30a 3848c30b 3848c30c 3848c30d 3848c30e 3848c30f => memory is updated => Then invalidate a cache line > flush 0x10000020 i Inval 10000020 cached: 10000000: 89905d00 89905d01 89905d02 89905d03 89905d04 89905d05 89905d06 89905d07 10000020: 3848c308 3848c309 3848c30a 3848c30b 3848c30c 3848c30d 3848c30e 3848c30f direct: 30000000: 89905d00 89905d01 89905d02 89905d03 89905d04 89905d05 89905d06 89905d07 30000020: 3848c308 3848c309 3848c30a 3848c30b 3848c30c 3848c30d 3848c30e 3848c30f => cache content is thrown away, and matches memory Change-Id: I5dbcc366236fef56f7cb048ce313247cf3d51276 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1475092 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Yilun Lin <yllin@chromium.org>
* kukui_scp: Always use watchdog reset on reboot.Pi-Hsun Shih2019-02-191-3/+4
| | | | | | | | | | | | BUG=b:120889996 TEST=`reboot` in SCP console, and see that it triggers a watchdog reset. BRANCH=none Change-Id: I4b629dc32dfd3bed8d802b211c1170ff72ee0943 Signed-off-by: Pi-Hsun Shih <pihsun@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1469853 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* mt_scp: Add support to store some code in DRAMNicolas Boichat2019-01-241-0/+5
| | | | | | | | | | | | | | | | | This allows to store specific code/data in a .dram region. This is used by mt_scp to run code off DRAM, as we plan to have more code than what can fit in SRAM. BRANCH=none BUG=b:122058243 TEST=make BOARD=kukui_scp -j objdump -x build/kukui_scp/ec.obj => Some code is loaded in DRAM TEST=Load kukui_scp, icachetest works Change-Id: Idbab809ba86cabe3b984944adc2781b37d2d544b Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1391542
* mt_scp: Enable I/D-cache on bootNicolas Boichat2019-01-243-7/+205
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable cache mapping on boot, add functions for cache support. Invalidate the cache on boot, and add benchmarching function. BRANCH=none BUG=b:117804463 TEST=Boot kukui_scp with TEST-ONLY CL. TEST=Run dcachetest command, see performance difference, and lack of coherency if the data is updated from AP side. > dcachetest cached: 19745 us (val: ef915230) cached+inval: 39402 us (val: ef915230) direct: 94096 us (val: ef915230) TEST=See that icachetest (cached) and perftest have similar performance: > icachetest run from DRAM (cached): 102779 us (total: 12a052eb9) run from DRAM (direct): 1867168 us (total: 12a052eb9) > perftest run from SRAM: 102566 us (total: 12a052eb9) TEST=cacheinfo reports sensible data: > cacheinfo Icache hit count: 12000127 Icache access count: 12000131 Dcache hit count: 960034 Dcache access count: 1024034 Change-Id: I3272f4ff9edc0059c4937908b1235346c582c680 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1391529 Reviewed-by: Rong Chang <rongchang@chromium.org>
* mt_scp/memmap: Enable memmap between AP and SCP.Yilun Lin2019-01-245-23/+224
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SCP/AP can access the AP/SCP address via memory address translation. TEST=Run memmap (TEST-ONLY CL), see direct mapping makes sense: Direct mapping: 00001000 INVAL 0f002000 INVAL 10003000 INVAL 1f004000 INVAL 20005000 40005000 => 20005000 OK 2f006000 4f006000 => 2f006000 OK 30007000 50007000 => 30007000 OK 3f008000 5f008000 => 3f008000 OK 40009000 INVAL 4f00a000 INVAL 5000b000 INVAL 5f00c000 INVAL 6000d000 6000d000 => 6000d000 OK 6f00e000 6f00e000 => 6f00e000 OK 7000f000 7000f000 => 7000f000 OK 7f010000 7f010000 => 7f010000 OK 80011000 80011000 => 80011000 OK 8f012000 8f012000 => 8f012000 OK 90013000 00013000 => 90013000 OK 9f014000 0f014000 => 9f014000 OK a0015000 10015000 => a0015000 OK af016000 1f016000 => af016000 OK b0017000 20017000 => b0017000 OK bf018000 2f018000 => bf018000 OK c0019000 30019000 => c0019000 OK cf01a000 3f01a000 => cf01a000 OK d001b000 1001b000 => a001b000 BAD df01c000 1f01c000 => af01c000 BAD (these are ok as 0x1* is mapped from both 0xd* and 0xa*) e001d000 a001d000 => e001d000 OK ef01e000 af01e000 => ef01e000 OK f001f000 9001f000 => f001f000 OK ff020000 9f020000 => ff020000 OK BRANCH=None BUG=b:114326670 Change-Id: I29298c2e5a897d08d21390c751bdd881170adb59 Signed-off-by: Yilun Lin <yllin@google.com> Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1385910 Reviewed-by: Erin Lo <erin.lo@mediatek.com> Reviewed-by: Rong Chang <rongchang@chromium.org>
* mt_scp/ipi: Fix typo in IPI macro check.Yilun Lin2019-01-181-1/+1
| | | | | | | | | | | | | TEST=make BOARD=kukui_scp -j BUG=None BRANCH=None Change-Id: I18cef1540fd3fe76269a16edab6c622084417c7e Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/1420248 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Pi-Hsun Shih <pihsun@chromium.org>
* mt_scp/ipi: Support host command.Yilun Lin2018-12-291-0/+72
| | | | | | | | | | | | | | | | | | | | | | | | | | | mt_scp is the first chip which uses IPI to do host command communication. This CL implements the host command over IPI. TEST=Run ec.RW.bin on kukui by "echo start > /sys/class/remoteproc/remoteproc0/state" and see that there are HC logs from SCP uart [0.000385 hostcmd init 0x0000000000002000] [0.049958 HC 0x0b] [0.050061 HC 0x400b] [0.050108 HC 0x400b err 1] [0.050204 HC 0x08] [0.050240 HC 0x08 err 3] [0.050370 HC 0x8d] [0.050406 HC 0x8d err 1] [0.050821 HC 0x0d] BUG=b:117917141, b:120953723 BRANCH=None Change-Id: I2c2b701d92504a74cc2ee90ab05912e99378acde Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/1379410 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* mt_scp: Support inter-process interrupt/communication (IPI).Yilun Lin2018-12-297-4/+368
| | | | | | | | | | | | | | | | | | This CL enables the IPI/IPC functions in mt_scp on MTK SOC. TEST=Run ec.RW.bin on kukui, and see EC version string in AP console: remoteproc remoteproc0: powering up scp remoteproc remoteproc0: Booting fw image scp.img, size 29800 mtk-scp 10500000.scp: scp is ready. kukui_scp_v2.0.519+164255084 BRANCH=None BUG=b:117917141, b:120172001, b:120953723 Change-Id: I2a43aee13141535bf71f839cf9e6cc0460b65844 Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/1351924 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* mt_scp: Support SCP reset stepping stone function.Yilun Lin2018-12-234-1/+28
| | | | | | | | | | | | | | | | | | | | SCP assumes vector table at CONFIG_RAM_BASE. However, on cortex-m resetting, it would load 0x0 to SP(r13) and load 0x04 to PC(r15). Stepping stones copy these two very special values from CONFIG_RAM_BASE, CONFIG_RAM_BASE + 0x04 to 0x0, 0x4 resepctively. TEST=make BOARD=kukui_scp -j, and see the value from 0x0, 0x4 in kukui_scp/RW/ec.RW.flat are the same as 0x800, 0x804 respectively. TEST=Puts ec.RW.bin on kukui and see that SCP boots. BUG=b:120825336 BRANCH=None Change-Id: I71670d5d4b5ba3aaad17c264a2a3bc3076703a9c Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/1373950 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* mt_scp/uart: Do not use usleep in tx_flush/write_charNicolas Boichat2018-12-231-3/+2
| | | | | | | | | | | | | | | These functions may be called in interrupt/exception context, especially when panic_printf is used. We need to busy-loop. BRANCH=none BUG=b:119929419 TEST=crash divzero works Change-Id: Ie97243afcc433226e78ea1b1225227c6ffbf2a04 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1373288 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Yilun Lin <yllin@chromium.org>
* mt_scp/hrtimer: Fix race condition in timer_read_raw_systemNicolas Boichat2018-12-231-2/+11
| | | | | | | | | | | | | | | | | | | When the 32-bit bit timer @26Mhz wraps around, there is a short amount of time when the 32-bit timer value (@1Mhz) is incorrect. Fix this by manually adjusting sys_high if an interrupt is pending. BRANCH=none BUG=b:120173036 BUG=b:120763595 TEST=Boot kukui_scp, leave it running for 200 seconds taskinfo "time in exceptions" look reasonable Change-Id: I053972d018e3e5e9c46cb73a0edb16b0354d5c43 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1372871 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Yilun Lin <yllin@chromium.org>
* kukui: Add initial kukui_scp board for SCP developmentRong Chang2018-12-201-2/+2
| | | | | | | | | | | | | | | | | | | Kukui is the first project with Chromium OS EC based SCP. This is an base board to develop SCP functionalities. BRANCH=none BUG=b:114326670 TEST=manual make BOARD=kukui_scp -j Change-Id: I65897d5439e88cebdc6543e5a8e07cd5657303e7 Signed-off-by: Rong Chang <rongchang@chromium.org> Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/1208772 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* scp: Add mt_scp chipRong Chang2018-12-2010-0/+1618
SCP is a Cortex-M4 based sensor hub in Mediatek SoC. This change adds the chip folder and system level drivers. BRANCH=none BUG=b:114326670 TEST=manual make BOARD=kukui_scp -j copy ec.bin to /lib/firmware/scp.img echo 'stop' > /sys/class/remoteproc/remoteproc0/state echo 'start' > /sys/class/remoteproc/remoteproc0/state check EC uart console Change-Id: I6629149f352184108fa520e80b59fd2ce94c76f7 Signed-off-by: Rong Chang <rongchang@chromium.org> Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/1208770 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
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