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* npcx: introduce npcx7m6fc chip definitions and configurationsCHLin2018-11-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | This CL includes: 1. add CHIP_VARIANT_NPCX7M6FC in the npcx chip configuration files to define what (RAM, features...) is supported in npcx7m6fc. 2. add the chip id and chip revision id of npcx7m6fc. BRANCH=none BUG=none TEST=No build errors for make buildall. TEST=Change CHIP_VARIANT to npcx7m6fc in board/npcx7_evb/build.mk; flash image in the internal testing board of npcx7m6fc; make sure the EC can boot up. Check the chip ID and chip revision ID are correct by console command "version". TEST=build and flash the yorp image to the platform; make sure no issues are found. Change-Id: Ibcb25fc09b21ec3e5738418af16826035ec81e69 Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/1343639 Commit-Ready: CH Lin <chlin56@nuvoton.com> Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* npcx: Decide erase size based on ro/rw region sizeFurquan Shaikh2018-09-051-0/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change updates the erase operation in npcx chip to use 64k/32k/4k block erase depending upon the alignment of CONFIG_RO_SIZE. This helps reduce the EC SW sync time from ~9.5 seconds to ~5.4 seconds on NPCX7. Ideally, we would want to check the offset and size of region to be erased dynamically and decide which erase operation to use. However, common flash code checks against CONFIG_FLASH_ERASE_SIZE to ensure that the area being erased is aligned to that size. Thus, even if we add dynamic erase at chip level, it isn't going to help. This change also updates CONFIG_FLASH_BANK_SIZE to be the same as CONFIG_FLASH_ERASE_SIZE since it is checked by common code. I am honestly not sure why the CONFIG_FLASH_BANK_SIZE is tightly coupled with CONFIG_FLASH_ERASE_SIZE. But, based on the usage, it seems to be a safe change. On the other hand, changing CONFIG_FLASH_BANK_SIZE helps reduce the write time as well, thus overall helping with the EC SW Sync time. Please see go/cros-npcx7-ec-sw-sync for more details. BUG=b:113530328 BRANCH=nocturne TEST=Verified that EC SW sync time goes down from 9.5 seconds to 5.4 seconds. Change-Id: I5908eeeb3e4207a27abe804db8eb9d39ef9d73c4 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1195598 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* npcx: change chip variants of npcx7 series for better clarification.Mulin Chao2018-04-271-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In this CL, we changed chip variants npcx7m6xb to npcx7m6fb and npcx7m7w to npcx7m7wb for better clafiication since it introduced new parameter "b" for chip generation in the same family series. In new npcx7 series naming rule, it follows: Format: NPCX7(M)(N)(G/K/F)(B/C) param M: 8: 128-pins package, 9: 144-pins package param N: 5: 128KB RAM Size, 6: 256KB RAM Size, 7: 384KB RAM Size param G/K/F/W: Google EC depends on specific features. param B/C: Chip generation in npcx7. (Generation A is ignored. It follows nameing rule in npcx5.) The all chip variants of npcx7 used in boards are also listed below: npcx7m6g - for npcx7 ec without internal flash on npcx_evb. npcx7m6f - for npcx7 ec with internal flash. npcx7m6fb - for npcx7 ec with internal flash, enhanced features. npcx7m7wb - for npcx7 ec with internal flash, enhanced features + WOV. BRANCH=none BUG=none TEST=No build errors for npcx7 series. Change-Id: I896ee33209efa5d7157c90515005db5f36318c76 Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/1025471 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* npcx7: Add definition/configuration for npcx7m6xb/npcx7m7wCHLin2018-01-171-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | In this CL, we add the following changes to support the CHIP_VARIANT npcx7m6xb and npcx7m7w: 1. Define the code RAM, data RAM, BBRAM base address/size. 2. Initialize the wov.c file for WoV driver development. (It will be compiled only when CHIP_VARIANT=npcx7m7w in the build.mk and CONFIG_WAKE_ON_VOICE is defined in board.h) 3. Fix the the incorrect offset of PWDWN_CTRL7 register. BRANCH=none BUG=none TEST=No build errors for make buildall. TEST=Change CHIP_VARIANT to npcx7m7w/npcx7m6xb in board/npcx7_evb/build.mk; "BOARD=npcx7_evb make"; Check ec image can be built. Flash the image on EVB; make sure EVB bootup. Change-Id: I87bccb9097f8f0a6c67f96a8d90adf201ae9e773 Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/858637 Commit-Ready: CH Lin <chlin56@nuvoton.com> Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* npcx: Add support for chip variant npcx7m6gCHLin2017-07-161-1/+1
| | | | | | | | | | | | | | | | | | | | | This CL adds CHIP_VARIANT_NPCX7M6G to support another npcx7 ec SKU. Please note that the default setting in npcx7_evb is npcx7m6f. For the EVB using the 128-pins EC package, please change CHIP_VARIANT from npcx7m6f to npcx7m6g in build.mk. BRANCH=none BUG=none TEST=No build errors for make buildall; Set CHIP_VARIANT=npcx7m6g in board/npcx7_evb/build.mk; Build the image and test on EVB. Change-Id: I2f857e4f6524eab45930bac3cc209409d4a53ee8 Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/569320 Commit-Ready: Jun Lin <riverq@gmail.com> Tested-by: Jun Lin <riverq@gmail.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
* rwsig: Fix mapped read location for rwsig / pubkeyShawn Nematbakhsh2017-06-211-5/+8
| | | | | | | | | | | | | | | | | | | | Mapped reads are relative to CONFIG_EC_*_STORAGE_OFF, not CONFIG_R*_MEM_OFF. The previous implementation happened to work for internal mapped storage (eg. stm32) but failed for external mapped storage which is copied to SRAM before execution (eg. npcx). BUG=b:62841029 TEST=Verify sysjump works again on eve/poppy/soraka. Verify sysjump and sig verification continues to work on fizz and stm32. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Id51ce5697555eea38b246b58dbf47f22d4befaa7 Reviewed-on: https://chromium-review.googlesource.com/541861 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* Fizz: Verify and jump to RW imageDaisuke Nojiri2017-06-191-1/+2
| | | | | | | | | | | BUG=b:37316498 BRANCH=none TEST=Boot Fizz Change-Id: Iaceb64bcf5d54145c26e86ce62a14d5732a22e78 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/517406 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* npcx: Introduce npcx7 series ec chip definitions and configurations.Mulin Chao2017-04-251-0/+5
| | | | | | | | | | | | | | | | | | | | | | | This CL includes: 1. Add CHIP_FAMILY_NPCX5/7 and CHIP_VARIANT_NPCX7M6F to distinguish which npcx's ec is used on the board. 2. Add config_chip-npcx5/7.h files and move features depend on chip family into them. 3. Add NPCX_INT_FLASH_SUPPORT, NPCX_PSL_MODE_SUPPORT and NPCX_EXT32K_OSC_SUPPORT to determine which features are supported on npcx7 ec. We'll use them later in gpio/system/flash drivers. 4. Add ram size checking for all npcx ec series. BRANCH=none BUG=none TEST=No build errors for all boards using npcx5 series (besides gru). Build poppy board and upload FW to platform. No issues found. Change-Id: Ia932996d01da71fea73ddd545255bdd59e581bcf Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/481560 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* kevin: Move RAM from data section to codeShawn Nematbakhsh2016-05-101-1/+1
| | | | | | | | | | | | | | | | | | Kevin is code space constrained, so use RAM normally used for data instead for code. BUG=chrome-os-partner:52876 BRANCH=None TEST=Verify free code RAM becomes 5732 bytes (was 1636) and free data RAM becomes 3072 bytes (was 7168 bytes) (measured with pending changes to add sensor task). Also, verify kevin continues to boot + power sequence. Change-Id: Ia6470a76f95e87d6cda1bf7273deaab6344f8ee9 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/343191 Commit-Ready: Wonjoon Lee <woojoo.lee@samsung.com> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* npcx: Add 256KB alignment of RO & RW regions for npcx5m6g.Mulin Chao2016-03-151-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Since npcx5m6g has larger than 128 KB code ram for FW, the original alignment between RO & RW regions isn't suitable for new chip. Therefore, we add 256KB alignment of them for npcx5m6g. In order to program the flash used by npcx5m6g, we add new board array, BOARDS_NPCX_5M6G_JTAG, in flash_ec to distinguish which flash layout ec used. In npcx_cmds.tcl, add new script funcs such as flash_npcx5m5g and flash_npcx5m6g to program flash with different layout. Modified sources: 1. config_flash_layout.h: Add 256KB alignment of RO & RW regions for npcx5m6g. 2. util/flash_ec: Add new board array, BOARDS_NPCX_5M6G_JTAG, to distinguish which flash layout ec used. 3. openocd/npcx_cmds.tcl: Add new script funcs to program flash with different layout. BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers BRANCH=none Change-Id: I0ace31d96d6df2c423b66d508d30cefb0b82ed6c Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/331903 Reviewed-by: Shawn N <shawnn@chromium.org>
* npcx: Add CHIP_VARIANT variant for different versions of npcx ec.Mulin Chao2016-03-051-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to support 256 KB ram version of npcx ec, we add CHIP_VARIANT variant to distinguish which verson ec is. In config_chip.h, we use CHIP_VARIANT to specify the size and start address of program memory. Ecst tool also needs a chip parameter to make sure the address range checking of entry pointer won't fail. Modified sources: 1. config_chip.h: Use CHIP_VARIANT to specify the different hardware spec of npcx ec. 2. config_flash_layout.h: Replace constant value with CONFIG_PROGRAM_MEMORY_SIZE for CONFIG_RO_SIZE. 3. build.mk: Add -chip parameter for ecst tool to check entry address. 4. npcx_evb\build.mk: Add CHIP_VARIANT definition (npcx5m5g). 5. npcx_evb_arm\build.mk: Add CHIP_VARIANT definition (npcx5m5g). 6. wheatley\build.mk: Add CHIP_VARIANT definition (npcx5m5g). BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers BRANCH=none Change-Id: I1b8b9b9d0a59bdc01210f498ac67e4a342743b47 Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/330072 Tested-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* nuc: Fixed wheatley bugs of SERIRQ and AC detection.Mulin Chao2015-11-111-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | SERIRQ bug: PMC1/2 share the same IRQ number 1 with default setting. Enable it will influence 8042 protocols since KBC has no data but IRQ 1 is issued by PMC. AC detection bug: GPIO definitions between AC_PRESENT and ACOK mismatched. AC_PRESENT will always be high even we don't plug the adaptor. Modified drivers: 1. lpc.c: Remove enabling SERIRQ for PMC1/2 and disable IRQ12 for Mouse. 2. config_flash_layout.h: Modified for adjusting RAM size. 3. gpio.inc: Modified GPIO definitions for AC issue 4. board.h: Modified for adjusting RAM size and add support for ACC 5. board.c: Add support for ACC and adjust ADC max value BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers BRANCH=none Change-Id: Ib330ef4078e4b06f1c01a2a6316e468b43d7a8d9 Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/311933 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* nuc: Remove unnecessary NPCX_EC_FLASH_SIZE definition in npcx.Mulin Chao2015-10-191-6/+0
| | | | | | | | | | | | | | | | | | | Remove NPCX_EC_FLASH_SIZE definition and replace it with CONFIG_FLASH_SIZE. Due to inconsistence between NPCX_EC_FLASH_SIZE and CONFIG_FLASH_SIZE, some flash commands such as flasherase will cause unexpected results. Modified drivers: 1. config_flash_layout.h: Remove NPCX_EC_FLASH_SIZE definition. 2. flash.c: Replace NPCX_EC_FLASH_SIZE with CONFIG_FLASH_SIZE. BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers BRANCH=none Change-Id: Idca286eef5bb014d5c4cd689c39635e09f40ee03 Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/307004 Reviewed-by: Shawn N <shawnn@chromium.org>
* cleanup: Remove CONFIG_FW_IMAGE_SIZEShawn Nematbakhsh2015-09-241-7/+2
| | | | | | | | | | | | | | | | | | Since CONFIG_RO_SIZE and CONFIG_RW_SIZE now exist (which may theoretically be different sizes), it is no longer useful to globally define the size of an image. BUG=chromium:535027 BRANCH=None TEST=`make buildall -j`. Also, verify glados / glados_pd continue to function as expected. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Ie29959923bc5d02b4d7d6d507ff2191bcb7d24c8 Reviewed-on: https://chromium-review.googlesource.com/301743 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* nuc: Fixed flash layout issue for npcxMulin Chao2015-09-211-4/+4
| | | | | | | | | | | | | | | | | | | | Fixed flash layout issue for npcx Modified drivers: 1. config_flash_layout.h: Fixed layout issue for npcx 2. flash_ec: add flashrom support for boards without JTAG in servo connector BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers BRANCH=none Change-Id: I0b9b679c52b8a8e2a26c278b5024d0350fb77338 Reviewed-on: https://chromium-review.googlesource.com/300392 Commit-Ready: Mulin Chao <mlchao@nuvoton.com> Tested-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* cleanup: Remove redundant FLASH_SIZE CONFIGsShawn Nematbakhsh2015-09-161-6/+11
| | | | | | | | | | | | | | | | | | | | Since there is no more concept of a flash region belonging only to the EC, we only need one FLASH_SIZE config, which represents the actual physical size of flash. BRANCH=None BUG=chrome-os-partner:23796 TEST=With entire patch series, on both Samus and Glados: - Verify 'version' EC console command is correct - Verify 'flashrom -p ec -r read.bin' reads back EC image - Verify software sync correctly flashes both EC and PD RW images Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I18a34a943e02c8a029f330f213a8634a2ca418b6 Reviewed-on: https://chromium-review.googlesource.com/297824 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cleanup: Change meaning of storage offset CONFIGsShawn Nematbakhsh2015-09-161-5/+10
| | | | | | | | | | | | | | | | | | | | | | | In order to support architectures with non-contiguous writable and protected regions, change storage offsets to be relative to writable and protected regions, rather than relative to "the start of the region of storage belonging to the EC". Spec doc available at https://goo.gl/fnzTvr. BRANCH=None BUG=chrome-os-partner:23796 TEST=With entire patch series, on both Samus and Glados: - Verify 'version' EC console command is correct - Verify 'flashrom -p ec -r read.bin' reads back EC image - Verify software sync correctly flashes both EC and PD RW images Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I796f8e7305a6336495bd256a78774595cb16a2e4 Reviewed-on: https://chromium-review.googlesource.com/297823 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cleanup: Remove CDRAM / CODERAM CONFIGsShawn Nematbakhsh2015-09-161-3/+3
| | | | | | | | | | | | | | | | | | | | | | | CDRAM / CODERAM configs were previously used for chips which copied code from external SPI to program memory prior to execution, and were used inconsistently between npcx and mec1322. These CONFIGs are now completely redundant given new configs like CONFIG_MAPPED_STORAGE_BASE and CONFIG_EXTERNAL_STORAGE. BRANCH=None BUG=chrome-os-partner:23796 TEST=With entire patch series, on both Samus and Glados: - Verify 'version' EC console command is correct - Verify 'flashrom -p ec -r read.bin' reads back EC image - Verify software sync correctly flashes both EC and PD RW images Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I0e054ab4c939f9dcf54abee8e5ebd9b2e42fe9c4 Reviewed-on: https://chromium-review.googlesource.com/297804 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cleanup: Rename geometry constantsShawn Nematbakhsh2015-09-161-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Rename and add geometry constants to match spec doc - https://goo.gl/fnzTvr. CONFIG_FLASH_BASE becomes CONFIG_PROGRAM_MEMORY_BASE CONFIG_FLASH_MAPPED becomes CONFIG_MAPPED_STORAGE Add CONFIG_INTERNAL_STORAGE, CONFIG_EXTERNAL_STORAGE and CONFIG_MAPPED_STORAGE_BASE where appropriate. This CL leaves chip/npcx in a broken state -- it's fixed in a follow-up CL. BRANCH=None BUG=chrome-os-partner:23796 TEST=With entire patch series, on both Samus and Glados: - Verify 'version' EC console command is correct - Verify 'flashrom -p ec -r read.bin' reads back EC image - Verify software sync correctly flashes both EC and PD RW images Change-Id: Idb3c4ed9f7f6edd0a6d49ad11753eba713e67a80 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/297484 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cleanup: Clarify use of flash layout CONFIGsShawn Nematbakhsh2015-09-021-0/+46
Based on feedback from programmers, it's not clear when config_std_internal_flash should be used, and when non-standard chip-specific layouts need to be defined. Add clarity here with the following changes: - Explain in-depth the one config that config_std_internal_flash should be used for. - Move non-standard chip-level flash layout CONFIGs to their own new chip-level file, config_flash_layout. All chips should either include config_std_internal_flash.h OR define their own layout in their own config_flash_layout. Functionally, this change is a NOP. BUG=chrome-os-partner:23796 TEST=`make buildall -j` BRANCH=None Change-Id: I6037b68db9048d90fa2a2da4c9c9e09d1143fa68 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/296527 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
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