| Commit message (Collapse) | Author | Age | Files | Lines |
|---|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
In the interest of making long-term branch maintenance incur as little
technical debt on us as possible, we should not maintain any files on
the branch we are not actually using.
This has the added effect of making it extremely clear when merging CLs
from the main branch when changes have the possibility to affect us.
The follow-on CL adds a convenience script to actually pull updates from
the main branch and generate a CL for the update.
BUG=b:204206272
BRANCH=ish
TEST=make BOARD=arcada_ish && make BOARD=drallion_ish
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I17e4694c38219b5a0823e0a3e55a28d1348f4b18
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3262038
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Tom Hughes <tomhughes@chromium.org>
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
The npcx eSPI driver only prints if eSPI_DEBUG is on. Without ESPI_DEBUG,
critical eSPI errors are hidden and it may not be obvious why the
system is failing. This change forces eSPI bus error messages to always
print.
This is inside of an interrupt_handler, so printing too much could
cause other interrupts to be missed. The error message is short and it
did not cause additional errors during testing. Since eSPI bus errors
are often fatal, this risk is acceptable.
BUG=None
TEST=Boot image with known eSPI errors, see error message
Boot with known good image, see no error message
Remove condition, boot good image, eSPI functions normally
BRANCH=None
Change-Id: Ic1431800560091001b73dafcd77362e061323c1a
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3111457
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Diana Z <dzigterman@chromium.org>
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
| |
This renames IS_SLAVE_CHAN_ENABLE to IS_PERIPHERAL_CHAN_ENABLE.
BRANCH=none
BUG=b:163885307
TEST=buildall and compare_build.sh pass
Change-Id: Iaab11a2485fdcde3992ecb457c204465acfdf732
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2938042
Reviewed-by: Harry Cutts <hcutts@chromium.org>
Commit-Queue: Harry Cutts <hcutts@chromium.org>
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
VW_PERIPHERAL_BTLD_STATUS_DONE
This replaces VW_SLAVE_BTLD_STATUS_DONE with
VW_PERIPHERAL_BTLD_STATUS_DONE.
BRANCH=none
BUG=b:163885307
TEST=buildall, compare_build.sh pass
Change-Id: I0b8c71fa7e590dc89357e22aafce0b67717af183
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2938041
Reviewed-by: Harry Cutts <hcutts@chromium.org>
Commit-Queue: Harry Cutts <hcutts@chromium.org>
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
| |
This updates some comments to be OSHWA friendly.
BRANCH=none
BUG=b:163885307
TEST=buildall and compare_build.sh pass
Change-Id: I9fdcf1a64febccb3622379ffb5f4e31efeb8bb12
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2938040
Reviewed-by: Harry Cutts <hcutts@chromium.org>
Commit-Queue: Harry Cutts <hcutts@chromium.org>
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Errata 2.22 requires that we disable the peripheral support while
enabling the peripheral channel. This workaround was only required for
NPCX5. This change removes the errata for NPCX7+. This workaround was
also racy. If the host read the capabilities before the PLTRST# interrupt
handler completed, then it might think that the device doesn't support
the peripheral channel.
BUG=b:188188172, b:188935533
BRANCH=none
TEST=Boot guybrush to the OS.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I38bc7016280ab99135b1a9af8c76e4cceebfb605
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2912927
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
The PLTRST# handler has a race condition. It sets the peripheral channel
ready bit before the IO ports are memory mapped. This means that the AP
can start sending IO requests before the mappings are ready.
BUG=b:188188172, b:188935533
BRANCH=none
TEST=On guybrush make an EC call after eSPI init. I no longer see a
failure. Also verify zork still boots.
Suggested-by: Rob Barnes <robbarnes@google.com>
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I09c58ef989b8bb90d7662afc63d23dc5498c293b
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2912090
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
It was observed that in byra, when the "apshutdown" console command is
executed, the power state of EC is messed up. This was caused by the
SLP_Sx virtual wire is not updated due to the ungraceful global reset.
This CL adds a config option to let npcx EC reset SLP_Sx VW when
eSPI_RST is asserted.
Note: don't enable this config if the platform implements deep Sx entry
(e.g. KBL) for the reason per Intel eSPI spec. (scenario 3 in Table 7):
These pins retain state (0 or 1) until PCH/SoC exits Deep-Sx and PMC
sends a VW message to the EC with the new states for these pins.
BRANCH=none
BUG=b:179977907
TEST=pass "make buildall"
TEST=With the config defined, see the SLP_S4 virtual wire reset when
eSPI_RST is asserted.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Change-Id: I413b3d211537295b32c49b6e4a1797e48a26ec5f
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2766428
Tested-by: CH Lin <chlin56@nuvoton.com>
Tested-by: caveh jalali <caveh@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Commit-Queue: caveh jalali <caveh@chromium.org>
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
1. Functions are supported in npcx7 but npcx5 are guarded by:
"#if defined(CHIP_FAMILY_NPCX7)."
In npcx9, most of these functions are inherited. Change the guard to:
"#if NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7"
2. Configure APB4DIV in clock.c
3. In npcx5/7, the host interface type (HIF_TYP_SEL in the
DEVCNT register) is updated by booter after VCC1 Power-Up reset
according to VHIF voltage. In npcx9, the booter will not do this
anymore. Set the HIF_TYP_SEL filed at initialization in lpc.c anyway
to cover to all chip family.
4. Configure power down registers appropriately.
5 add symbolic links:
i2c-npcx9.c -> i2c_npcx5.c
system-npcx9.c -> system-npcx7.c
BRANCH=none
BUG=b:165777478
TEST=pass "make buildall"
TEST=with related CLs, build and flash image on the npcx7/9 EVB and
yorp, no symptom occurs.
Signed-off-by: CHLin <CHLin56@nuvoton.com>
Change-Id: I17a71b7b90435d4a3ff75aac18bf2640b5b15515
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2402843
Commit-Queue: CH Lin <chlin56@nuvoton.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: caveh jalali <caveh@chromium.org>
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Split the configuration option CONFIG_HOSTCMD_ESPI_VW_SLP_SIGNALS into
separate options controlling SLP_S3 and SLP_S4. Allow volteer to
configure SLP_S3 as a GPIO and SLP_S4 as an eSPI virtual wire. Cause a
build error if virtual wires are configured, but eSPI is not.
BUG=b:139553375,b:143288478
TEST=make buildall
TEST=Build volteer with CONFIG_HOSTCMD_ESPI_VW_S4 defined but
CONFIG_HOSTCMD_ESPI undefined; observe build error
BRANCH=none
Change-Id: I8c6737e2ccb1a77a882e5fa65c6eddb342209b61
Signed-off-by: Abe Levkoy <alevkoy@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1881758
Reviewed-by: Keith Short <keithshort@chromium.org>
|
| |
|
|
|
|
|
|
|
|
|
|
| |
BUG=none
BRANCH=none
TEST=buildall
Change-Id: I7f9089ce8028f12a94d8e73dd58a5bb36ebc614f
Signed-off-by: Edward Hill <ecgh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1862090
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
Commit-Queue: Denis Brockus <dbrockus@chromium.org>
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
The source of the SLP_Sx power signals can come from only either GPIO
or virtual wire. The firmware now assumes that, when the GPIO is chosen,
(i.e. CONFIG_HOSTCMD_ESPI_VW_SLP_SIGNALS is not enabled.)
there should be no virtual wire SLP_Sx event is triggered.
However if the host accidentally sends a SLP_Sx VW to EC, EC will call
the power_singal_interrput(signal) by passing an invalid enum signal
number. (i.e. The index is of the range of GPIO table.)
It may cause the system problematic when the firmware uses the
enum signal number to access the GPIO table.
BUG=b:141730279
BRANCH=none
TEST=No error for "make buildall"
TEST=Test on trembyle, the crash symptom can be fixed.
Change-Id: I0fa606f812b377d6616e314ca1f1c9675a04e2a8
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1844658
Reviewed-by: Edward Hill <ecgh@chromium.org>
Commit-Queue: Edward Hill <ecgh@chromium.org>
Tested-by: Edward Hill <ecgh@chromium.org>
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
According to the datasheet, firmware should clear MIWU pending register
(WKPND) after configuring WKMOD/WKEDG/WKAED register and before
enabling WKEN register. Otherwise, the module might cause a false
wake-up or interrupt event.
BUG=b:141730279
BRANCH=none
TEST=No error for "make buildall"
TEST=Test on yorp, check the fake virtual wire events are no longer
generated and the system crash symptom is fixed when CONFIG_BRINGUP
is defined.
Change-Id: I89e055b4174419658cdd823f04acff41aa14cfe6
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1844660
Reviewed-by: Edward Hill <ecgh@chromium.org>
Commit-Queue: Edward Hill <ecgh@chromium.org>
Tested-by: Edward Hill <ecgh@chromium.org>
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Mechanical replacement of bit operation where operand is a constant.
More bit operation exist, but prone to errors.
Reveal a bug in npcx:
chip/npcx/system-npcx7.c:114:54: error: conversion from 'long unsigned int' to 'uint8_t' {aka 'volatile unsigned char'} changes value from '16777215' to '255' [-Werror=overflow]
BUG=None
BRANCH=None
TEST=None
Change-Id: I006614026143fa180702ac0d1cc2ceb1b3c6eeb0
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1518660
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Before this change uart_ec_interrupt and software watchdog
interrupt handler both had priority 0. Since UART IRQ number is
33, and software watchdog is 44, the UART interrupt handler
would have higher prority.
Fix this by increasing all interrupt handler priorities, leaving
the software watchdog handler alone on priority 0.
BRANCH=eve,poppy,fizz
BUG=b:76391320
TEST=Cherry-pick CL:979736 (causes a watchdog in UART interrupt
handler), check that panicinfo contains a sensible PC in r5
after reset.
Change-Id: I97f99af5192a4a9571854a4d3f7c48a4674d605e
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/979738
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
NPCX7 requires that the HW_WIRE bits 2-0 of VWEVSM2 register are set
so that the hardwire signals for SCI, SMI and RCIN are connected to VW
input of eSPI_SIF module. NPCX5 did this by default, however NPCX7 has
made it configurable.
NPCX7 however sets the HW_WIRE bits 2-0 to 1 at reset. So, this change
ensures that they are preserved while initializing VWEVSM2 registers
BUG=b:74111394
BRANCH=None
TEST=Verified that SCI works on glkrvp and meowth with NPCX7.
Change-Id: I9da6f45b4aa0b72b68db6192cb7567f09b072f0c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/943801
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Divya S Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: ML Chao <mlchao@nuvoton.corp-partner.google.com>
Reviewed-by: Jett Rink <jettrink@chromium.org>
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
the npcx7 can only run eSPI at (up to) 50MHz while the npcx5 can go up
to 66MHz. so, set the max speed to whatever the hardware can actually
do. the bit pattern for 66MHz is "reserved" on the npcx7, so let's
not even define it in the npcx7 case.
BUG=b:72838699, b:71859563
BRANCH=none
TEST="make buildall" passes; boots on meowth
Change-Id: I428caf72a41fe58008df4624c475dafadca4a0bc
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/910321
Commit-Ready: caveh jalali <caveh@chromium.org>
Tested-by: caveh jalali <caveh@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
This CL fixed the issue that ec cannot enter low power mode, which
increases more power consumption in s5, by not setting ESPIRSTWE bit.
For more detail, please see the npcx5's errata rev1_7, No.2.21.
BRANCH=none
BUG=b:69351155
TEST=No build errors for "make buildall".
TEST=build and flash soraka, run commands to read the power consumption:
dut-control pp3300_dsw_ec_cfg_reg:0x7327k
dut-control pp3300_dsw_ec_mw -t 20 | grep "@@"
the average power consumption measured reduces from 42.x to 10.x mw.
TEST=do cold reboot stress test for 4 hours and no symptom occurred.
Change-Id: Ic6fd7fe14ae8acaefd4e1a99ca1625254f67d708
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/778709
Commit-Ready: CH Lin <chlin56@nuvoton.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
According npcx ec wake-up mechanism by espi VW events, the driver
needs to make sure the IE/WE bits in VWEVMSn and the VWUPD bit in
ESPIWE registers are both set. Or ec won't wakeup by VW signals until
the other wake-up events occured. (WE bit of VWEVMSn is introduced on
npcx7.)
In this CL, we turn on IE/WE bit in VWEVMSn registers during espi driver
initialization and toggle the bits of ESPIWE register for VW and general
events such as ESPI_RST and so on when ec turn on/off host interface's
interrupts to make sure ec can wake-up from deep idle by espi events in
time.
BRANCH=none
BUG=none
TEST=No build errors for npcx5/7 series. Using "suspend_stress_test -c
1000" to do stress test and no symptom occurred on poppy. Both warmboot
and coldboot stress test for 5 hours and no symptom occurred on poppy.
Change-Id: I853532508bf9da5f3abc39e20ab848e659ca5e26
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/725559
Reviewed-by: Amit Maoz <amit.maoz@nuvoton.corp-partner.google.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
In npcx7, we introduced a new bit, VWUPDW, in ESPISTS register to
indicate a Master-to-Slave VW signal was updated and the relevant WE
bit is 1. But there's no relevant IE bit in ESPIIE for VWUPDW, old
mechanism for clearing pending bits of ESPISTS will ignore this bit.
And ec cannot enter deep sleep anymore since this bit is set. This CL
fixed this bug by setting bit 17 of mask variable if ec is npcx7 series.
BRANCH=none
BUG=none
TEST=No build errors for npcx5/7 series.
Change-Id: I80c57d3c230e9d06ba134538ccdcd29f290bb7bf
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/672183
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Amit Maoz <Amit.Maoz@nuvoton.com>
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
| |
Because m is unsigned, it can't be less than 0.
BUG=b:64477774
TEST=Build
Change-Id: Iec93f396be1f01bc1c38b3285b93daacff6a15db
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/606454
Commit-Ready: Martin Roth <martinroth@chromium.org>
Tested-by: Martin Roth <martinroth@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Because sig_idx was declared as uint8_t, if espi_vw_get_signal_index()
returned an error value of -1, it wouldn't get caught. This would
cause the arrays to access the wrong locations later.
BUG=b:64477774
TEST=Build
Change-Id: Ibe21d51c00ae3511a66a6976e18495c3f7683a78
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://chromium-review.googlesource.com/606453
Commit-Ready: Martin Roth <martinroth@chromium.org>
Tested-by: Martin Roth <martinroth@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
In case there is a sudden power loss to PCH, then there are no eSPI VW
messages sent from the PCH to EC indicating power state transition into
S5. Instead, the eSPI compatibility spec defines such events as global
reset events. For global reset events, eSPI_Reset# signal is asserted
without SLP_SUS# being asserted. This acts as an indication to the EC
that there was a global reset event.
Add a callback chipset_handle_espi_reset_assert that takes any necessary
action whenever eSPI_Reset# pin is asserted. On skylake, it would check
if power button was being pressed and release the button.
BUG=chrome-os-partner:62014
BRANCH=None
TEST=Verified that apshutdown works as expected.
Change-Id: I409afa0d00faca55ae3aa577743cedac58d4d877
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/438935
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Enable the chipset_reset_hook by adding interrupt trigger on
pltrst assertion and fix the compilation when built with
CONFIG_CHIPSET_RESET_HOOK enabled.
BUG=chrome-os-partner:58666
BRANCH=none
TEST=build with CONFIG_ESPI and CONFIG_CHIPSET_RESET_HOOK
Change-Id: I64eb7a1acc58c07beba0d28f94d95ef33d7220fb
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/400035
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Enable valid bits of SCI#/SMI# of eSPI's VW if there's no CONFIG_SCI_GPIO
definition in board-level driver. This CL also fixed the order of VW
event bits in comments.
Modified sources:
1. espi.c: Enable valid bits of SCI#/SMI#.
BRANCH=none
BUG=chrome-os-partner:34346
TEST=make all; test nuvoton IC specific drivers
Change-Id: I8d094513284b4ed42c5c26fe1975d71bbf050aa4
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/396618
Reviewed-by: Duncan Laurie <dlaurie@google.com>
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
During removing primary power of CPU, EC also needs to handle VW event
of SUS_WARN# in espi driver. Modify the MIWU trigger mode of it from
EDGE_RISING to EDGE_ANYING to solve it.
Modified sources:
1. espi.c: Handling VW event of SUS_WARN# in both edge.
BRANCH=none
BUG=chrome-os-partner:34346
TEST=make BOARD=wheatley; test power sequence on espi POC of wheatley.
Change-Id: I9e45115f3c274d08cdc694911d38599bc8da70c5
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/377780
Reviewed-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Since pretty much always, we've declared console commands to take
a "longhelp" argument with detailed explanations of what the
command does. But since almost as long, we've never actually used
that argument for anything - we just silently throw it away in
the macro. There's only one command (usbchargemode) that even
thinks it defines that argument.
We're never going to use this, let's just get rid of it.
BUG=none
BRANCH=none
CQ-DEPEND=CL:*279060
CQ-DEPEND=CL:*279158
CQ-DEPEND=CL:*279037
TEST=make buildall; tested on Cr50 hardware
Everything builds. Since we never used this arg anyway, there had
better not be any difference in the result.
Change-Id: Id3f71a53d02e3dc625cfcc12aa71ecb50e35eb9f
Signed-off-by: Bill Richardson <wfrichar@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/374163
Reviewed-by: Myles Watson <mylesgw@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
|
|
|
Add espi driver for x86-based platform which support espi interface such
as skylake and so on.
Added source:
1. espi.c: Add drivers which supports the utilities of peripheral and
virtual-wire channels so far.
2. espi.h: Add espi virtual-wire declaration for power sequence FW.
Modified sources:
1. lpc.c: Add interrupts and initialization steps for espi.
2. gpio.c: Add interrupt handler of espi reset.
BRANCH=none
BUG=chrome-os-partner:34346
TEST=make buildall -j; test nuvoton IC specific drivers
Change-Id: Ie80afe79d85aba47fc0b72898a8374c2898ec114
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/366181
Reviewed-by: Randall Spangler <rspangler@chromium.org>
|
