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* include/flash: rename the APIsTim Lin2021-06-091-28/+28
| | | | | | | | | | | | | | | | The names conflict when enabling both Zephyr's flash driver and CONFIG_FLASH_CROS option. Rename all the APIs in include/flash.h BUG=b:187192628 BRANCH=none TEST=make buildall -j4 Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com> Change-Id: If1fd0ea28fa9f5cec1c1daa8f72f63eb7a0e6500 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2931749 Commit-Queue: Keith Short <keithshort@chromium.org> Reviewed-by: Keith Short <keithshort@chromium.org> Reviewed-by: Denis Brockus <dbrockus@chromium.org>
* Refactor CONFIG_FLASH_SIZE to CONFIG_FLASH_SIZE_BYTESYuval Peress2021-01-151-3/+3
| | | | | | | | | | | | | | | | | | | | | In Zephyr CONFIG_FLASH_SIZE is a Kconfig value that is used throughout. The issue is that the units don't match. In Zephyr the value is in KiB instead of bytes. This refactor simply renames CONFIG_FLASH_SIZE in platform/ec to include the unit (via _BYTES). BRANCH=none BUG=b:174873770 TEST=make buildall be generated by the build instead of per board Signed-off-by: Yuval Peress <peress@chromium.org> Change-Id: I44bf3c7a20fcf62aaa9ae15715be78db4210f384 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2627638 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Hughes <tomhughes@chromium.org> Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
* task: Change mutex_lock() assertEdward Hill2020-08-151-4/+0
| | | | | | | | | | | | | | | | | | | Instead of asserting that task_start() has not been called, just return without doing any locking. This avoids the need to fix every caller of mutex_lock() to check task_start_called(). BUG=b:164461158 BRANCH=none TEST=Esc+F3+Power enters recovery, does not assert. Signed-off-by: Edward Hill <ecgh@chromium.org> Change-Id: Ic157d7e7041185a67f257f0f5710fd02e45cd77f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2357496 Reviewed-by: Wai-Hong Tam <waihong@google.com> Tested-by: Wai-Hong Tam <waihong@google.com> Commit-Queue: Wai-Hong Tam <waihong@google.com>
* task: Fix mutex_lock() assert (reland)Edward Hill2020-08-121-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | mutex_lock() must not be used in interrupt context. Add an assert to catch this. Also assert task_start_called() since task ID is not valid before this. Also remove an old assert since comparing id with TASK_ID_INVALID doesn't make sense. Add check for task_start_called() for NPCX flash_lock, I2C port_mutex, pwr_5v_ctl_mtx, STM32 bkpdata_write_mutex. This was submitted CL:2309057, reverted CL:2323704, submitted CL:2335738, reverted CL:2341706. BUG=b:160975910 BRANCH=none TEST=boot AP, jump to RW Signed-off-by: Edward Hill <ecgh@chromium.org> Change-Id: I0aadf29d073f0d3d798432099bd024a058332412 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2343450 Reviewed-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Denis Brockus <dbrockus@chromium.org>
* Revert "task: Fix mutex_lock() assert (reland)"caveh jalali2020-08-071-9/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 8d46141f4d45c65712a9ca7509b7b60128fa4d89. Reason for revert: getting EC boot loop on volteer: (note that you have to flash EC-RO to get this) 20-08-07 00:22:33.520 --- UART initialized after reboot --- 20-08-07 00:22:33.531 [Image: RO, volteer_1.1.9999-4284ce1 @caveh] 20-08-07 00:22:33.531 [Reset cause: reset-pin] 20-08-07 00:22:33.531 [0.005149 KB boot key mask 0] 20-08-07 00:22:33.543 [0.005438 init buttons] 20-08-07 00:22:33.543 [0.005669 VB Main] 20-08-07 00:22:33.543 [0.005872 VB Ping Cr50] 20-08-07 00:22:33.543 [0.007148 hash start 0x00040000 0x0002f61c] 20-08-07 00:22:33.833 [0.300169 hash done e4ddc3d0ffd015db085389d94faa38d3922e42290b6887baa8de3067ce846c13] 20-08-07 00:22:33.833 [0.300289 VB Verifying hash] 20-08-07 00:22:33.833 ��������������������������������EC\0 \0 �������S��O�8Ӓ.B) h����0g΄l[0.317577 VB Received 0xec00] 20-08-07 00:22:33.850 [0.317899 Jumping to image RW] 20-08-07 00:22:33.850 20-08-07 00:22:33.850 ASSERTION FAILURE '!in_interrupt_context() && task_start_called()' in mutex_lock() at core/cortex-m/task.c:868 20-08-07 00:22:33.861 20-08-07 00:22:33.861 === HANDLER EXCEPTION: 00 ====== xPSR: 0000000a === 20-08-07 00:22:33.861 r0 :00000364 r1 :100b6815 r2 :100b72ab r3 :100956bd 20-08-07 00:22:33.873 r4 :dead6663 r5 :00000364 r6 :200c1c20 r7 :00000001 20-08-07 00:22:33.873 r8 :00001388 r9 :100b4108 r10:100b4158 r11:00000013 20-08-07 00:22:33.884 r12:10095811 sp :200c0320 lr :200c1c20 pc :200c14f8 20-08-07 00:22:33.884 20-08-07 00:22:33.884 cfsr = 0, shcsr = 70000, hfsr = 0, dfsr = 0 20-08-07 00:22:33.884 20-08-07 00:22:33.884 =========== Process Stack Contents =========== 20-08-07 00:22:33.889 00000000: 100cfc00 00002a3d 00002751 00002731 20-08-07 00:22:33.901 00000010: 00002741 00002711 000027e1 00002791 20-08-07 00:22:33.901 00000020: 000027a1 000027b1 00002771 000027c1 20-08-07 00:22:33.901 00000030: 00002721 00002781 00002761 000027d1 20-08-07 00:22:33.906 20-08-07 00:22:33.906 Rebooting... 20-08-07 00:22:33.996 20-08-07 00:22:33.996 20-08-07 00:22:33.996 --- UART initialized after reboot --- Original change's description: > task: Fix mutex_lock() assert (reland) > > mutex_lock() must not be used in interrupt context. Add an assert > to catch this. > > Also assert task_start_called() since task ID is not valid > before this. > > Also remove an old assert since comparing id with TASK_ID_INVALID > doesn't make sense. > > This was first submitted as CL:2309057, then reverted by CL:2323704 > because it broke jump to RW (b/162302011). Fix this by adding check > for task_start_called() to chip/npcx/flash.c and common/i2c_master.c. > > BUG=b:160975910 > BRANCH=none > TEST=boot AP, jump to RW > > Signed-off-by: Edward Hill <ecgh@chromium.org> > Change-Id: I070a265a95d2128643b536814e608509d81adbe3 > Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2335738 > Reviewed-by: Raul E Rangel <rrangel@chromium.org> > Reviewed-by: Denis Brockus <dbrockus@chromium.org> Bug: b:160975910 Change-Id: I9e37b1eac7344cddbd756fb45b130d7e0aee661b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2341706 Reviewed-by: caveh jalali <caveh@chromium.org> Commit-Queue: caveh jalali <caveh@chromium.org> Tested-by: caveh jalali <caveh@chromium.org>
* task: Fix mutex_lock() assert (reland)Edward Hill2020-08-061-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | | mutex_lock() must not be used in interrupt context. Add an assert to catch this. Also assert task_start_called() since task ID is not valid before this. Also remove an old assert since comparing id with TASK_ID_INVALID doesn't make sense. This was first submitted as CL:2309057, then reverted by CL:2323704 because it broke jump to RW (b/162302011). Fix this by adding check for task_start_called() to chip/npcx/flash.c and common/i2c_master.c. BUG=b:160975910 BRANCH=none TEST=boot AP, jump to RW Signed-off-by: Edward Hill <ecgh@chromium.org> Change-Id: I070a265a95d2128643b536814e608509d81adbe3 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2335738 Reviewed-by: Raul E Rangel <rrangel@chromium.org> Reviewed-by: Denis Brockus <dbrockus@chromium.org>
* npcx: Add support for CONFIG_WP_ACTIVE_HIGHAseda Aboagye2020-01-031-0/+12
| | | | | | | | | | | | | | | | | NPCX was missing support for an inverted write protect polarity, this commit simply adds that support. BUG=b:146172102 BRANCH=None TEST=`make -j buildall` Change-Id: I3324d7f7cfa268a2d55f87d3b1943717e26c856c Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1986311 Tested-by: Aseda Aboagye <aaboagye@chromium.org> Auto-Submit: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Diana Z <dzigterman@chromium.org>
* host_command: Change host command return value to enum ec_statusTom Hughes2019-10-021-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the host command handler callback function returns an int, it's easy to accidentally mix up the enum ec_error_list and enum ec_status types. The host commands always expect an enum ec_status type, so we change the return value to be of that explicit type. Compilation will then fail if you accidentally try to return an enum ec_error_list value. Ran the following commands and then manually fixed up a few remaining instances that were not caught: git grep --name-only 'static int .*(struct host_cmd_handler_args \*args)' |\ xargs sed -i 's#static int \(.*\)(struct host_cmd_handler_args \*args)#\ static enum ec_status \1(struct host_cmd_handler_args \*args)##' git grep --name-only 'int .*(struct host_cmd_handler_args \*args)' |\ xargs sed -i 's#int \(.*\)(struct host_cmd_handler_args \*args)#\ enum ec_status \1(struct host_cmd_handler_args \*args)##' BRANCH=none BUG=chromium:1004831 TEST=make buildall -j Cq-Depend: chrome-internal:1872675 Change-Id: Id93df9387ac53d016a1594dba86c6642babbfd1e Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1816865 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* LICENSE: remove unnecessary (c) after CopyrightTom Hughes2019-06-191-1/+1
| | | | | | | | | | | | | | | | Ran the following command: git grep -l 'Copyright (c)' | \ xargs sed -i 's/Copyright (c)/Copyright/g' BRANCH=none BUG=none TEST=make buildall -j Change-Id: I6cc4a0f7e8b30d5b5f97d53c031c299f3e164ca7 Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1663262 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* npcx: Check WP_IF for internal flash before writing status registerFurquan Shaikh2018-09-271-1/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In case of internal flash, WP_IF needs to be checked to determine if it is okay to write status register. WP_IF is R/W1S, hence once it is set, it gets cleared only on core domain reset. Thus, it is necessary to reboot EC on WP de-assertion before any attempt to write status register is made. This change checks to ensure that internal flash is not protected based on the state of WP_IF bit in DEV_CTL4 before writing status register. BUG=b:115983409 BRANCH=None TEST=Verified following: 1. Attempt to write status register without rebooting EC: a. Disable WP b. flashrom -p ec --wp-disable ---> Reports failure back to host 2. Attempt to write status register after rebooting EC: a. Disable WP b. Reboot EC c. flashrom -p ec --wp-disable ---> Reports success and SW WP is successfully disabled. Change-Id: I2a89ecfc0bed824d5e75110f00b060980627dd33 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1248481 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Sanna Fnu <fnu.sanna@intel.corp-partner.google.com> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
* npcx: Change sleep in flash_wait_ready to 10usecFurquan Shaikh2018-09-071-15/+14
| | | | | | | | | | | | | | | | | | | | | | | flash_wait_ready had a sleep of 1 msec to check for busy bit status. This is too long of a wait for flash chip operation to complete and hence adds unnecessary delay during flash write. Changing the delay to 10usec helps cut the flash write time by 50%. This change reduces the delay to check busy bit to 10usec and also organizes the code slightly differently to use timestamp_expired() instead of decrementing timeout and checking it against 0. BUG=b:113530328 BRANCH=nocturne,grunt TEST=Verified that EC SW sync time is down to 3.4 seconds with this change. Change-Id: I5796ac3c493031c9623a9e5171ce9c5a7087089e Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1213553 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* npcx: Decide erase size based on ro/rw region sizeFurquan Shaikh2018-09-051-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change updates the erase operation in npcx chip to use 64k/32k/4k block erase depending upon the alignment of CONFIG_RO_SIZE. This helps reduce the EC SW sync time from ~9.5 seconds to ~5.4 seconds on NPCX7. Ideally, we would want to check the offset and size of region to be erased dynamically and decide which erase operation to use. However, common flash code checks against CONFIG_FLASH_ERASE_SIZE to ensure that the area being erased is aligned to that size. Thus, even if we add dynamic erase at chip level, it isn't going to help. This change also updates CONFIG_FLASH_BANK_SIZE to be the same as CONFIG_FLASH_ERASE_SIZE since it is checked by common code. I am honestly not sure why the CONFIG_FLASH_BANK_SIZE is tightly coupled with CONFIG_FLASH_ERASE_SIZE. But, based on the usage, it seems to be a safe change. On the other hand, changing CONFIG_FLASH_BANK_SIZE helps reduce the write time as well, thus overall helping with the EC SW Sync time. Please see go/cros-npcx7-ec-sw-sync for more details. BUG=b:113530328 BRANCH=nocturne TEST=Verified that EC SW sync time goes down from 9.5 seconds to 5.4 seconds. Change-Id: I5908eeeb3e4207a27abe804db8eb9d39ef9d73c4 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1195598 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* npcx: don't clear DEVCNT_F_SPI_TRIS bit for chips that use intenal flashCHLin2018-08-261-1/+1
| | | | | | | | | | | | | | | | | | As documented in the datasheet, NPCX_DEVCNT_F_SPI_TRIS must be 1 for ECs that use internal flash (e.g., NPCX79nF and NPCX797W). BRANCH=none BUG=b:112906111 TEST=No build errors for make buildall. Flash image on npcx7_evb; check this bit is not cleared. Flash image on yorp; check the platform boots up to OS screen. Change-Id: I533553ad91ce0ecc79fc55b86aa83bbbcf514d89 Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/1188180 Commit-Ready: CH Lin <chlin56@nuvoton.com> Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Wai-Hong Tam <waihong@google.com>
* chip/npcx: Add command to dump flash chip infoFurquan Shaikh2018-07-271-2/+19
| | | | | | | | | | | | | | | | | | This change adds a command to dump flash chip info like status register values and jedec ID. This is very useful when debugging flash chip related issues. BUG=b:111735126 BRANCH=None TEST=None Change-Id: I12fdaf9b740493f59df3357be12d4a2f4f1c98ff Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/1152697 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* Shuffle const aroundPatrick Georgi2018-05-181-1/+1
| | | | | | | | | | | | | | | | | | | | gcc 8.1 complains about duplicate const, and while some of these really are duplicate, others look like they were supposed to tighten the API contract so that variables are "const pointer to const data", but didn't have that effect. BUG=b:65441143 BRANCH=none TEST=building Chrome EC as part of upstream coreboot's build with a gcc 8.1 compiler now works (better. there are other issues left) Change-Id: I6016c5f282516471746f08d5714ea07ebdd10331 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://chromium-review.googlesource.com/1039812 Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Tested-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* console: Fix help for parse_boolEdward Hill2018-03-161-2/+2
| | | | | | | | | | | | | | | A few commands had help text of "[0 | 1]" but parse_bool() doesn't recognize 0 and 1. Change help text to "[on | off]", matching other commands. BUG=b:75302458 BRANCH=none TEST=none Change-Id: I9b1e4a70e024d17ec8bccc015069e31d7fff08ca Signed-off-by: Edward Hill <ecgh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/967248 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* npcx/flash: not enable the flash pinmux when using internal flashCHLin2017-10-151-0/+4
| | | | | | | | | | | | | | | | | | | | | | In npcx5, the flash interface pinmux should be turned on in order to access the external flash. However, in npcx7, the internal flash is used. It is meaningless to turn the pinmux on. And it also causes the alternative function of these pins not work normally(such as GPIOA0/GPIOA2) if the pinmux is enabled. This CL uses the preprocessor flag NPCX_INT_FLASH_SUPPORT to conditionally prohibit the execution of flash pinmux code. BRANCH=none BUG=none TEST=No build errors for "make buildall". Build npcx_evb and npcx7_evb boards, make sure the pinmux are correctly configured seperately. Change-Id: Iba2300159f204b65d15852ec1755714df0c64816 Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/704316 Commit-Ready: CH Lin <chlin56@nuvoton.com> Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* npcx: Don't enable CONFIG_CMD_FLASH_TRISTATE when internal flash is usedCHLin2017-08-231-0/+3
| | | | | | | | | | | | | | | | | | | The bit controlling the tri-state of FIU pins is reserved when the internal flash is used and should not be modified. This CL adds a compiler error to prevent this kind of misuse. BRANCH=none BUG=none TEST=No build errors for "make buildall". "BORAD=npcx7_evb make" with CONFIG_CMD_FLASH_TRISTATE defined, make sure the error message is printed. Change-Id: I020c8ab9e02b9a377879bbd2a337943e77a369d6 Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/624828 Commit-Ready: CH Lin <chlin56@nuvoton.com> Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* npcx: flash: Add write-protect support for internal flash of npcx7 ecstabilize-9554.BMulin Chao2017-05-121-0/+36
| | | | | | | | | | | | | | | | | | | | | | | | | In order to support write-protect mechanism for the internal flash of npcx7 ec, WP_IF, bit 5 of DEV_CTL4, is used to achieve this by controlling the WP_L pin of internal flash. During ec initialization or any utilities related to access status registers, we'll protect them if WP_L is active. Please notice the type of WP_IF is R/W1S. It means we only can unlock write protection of internal flash by rebooting ec. This CL also includes: 1. Add protect_range array of npcx7's internal flash (W25Q80) for write-protect mechanism. 2. Add bypass of bit 7 of DEVCNT. BRANCH=none BUG=none TEST=No build errors for all boards using npcx5 series. (Besides gru) Build poppy board and upload FW to platform. No issues found. Passed flash write-protect checking on npcx796f evb. Change-Id: I0e669ce8b6eaebd85e062c6751e1f3dd809e21e2 Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/501727 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* npcx: flash: Lock all flash access before flash_execute_cmd() callsShawn Nematbakhsh2017-03-011-2/+39
| | | | | | | | | | | | | | | | | | Any call to flash_execute_cmd() can interfere with UMA / mapped read access, so grab the mutex first. BUG=b:35587287,b:35848370 BRANCH=reef TEST=Verify SW sync completes 8 hour stress test on kevin. Also verify 'ectool flashspiinfo' succeeds. Change-Id: Ib1b04371546c27517c1b1ac860e9afbc1fed435e Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/447905 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* kevin / gru: Reduce SRAM footprintShawn Nematbakhsh2017-02-131-17/+18
| | | | | | | | | | | | | | | Remove console commands and add CONFIG options to reduce RAM usage. BUG=chrome-os-partner:54099 BRANCH=gru TEST=Verify charge_ramp CONFIG + task builds for gru. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I2d7bc77d1fc032c6cb75eb1ec8d13dacb676658d Reviewed-on: https://chromium-review.googlesource.com/437662 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* flash: Pass more precise parameter to flash_[physical_]protect_at_bootNicolas Boichat2017-02-121-20/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In preparation for adding the rollback protection block, pass EC_FLASH_PROTECT_RO/ALL_AT_BOOT to flash_[physical_]protect_at_boot, instead of an enumeration no protection/RO/ALL. This will later allow us to protect/unprotect the rollback region only, by adding a EC_FLASH_PROTECT_ROLLBACK_AT_BOOT flag. BRANCH=none BUG=chrome-os-partner:61671 TEST=Build hammer with CONFIG_CMD_FLASH command, so that write protection can be checked with flasherase/flashwrite. TEST=On hammer (stm32f072): flashinfo => RO+RW not protected flashwp true; reboot => only RO protected flashwp rw; reboot => RO+RW protected flashwp norw; reboot => only RO protected TEST=On reef (npcx): deassert WP, flashwp false; flashinfo => RO+RW not protected flashwp true => only RO protected reboot => only RO protected flashwp rw => RO+RW protected reboot => only RO protected Change-Id: Iec96a7377baabc9100fc59de0a31505095a3499f Reviewed-on: https://chromium-review.googlesource.com/430518 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* npcx: flash: Set SRP0 when enabling RO write protectionShawn Nematbakhsh2016-12-011-3/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | HW protection can be overridden unless SRP0 is set with WP asserted. BUG=chrome-os-partner:60029 BRANCH=gru TEST=Manual on kevin, deassert WP: > flashrom -p ec --wp-enable > flashrom -p ec --wp-disable SUCCESS assert WP: > flashrom -p ec --wp-enable > flashrom -p ec --wp-disable FAILED: RO_AT_BOOT is not clear. Change-Id: I67c1ec086704cd5be4518b6dc3dc87146cbd2d99 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/415465 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> (cherry picked from commit 3025b40df5c7744dde44336cc11f520667a92268) Reviewed-on: https://chromium-review.googlesource.com/415499 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* npcx: flash: Use common code for SPI flash protect reg translationShawn Nematbakhsh2016-12-011-156/+5
| | | | | | | | | | | | | | | | | | | | | | Common code is more flexible and supports more parts, so delete the npcx-only register translation code. BUG=chrome-os-partner:60029 BRANCH=gru TEST=Manual on gru, run 'flashrom -p ec --wp-enable' and check that 0x28 gets written to SR1, which matches our desired 'protect botton 128KB', according to the datasheet. Also run 'flashrom -p ec --erase' then read back EC SPI contents, verify ROM is erased except for first 128KB region. Change-Id: I526401997ff7ec77f2a6047a4a9af74a671ed69a Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/413228 Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 43634d36d273887b1f2349c333a7b4b229a83365) Reviewed-on: https://chromium-review.googlesource.com/415498 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org>
* npcx: flash: Fix SR reg reads during UMA lockShawn Nematbakhsh2016-12-011-33/+53
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If UMA is locked, read and write access to SR* regs will fail, and we'll be unable to determine or change our write protect state. Save our SR regs before enabling UMA lock, and bring down UMA lock for a brief period when writing SR regs. BUG=chrome-os-partner:60029 BRANCH=gru TEST=Manual on kevin with SW sync enabled. flashrom -p ec --wp-enable -> verify success, check flags: Flags: wp_gpio_asserted ro_at_boot ro_now Reboot host, check flags: Flags: wp_gpio_asserted ro_at_boot ro_now all_now Verify flashrom -p ec --wp-status shows protected, and flashrom -p ec --wp-disable fails. Also verify same state after EC reset. Boot into recovery mode, check flags: Flags: wp_gpio_asserted ro_at_boot ro_now Remove WP screw, reboot EC, check flags: Flags: ro_at_boot ro_now Verify flashrom WP status shows protected, and flashrom WP disable succeeds and clears all flags. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I17e32f7305600183e7fcb87f69a3feb88978f94e Reviewed-on: https://chromium-review.googlesource.com/412977 (cherry picked from commit 6cfc0d0dd030b8b0334f99e99950a52fcf8267af) Reviewed-on: https://chromium-review.googlesource.com/415497 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* flash: Add command to get SPI flash chip infoRandall Spangler2016-09-231-0/+59
| | | | | | | | | | | | | | | | | | | Previously, there was no way to identify which flash chip was used by the EC, for ECs using an external SPI flash. Now, 'ectool flashinfo' will print more information about the SPI flash chip in these cases. BUG=chrome-os-partner:56765 BRANCH=any EC with MEC1322 or NPCX still going through factory TEST=define CONFIG_HOSTCMD_FLASH_SPI_INFO, then 'ectool flashspiinfo' on samus indicates no SPI flash info, and prints additional info on chell and kevin. Without the config defined, all platforms report no spi flash info. CQ-DEPEND=CL:386368 Change-Id: I3c162f7ad12ed4b30ab951c03f24476683382114 Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/385702 Reviewed-by: Shawn N <shawnn@chromium.org>
* npcx: flash: Lock mutex during flash operationsMulin Chao2016-09-161-102/+59
| | | | | | | | | | | | | | | | | | | Lock mutex during mapped flash read and when issuing flash commands to ensure no conflict between tasks. BUG=chrome-os-partner:55781 BRANCH=Gru TEST=Stress test flashrom, verify no verify failure occurs for 100 flashes. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I6036754dd4d84c45cd689ce5033d68c655431b14 Reviewed-on: https://chromium-review.googlesource.com/386419 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> (cherry picked from commit 9123cc86c9fb15d8b9fbdcd4a93a785b37381fbe) Reviewed-on: https://chromium-review.googlesource.com/386448 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* flash: Call lock function prior to mapped external readShawn Nematbakhsh2016-09-161-0/+7
| | | | | | | | | | | | | | | | | | | | | | | Mapped read access to external flash may conflict with direct access through SPI commands, so call a chip-level function to lock access prior to doing such reads. BUG=chrome-os-partner:55781 BRANCH=Gru TEST=Verify 'ver' still works fine on kevin, and vboot hashing completes successfully. Change-Id: I009d6d5ee61c83260fb49ad4ee137fa3f4cd625a Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/385165 Tested-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com> (cherry picked from commit a7f3e3fa376731709f4823a0c1d464b4d1deae14) Reviewed-on: https://chromium-review.googlesource.com/386446 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* cleanup: DECLARE_CONSOLE_COMMAND only needs 4 argsBill Richardson2016-08-241-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Since pretty much always, we've declared console commands to take a "longhelp" argument with detailed explanations of what the command does. But since almost as long, we've never actually used that argument for anything - we just silently throw it away in the macro. There's only one command (usbchargemode) that even thinks it defines that argument. We're never going to use this, let's just get rid of it. BUG=none BRANCH=none CQ-DEPEND=CL:*279060 CQ-DEPEND=CL:*279158 CQ-DEPEND=CL:*279037 TEST=make buildall; tested on Cr50 hardware Everything builds. Since we never used this arg anyway, there had better not be any difference in the result. Change-Id: Id3f71a53d02e3dc625cfcc12aa71ecb50e35eb9f Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/374163 Reviewed-by: Myles Watson <mylesgw@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* npcx/flash.c: Init return value for successMartin Roth2016-08-231-1/+1
| | | | | | | | | | | | | | | | | In flash_physical_erase(), if the area being erased was already cleared, the return value would never be set, and would be returned without being defined. Initialize the value so that if the area being erased is clear, we return success. TEST=Build BUG=None BRANCH=None Change-Id: Ib13e0be0ad1d3ad23c065b407c35e7b5c4db8487 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/371399 Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
* npcx/flash: Don't print uninitialized valuesMartin Roth2016-08-121-2/+3
| | | | | | | | | | | | | | | | In command_flash_spi_sel_lock(), and command_flash_tristate() a value could be printed without being initialized first. Only display the values in the paths where the variable gets read. BUG=None TEST=Build and boot Reef BRANCH=None Change-Id: I8ef86f966d017290491d6fe2b1486ce913cd09fb Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/368301 Reviewed-by: David Hendricks <dhendrix@chromium.org>
* shorten long console command namesVadim Bendebury2016-05-181-1/+1
| | | | | | | | | | | | | | | | | | | The EC code expects console commands to be no longer than 14 characters, otherwise the alignment of the help command output breaks. This patch replaces flash_spi_sel_lock with flash_spi_lock and fake_disconnect with fakedisconnect to make sure the command names fit. BRANCH=none BUG=none TEST=the 'help' command output is not misaligned any more Change-Id: Ia65f1535850a07adccbef0812c8a0922c0264cea Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/345570 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
* nuc: Remove unnecessary NPCX_EC_FLASH_SIZE definition in npcx.Mulin Chao2015-10-191-12/+11
| | | | | | | | | | | | | | | | | | | Remove NPCX_EC_FLASH_SIZE definition and replace it with CONFIG_FLASH_SIZE. Due to inconsistence between NPCX_EC_FLASH_SIZE and CONFIG_FLASH_SIZE, some flash commands such as flasherase will cause unexpected results. Modified drivers: 1. config_flash_layout.h: Remove NPCX_EC_FLASH_SIZE definition. 2. flash.c: Replace NPCX_EC_FLASH_SIZE with CONFIG_FLASH_SIZE. BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers BRANCH=none Change-Id: Idca286eef5bb014d5c4cd689c39635e09f40ee03 Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/307004 Reviewed-by: Shawn N <shawnn@chromium.org>
* common: Add __fls functionGwendal Grignou2015-09-211-1/+1
| | | | | | | | | | | | | | | Returns the most significant bit set. Replace 31 - __builtin_clz(x), so x must be different from 0. Use get_next_bit when not on the performance path, on performance path set the bit field just after reading it. BRANCH=smaug BUG=none TEST=compile, check Ryu still works. Change-Id: Ie1a4cda4188f45b4bf92d0549d5c8fb401a30e5d Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/301300
* cleanup: Remove redundant FLASH_SIZE CONFIGsShawn Nematbakhsh2015-09-161-11/+11
| | | | | | | | | | | | | | | | | | | | Since there is no more concept of a flash region belonging only to the EC, we only need one FLASH_SIZE config, which represents the actual physical size of flash. BRANCH=None BUG=chrome-os-partner:23796 TEST=With entire patch series, on both Samus and Glados: - Verify 'version' EC console command is correct - Verify 'flashrom -p ec -r read.bin' reads back EC image - Verify software sync correctly flashes both EC and PD RW images Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I18a34a943e02c8a029f330f213a8634a2ca418b6 Reviewed-on: https://chromium-review.googlesource.com/297824 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* cleanup: Remove CDRAM / CODERAM CONFIGsShawn Nematbakhsh2015-09-161-2/+2
| | | | | | | | | | | | | | | | | | | | | | | CDRAM / CODERAM configs were previously used for chips which copied code from external SPI to program memory prior to execution, and were used inconsistently between npcx and mec1322. These CONFIGs are now completely redundant given new configs like CONFIG_MAPPED_STORAGE_BASE and CONFIG_EXTERNAL_STORAGE. BRANCH=None BUG=chrome-os-partner:23796 TEST=With entire patch series, on both Samus and Glados: - Verify 'version' EC console command is correct - Verify 'flashrom -p ec -r read.bin' reads back EC image - Verify software sync correctly flashes both EC and PD RW images Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I0e054ab4c939f9dcf54abee8e5ebd9b2e42fe9c4 Reviewed-on: https://chromium-review.googlesource.com/297804 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* nuc: Fixed the bugs for flash and i2c drivers.Mulin Chao2015-09-061-41/+83
| | | | | | | | | | | | | | | | | | | | | | | | | | | Since the length of flash-write function used by host command is not aligned to 256 bytes, we need to split it into several sequences to make sure it won't exceed page buffer size of flash. Add i2c stop condition checking to avoid unnecessary i2c unwedge operations. We found some battery will held scl for a while and master cann't issue stop condition immediately. Modified drivers: 1. flash.c: Add support for sequence programing. 2. i2c.c: Add i2c stop condition checking mechanism. 3. i2c.c: Fixed bug of i2c_is_raw_mode. (wrong bit offset) BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers BRANCH=none Change-Id: I4f35a617466ba37bcc4e3aa5324c8950f824a4c2 Signed-off-by: Ian Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/295662 Commit-Ready: Mulin Chao <mlchao@nuvoton.com> Tested-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* tasks: Remove most task_start_called() calls.Aseda Aboagye2015-08-011-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | Now that HOOK_INIT hooks are called from a task switching context, most calls to task_start_called() should no longer be needed. This commit removes them. BRANCH=None BUG=chrome-os-partner:27226 TEST=make -j buildall tests TEST=Flash EC image onto samus and verify EC boot, AP boot, keyboard, lid, and tap-for-battery all functional. TEST=Flash EC image onto samus_pd and verify charging still works. TEST=Flash EC image onto ryu(P3) and verify that EC boot. TEST=Added ASSERT(task_start_called()) to the places where I removed task_start_called(). Booted samus, samus_pd, cyan, and ryu with AC inserted and verified that no ASSERT's were hit upon boot. Change-Id: Ic12c61862e85ca3a0a295beedbb4eeee6d5e515b Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/285635 Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org> Trybot-Ready: Aseda Aboagye <aaboagye@chromium.org>
* nuc: Add SHI driver for arm-based platform in chip folder.Ian Chao2015-06-261-11/+98
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add npcx_evb_arm board-level driver for arm-based platform. Add header.c: for booting from NPCX5M5G A3 Booter. Remove lfw folder due to those functionalitie have been replaced with Booter Modified drivers for Patch Set 1: 1. flash.c: Implement UMA lock, tri-state and selection register lock functionalities 2. hwtimer.c: Add ITIM32 for hwtimer 3. lpc.c: Add checking for LRESET 4. system.c: Modified CODERAM_ARCH functions for NPCX5M5G A3 Booter. 5. uart.c: Add support for module 2 Patch Set 2: 6. lpc.c: Modified lpc_get_pltrst_asserted() func Patch Set 3: 7. minimize the changes for CONFIG_CODERAM_ARCH in common layer 8. comments of Patch Set1/2 Patch Set 4: 9. Modified CONFIG_RO_MEM_OFF point to ro image and keep header as a part of ec.RO.flat. 10. Fixed RO_FRID and RW_FRID issues which caused by CONFIG_CODERAM_ARCH. Patch Set 5: 11. Modified system.c in common folder for supporting *_STORAGE_OFF. 12. Use *_STORAGE_OFF in firmware_image.lds.S to indicate flat file layout in flash. Patch Set 6: 13. rebase to newest version 14. system.c: Modified for the newest include/system.h Patch Set 7: 15. Merge from version 0625 BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers BRANCH=none Change-Id: Ifd7c10b81b5781ccd75bb2558dc236486976e8ed Signed-off-by: Ian Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/272034 Reviewed-by: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Commit-Queue: Shawn N <shawnn@chromium.org>
* cleanup: Use appropriate image geometry CONFIGsShawn Nematbakhsh2015-05-151-5/+5
| | | | | | | | | | | | | | | | - Use CONFIG_*_MEM when dealing with images in program memory. - Use CONFIG_*_STORAGE when dealing with images on storage. - Use CONFIG_WP when dealing with the entire WP RO region. BUG=chrome-os-partner:39741,chrome-os-partner:23796 TEST=Manual on Cyan with subsequent commit. Verify that FMAP matches actual layout of image. Verify flashrom succeeds flashing + verifying EC image using host command interface. BRANCH=None Change-Id: Iadc02daa89fe3bf07b083ed0f7be2e60702a1867 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/270269
* npcx: Use SPI status register instead of pstateRandall Spangler2015-02-261-54/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The npcx chip and evb use a SPI flash chip to hold the EC image. They don't need pstate, and should use the SPI flash status register directly. 1. Remove CONFIG_FLASH_PSTATE from npcx_evb. 2. Remap WP_L GPIO to GPIO 93 (this should be the same as the write protect line to the SPI flash chip). 3. Change the npcx flash driver so that it directly reads/writes the SPI status register instead of mucking with pstate. BUG=chrome-os-partner:34346 BRANCH=none TEST=manual Add a switch or jumper to the EVB so R1 can be closed. Toggle the switch and see that WP_L state changes. Leave enabled. flashinfo -> nothing is protected, WP_L is enabled (=0) (also do this after each flashwp command to check the protection status) flashwp enable -> RO is protected now and at boot. reboot flashwp enable -> RO is still protected. flashwp disable -> RO is still protected. (because WP switch is enabled). Toggle the switch so WP_L is disabled (=1) flashwp disable -> Succeeds, flash is not protected Change-Id: Ifa959bce69f8eb4724057ecaa6a6c5075783c19d Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/253633 Reviewed-by: Shawn N <shawnn@chromium.org>
* WIP - Nuvoton 30-Jan patchRandall Spangler2015-02-251-10/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Issues fixed on 0216: 1.Modified CONFIG_KEYBOARD_COL2_INVERTED support in keyboard_raw.c 2.Modified warm_reset checking in gpio.c 3.Modified system_get_chip_name in system.c for package info. 4.Modified fan.c and pwm.c for: ● If the DCRn value is greater than the CTRn value, the PWM_n signal is always low. ● Fan stall condition event: If the measured fan speed is lower than the lowLimit value (unless the Fan Speed Low Limit value is 0) or in case of erroneous measurement, the userCallback is called. 5. Change cycle_pluses to 480 in board.c Issues fixed: 1. Jump data at top of RAM is getting corrupted. Changed the flag to RESET_FLAG_RESET_PIN. Added a workaround method to fix VCC1_RST issue. 2. Hibernate wake need to report whether wake reason was GPIO or RTC 3. Hibernate wake must be distinguishable from watchdog reset. The booter will log reset reason in Code RAM. I copy the log data to battery-backup RAM in little FW. And system driver will refer this data to distinguish if it's watchdog reset or not. 4. Watchdog reset flag is not set. Same fix as 3. 5. Should return error if unable to clear SPI flash status register. 6. Remove chip_temp_sensor.c 7. Remove use of pstate from flash driver 8. Remove support for watchdog warm reset 9. Keyboard raw driver must support COL2 inverted 10. LPC memory mapped data must be read-only from host 11. LPC should support PLTRST# signal 12. Problems reading chip type/version. Use core registers and ROM data to read IDs. 13. When chip type/version is unknown, report hex value. 14. Watchdog does not consistently print panic information. 15. Remove console force enable logic. 16. Enable only the peripheral clocks that are needed. Please notice user should add bit mask in CGC_XXX_MASK if they want to enable additional module. For example, if user wants to enable PWM3, he must add PWDWN_CTL2_PWM3_PD bit in CGC_PWM_MASK. Please see HOOK_FREQ_CHANGE and HOOK_INIT these two hook functions. If I turn off all I2C modules in system_pre_init and turn on the modules I need in i2c_init, I found its freq is not correct. The root cause is hook_notify(HOOK_FREQ_CHANGE) is executed first (in clock_init) before i2c_init. At this time, i2c modules are power-down and writing to freq register is useless. I re-execute freq-changed hook function after turning on modules again. 17. MPU properly configured to prevent code execution from data RAM 18. Partial nvcontext implementation. Copy these 16 bytes in our battery-backup RAM. Additional items we also modified: 1. pwm.c: Support open-drain IO type of PWM. (PWM IO-Type cannot by determined by GPIO, we use bit 1 & 2 of function byte of gpio_alt_func array to support it) 2. ec_npcxflash.c: Use definition to replace constant value. Stop watchdog during flash programing. 3. npcx_cmds.tcl: Adjust script sequence for robustness. Add unlock MPU commands for Data RAM. BUG=chrome-os-partner:34346 BRANCH=none TEST=manually verify changes Change-Id: I722a77d29e7543b054819480c7b7477af4263119 Signed-off-by: Ian Chao <mlchao@nuvoton.com> Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/248670
* nuc: Add all IC specific drivers of NPCX5M5GIan Chao2015-01-141-0/+708
Add npcx_evb in board folder for testing Add shared-spi arch support in common layer. Modified drivers for 1. Fan.c: console command “pwmduty”. 2. Pwm.c: for the issue when set duty to 0. 3. System.c: for hw reset only during system reset. 4. Flash.c: Fixed access denied bug of the flash driver for host command. 5. Comments from Patch Set 1 6. Comments from Patch Set 3 (except sha256.c) 7. Add openocd and flash_ec support for npcx_evb 8. Add little FW and spi-flash upload FW in chip folder 9. Add optional make rules for PROJECT_EXTRA 10.Replace CONFIG_SHRSPI_ARCH with CONFIG_CODERAM_ARCH and remove changes in common layer sources for shared-spi arch. (except sysjump) 11.Find the root cause of JTAG issue and use workaround method with SUPPORT_JTAG in clock.c 12 Execute hibernate in low power RAM for better power consumption 13 Add workaround method for version console command 14 Modified coding style issues by checkpatch.pl tool BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers BRANCH=none Change-Id: I5e383420642de1643e2bead837a55c8c58481786 Signed-off-by: Ian Chao <mlchao@nuvoton.com> Signed-off-by: Randall Spangler <rspangler@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/233742
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