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path: root/chip/npcx/gpio.c
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* COIL: Change host interface option to CONFIG_HOSTCMD_SHIKeith Short2021-08-031-1/+1
| | | | | | | | | | | | | | Update SPI host interface config option for inclusive language. BUG=b:163885307 BRANCH=none TEST=compare_build.sh Signed-off-by: Keith Short <keithshort@chromium.org> Change-Id: I808d5960fa3e746626465bedc626a95e0f0aaa3f Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3066271 Commit-Queue: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
* chip/npcx: Fix comment white spaceCaveh Jalali2021-05-271-1/+1
| | | | | | | | | | | | | | This fixes a missing white space in a comment. BUG=none BRANCH=none TEST=buildall passes Change-Id: Ifde65ab45be7fa6881195ecf723d999d9991f2aa Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2921289 Reviewed-by: Boris Mittelberg <bmbm@google.com> Commit-Queue: Boris Mittelberg <bmbm@google.com>
* common: move some structures from .rodata to .dataKeith Short2021-02-051-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the GPIO tables and the USB PRL states from .rodata to .data on boards that support CONFIG_CHIP_DATA_IN_INIT_ROM. This saves 1600 to 1900 bytes of flash space (and reduces RAM space by the similar amount). Boards affected: delbin_npcx796fc eldrid_npcx796fc halvor lindar lingcod magolor_legacy malefor metaknight_legacy terrador todor trondo voema volteer_apmodeentry volteer waddledoo BUG=none BRANCH=none TEST=make buildall TEST=boot Volteer, run gpioget Signed-off-by: Keith Short <keithshort@chromium.org> Change-Id: I1a9f421981fb8db4d7ddd62b21d609a401862491 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2677087 Reviewed-by: Abe Levkoy <alevkoy@chromium.org> Commit-Queue: Abe Levkoy <alevkoy@chromium.org>
* npcx: Don't delay hibernate wake by 2 seconds (v2)Edward Hill2020-12-161-5/+1
| | | | | | | | | | | | | | | | | | | | | | | Revert CL:2576439 and try again, this time checking for EC_RESET_FLAG_HIBERNATE before setting EC_RESET_FLAG_INITIAL_PWR. The problem with the first attempt was on sysjump to RW after wake from hibernate. Then gpio_pre_init() saw EC_RESET_FLAG_INITIAL_PWR but not EC_RESET_FLAG_HIBERNATE and so added an unwanted 2 second delay because system_common_pre_init() hadn't yet restored the flags from before the jump. Moving the check for EC_RESET_FLAG_HIBERNATE into check_reset_cause() avoids this issue. BUG=b:173180800 BRANCH=zork TEST=no 2 second delay on wake from hibernate, for both RO boot and jump to RW. Signed-off-by: Edward Hill <ecgh@chromium.org> Change-Id: Ia1bfba5740d77961ccc7e140da80be1070700b1e Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2592501 Reviewed-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Peter Marheine <pmarheine@chromium.org>
* npcx: Don't delay hibernate wake by 2 secondsEdward Hill2020-12-071-1/+5
| | | | | | | | | | | | | | | Waking from PSL hibernate is power-on for EC but not for H1, so we should not add the 2 second delay for CONFIG_BOARD_RESET_AFTER_POWER_ON in this case. BUG=b:173180800 BRANCH=zork TEST=no 2 second delay on wake from hibernate Signed-off-by: Edward Hill <ecgh@chromium.org> Change-Id: Ib0c8f2ca7f197626b20a11e21ace44a5046db18b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2576439 Reviewed-by: Peter Marheine <pmarheine@chromium.org>
* npcx: Explicitly disable alt-function for unused pinsWai-Hong Tam2020-10-311-2/+5
| | | | | | | | | | | | | | Make the unused pins as GPIO and disable any alt-function. BRANCH=None BUG=b:169595541 TEST=make buildall -j Change-Id: I6b7c16dd68654b38c8a12654207438315fe86c2c Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2508862 Reviewed-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Stephen Boyd <swboyd@chromium.org>
* npcx: Configure unused GPIOs as INPUT with PU to save powerWai-Hong Tam2020-10-221-0/+6
| | | | | | | | | | | | | | | | | According to Power Consumption Investigation Guide, by Nuvoton, setting the disconnected/unused pins as input with an internal pull-up gets better power number. Do it automically for all GPIOs defined through the UNUSED() macro. BRANCH=None BUG=b:169595541 TEST=make buildall -j Change-Id: I929c139e73d8253c79e0b9a3445217a300dc98cb Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2488214 Reviewed-by: Alexandru M Stan <amstan@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* npcx: add GPIO support for npcx9 and refactor GPIO driverCHLin2020-09-251-181/+18
| | | | | | | | | | | | | | | | | | | | | 1. Add GPIO driver support for npcx9. 2. move the GPIO interrupt handler (MIWU) from gpio.h to gpio-npcx5.h, gpio-npcx7.h, and gpio-npcx9.h separately. Note: gpio-npcx7.h is a link to gpio-npcx5.h because almost all of the source codes are the same. BRANCH=none BUG=b:165777478 TEST=pass "make buildall" TEST=with related CLs, build and flash image on the npcx5/7/9 EVB and yorp; verify GPIO functionality. Signed-off-by: CHLin <CHLin56@nuvoton.com> Change-Id: I665507f804ca3772f81f0ff8bd917a633bda2d11 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2402842 Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: caveh jalali <caveh@chromium.org> Commit-Queue: CH Lin <chlin56@nuvoton.com>
* npcx: rtc: Prevent locking a mutex in interrupt contextWai-Hong Tam2020-07-301-1/+9
| | | | | | | | | | | | | | | | In the RTC interrupt, it calls host_set_single_event() directly, that eventually tries to lock a mutex. Trying to lock a mutex in the interrupt context should be forbidden. So move the call to a deferred function. BRANCH=None BUG=b:162434716 TEST=Running suspend_stress_test doesn't result any EC crash. Change-Id: I80d1f1d8cefa4b8d01e707edff602dfdc860fc35 Signed-off-by: Wai-Hong Tam <waihong@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2327248 Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
* npcx: Add a new flag to check for initial power-onAndrew McRae2020-06-231-4/+4
| | | | | | | | | | | | | | | | | | | | | The CR50 will reset the EC on some platforms after power-on. Add a reset flag to detect this and treat the second restart as a power-on restart rather than reset. Subsume the CONFIG_GPIO_INIT_POWER_ON_DELAY_MS config to make it clear what the behaviour will be. BUG=b:151329011 TEST=Confirm on dalboz, puff & variants that second reset is treated correctly. BRANCH=none Change-Id: Ib66de920403f08099b87d1eff797270606b44f8f Signed-off-by: Andrew McRae <amcrae@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2255830 Reviewed-by: Peter Marheine <pmarheine@chromium.org> Commit-Queue: Andrew McRae <amcrae@chromium.org> Tested-by: Andrew McRae <amcrae@chromium.org>
* Cleanup: Correct GPIO alternate function parameterVijay Hiremath2019-11-011-6/+9
| | | | | | | | | | | | | | | Added code to correct the GPIO alternate function parameter at Chipset level. Optionally board level functions can cleanup the code in additional change lists. BUG=b:139427854 BRANCH=none TEST=make buildall -j Change-Id: I1171ca36a703291070fc89f972f84414adcf04fc Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1880974 Reviewed-by: Keith Short <keithshort@chromium.org>
* NPCX GPIO: Assert that gpio_get/set_level is passed a GPIO signalEdward Hill2019-10-251-0/+4
| | | | | | | | | | | | | | | Ensure that IOEX and VW signals are not accidentally passed to NPCX's gpio_get_level or gpio_set_level. BUG=b:138600691 BRANCH=none TEST=saw assert when passing IOEX signal to gpio_set_level Change-Id: Ib3eea074a104820cea4095897f4174a84e8368d6 Signed-off-by: Edward Hill <ecgh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1854781 Reviewed-by: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* include: Move RESET_FLAG_* into ec_commands.h as EC_RESET_FLAG_*You-Cheng Syu2019-08-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | RESET_FLAGS_* are used when setting/reading the field ec_reset_flags of struct ec_response_uptime_info, which is defined in ec_commands.h. So it might be better to put those macros there. To be consistent with the other macros in the file, add "EC_" prefixes to them. BUG=b:109900671,b:118654976 BRANCH=none TEST=make buildall -j Cq-Depend: chrome-internal:1054910, chrome-internal:1054911, chrome-internal:1045539 Change-Id: If72ec25f1b34d8d46b74479fb4cd09252102aafa Signed-off-by: You-Cheng Syu <youcheng@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1520574 Tested-by: Yu-Ping Wu <yupingso@chromium.org> Commit-Ready: Yu-Ping Wu <yupingso@chromium.org> Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org> Reviewed-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* LICENSE: remove unnecessary (c) after CopyrightTom Hughes2019-06-191-1/+1
| | | | | | | | | | | | | | | | Ran the following command: git grep -l 'Copyright (c)' | \ xargs sed -i 's/Copyright (c)/Copyright/g' BRANCH=none BUG=none TEST=make buildall -j Change-Id: I6cc4a0f7e8b30d5b5f97d53c031c299f3e164ca7 Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1663262 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* gpio: add config option for using gpio_get_flagsMary Ruthven2019-04-051-1/+1
| | | | | | | | | | | | | | | Separate gpio_get_flags from the CONFIG_CMD_GPIO_EXTENDED, so we can enable getting the gpio flags without enabling the ability to set them. BUG=none BRANCH=cr50 TEST=none Change-Id: Ib8e3a13fdcfe8ebec4523eb070b2425b5dc28278 Signed-off-by: Mary Ruthven <mruthven@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1542798 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* common: bit change 1 << constants with BIT(constants)Gwendal Grignou2019-03-261-1/+1
| | | | | | | | | | | | | | | | | Mechanical replacement of bit operation where operand is a constant. More bit operation exist, but prone to errors. Reveal a bug in npcx: chip/npcx/system-npcx7.c:114:54: error: conversion from 'long unsigned int' to 'uint8_t' {aka 'volatile unsigned char'} changes value from '16777215' to '255' [-Werror=overflow] BUG=None BRANCH=None TEST=None Change-Id: I006614026143fa180702ac0d1cc2ceb1b3c6eeb0 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1518660 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* npcx: gpio: implement the gpio_get_flags_by_mask functionCHLin2018-11-051-3/+85
| | | | | | | | | | | | | | | | | | | | This CL adds the gpio_get_flags_by_mask function which is used to get the flag information of a GPIO when CONFIG_CMD_GPIO_EXTENDED is enabled. BRANCH=none BUG=b:118390658 TEST=No build error for make buildall. TEST=Enable CONFIG_CMD_GPIO_EXTENDED in npcx7_evb/board.h; modify flags of GPIOs in gpio.inc to cover all the flags required to be shown in print_gpio_info(); check the result of "gpioget" is consistent with what is set in the gpio.inc. Change-Id: Icb17e59f959c0d15e95023f27187972f690d88ce Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/1312515 Commit-Ready: CH Lin <chlin56@nuvoton.com> Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* npcx: gpio: fix bugs of low voltage level selectionCHLin2018-10-301-9/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This CL fixed the following bugs of low voltage support of GPIO: 1. fix the mismatch issue of low voltage support GPIOs when the mask passed to gpio_low_voltage_level_sel() has multiple bits set. (see more detail in the bug:118443060.) The idea is to create a new function gpio_low_vol_sel_by_mask() to iterate the match for each bit set in the mask. i.e. while (lv_mask) { bit = get_next_bit(&lv_mask); gpio_low_voltage_level_sel(p, bit, low_vol); }; The second parameter of gpio_match()/gpio_low_voltage_level_sel is also changed from "mask" to "bit" because of above modification. 2. It was observed that there are some errors of the low level mapping table because the older datasheet we used to develop the driver is not correct. After checking the latest datasheets of all EC sku, the low level table should have the following modification: - GPIO65 cannot support low level and should be removed. - GPIO86 can support low level in all EC skus. BRANCH=none BUG=b:118443060 TEST=Add GPIO_SEL_1P8V flag in the ALTERNATE macros which have multiple bits set in the mask field in npcx7_evb board. Flash the image and make sure the warning message doesn't print and the related low level bits are set. Change-Id: I7aa23eb42dda178db34fe44a663df29757910a55 Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/1301674 Commit-Ready: CH Lin <chlin56@nuvoton.com> Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Wai-Hong Tam <waihong@google.com>
* npcx: add console command to better investigate power consumption of GPIOsCHLin2018-10-301-0/+97
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This CL adds the console command to disable the input buffer of non-I2C and non-ISR GPIOs which are configured as either input or open-drain. The GPIOs set as 1.8V are also ignored because they are already disabled in the gpio_pre_init. Usage: 1. type "gpiodisable next" to disable the input buffer of next GPIO wihch is either input or open drain in the gpio list. (if the next one is I2C or 1.8V or ((!input) && (!open-drain)), it will ignore it and check the following next one). Ex: > gpiodisable next current GPIO : 16 LID_ACCEL_INT_L --> Ignore 1v8 pin! current GPIO : 17 PLT_RST_L --> Disable WKINEN! > gpiodisable next current GPIO : 18 SYS_RESET_L --> Disable WKINEN! > gpiodisable next current GPIO : 19 ENTERING_RW --> Not Input or OpenDrain current GPIO : 20 PCH_WAKE_L --> Disable WKINEN! ......... ......... > gpiodisable next current GPIO : 34 I2C0_SCL --> Ignore I2C pin! current GPIO : 35 I2C0_SDA --> Ignore I2C pin! current GPIO : 36 I2C1_SCL --> Ignore I2C pin! current GPIO : 37 I2C1_SDA --> Ignore I2C pin! current GPIO : 38 I2C2_SCL --> Ignore I2C pin! current GPIO : 39 I2C2_SDA --> Ignore I2C pin! current GPIO : 40 I2C3_SCL --> Ignore I2C pin! current GPIO : 41 I2C3_SDA --> Ignore I2C pin! current GPIO : 42 I2C4_SCL --> Ignore I2C pin! current GPIO : 43 I2C4_SDA --> Ignore I2C pin! current GPIO : 44 I2C7_SCL --> Ignore I2C pin! current GPIO : 45 I2C7_SDA --> Ignore I2C pin! current GPIO : 46 EN_USB_A0_5V --> Not Input or OpenDrain current GPIO : 47 EN_USB_A1_5V --> Not Input or OpenDrain current GPIO : 48 USB_A0_CHARGE_EN_L --> Not Input or OpenDrain current GPIO : 49 USB_A1_CHARGE_EN_L --> Not Input or OpenDrain current GPIO : 50 USB_C0_BC12_VBUS_ON --> Not Input or OpenDrain current GPIO : 51 USB_C0_BC12_CHG_DET_L --> Disable WKINEN! 2. Enable/Disable a specific GPIO's input buffer by "gpiodisable ${GPIO_NUM_IN_LIST} on|off" (use "gpiodisable list" can check the GPIO_NUM_IN_LIST of a GPIO) Ex: > gpiodisable list 16: LID_ACCEL_INT_L 17: PLT_RST_L 18: SYS_RESET_L ...... ...... > gpiodisable 17 off --> disable input buffer of GPIO PLT_RST_L > gpiodisable 17 on --> enable input buffer of GPIO PLT_RST_L BRANCH=none BUG=b:117139495 TEST=No build errors for "make buildall". TEST=Manually run the console commands and check the result as expected. Change-Id: I7c750804cf45218a3ab1baacefcda64833861b1f Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/1275765 Commit-Ready: CH Lin <chlin56@nuvoton.com> Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* npcx: gpio: support internal pull-down when enable low voltage modeCHLin2018-10-261-5/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | There is the limitation that internal pull-up must be disabled when a GPIO is configured in low voltage level. However, thers is no such limitation of internal pull-down. The current GPIO driver disable no matter pull-up or pull-down when low voltage mode is set. This CL fixes it by: 1. enable internal PD when low voltage mode is set. 2. print warning message in the UART console when both low voltage and internal PU flags are set for any GPIO defined in gpio.inc. BRANCH=none BUG=b:118339468 TEST=No build error for make buildall TEST=define a gpio with internal PD+low-voltage in npcx7_evb/gpio.inc, check the releated bits of PxPULL and PxPUD are set; TEST=define a gpio with internal PU+low-voltage, check the warning message is printed on the console. Change-Id: I8e15125d3a2ccc73f84b8a559d12644b1d1af5f9 Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/1297872 Commit-Ready: CH Lin <chlin56@nuvoton.com> Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Wai-Hong Tam <waihong@google.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* Add CONFIG_GPIO_INIT_POWER_ON_DELAY_MSEdward Hill2018-09-041-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | On power on, H1 releases the EC from reset but then quickly asserts and releases the reset a second time (so that the EC comes out of reset the second time after the SPI buffers have been configured by H1). Add a delay so the EC can wait for this second reset before configuring GPIO outputs, to avoid extra output toggles. Unfortunate the timer is not set up by the time gpio_pre_init() is called, so we add a new __hw_early_init_hwtimer() function to set it up so that mdelay() worked. Without that, mdelay() hangs. BUG=b:72132384 BRANCH=none TEST=GPIO_OUT_HIGH has a single rising edge after power on (before it would rise-fall-rise) Check that mdelay(10) delays for about 10ms (actually perhaps a little more using a scope line on KB_BL_EN Change-Id: Iadc96fceb190e43ac0758f291f22e03aef81c379 Signed-off-by: Edward Hill <ecgh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/879353 Commit-Ready: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
* npcx: uart: Add driver support for the second UARTCHLin2018-07-051-11/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Nuvoton NPCX79nxB serie chips include two UART ports. In this CL, we add the driver support for these two UART modules. Develoers can select one of the UART ports as EC console by configuring "CONFIG_CONSOLE_UART" in board.h BRANCH=none BUG=none TEST=No build errors for make buildall. TEST="#define CONFIG_CONSOLE_UART 0"; build and flash image on npcx7 EVB; check EC console working via J21. TEST="#define CONFIG_CONSOLE_UART 1"; build and flash image on npcx7 EVB; check EC console working via J22. (Note: J16.3-J16.5 and JP6.2-JP6.3 must be connected together.) TEST=build images of board npcx_evb, poppy, and grunt, make sure EC console is functional on these boards. TEST=#define "CONFIG_CONSOLE_UART 0" and "CONFIG_UART_PAD_SWITCH" in board.h; build and flash image on npcx7_evb. check uart_alt_pad_read_write function still works by using the console command like: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/659460/1/board/poppy/board.c Change-Id: I7de91680e5d4f56c7cae66482c0953d8c324dbe7 Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/1113269 Commit-Ready: CH Lin <chlin56@nuvoton.com> Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* npcx: gpio: bypass for excessive power consumption on low-voltage IOs.Mulin Chao2018-06-291-1/+69
| | | | | | | | | | | | | | | | | | | | | | | | | | It was found that for npcx ec's GPIOs that support low-voltage input, there is an excessive power consumption when they are selected to low-voltage mode and their Vin is 1.8V. To bypass this issue when the chip enters deep sleep where current is important, this CL includes: 1. Disable GPIOs without ISR which are selected to 1.8V and not i2c ports in gpio_pre_init(). 2. Disable input buffer of 1.8V i2c ports before entering deep sleep. 3. Enable input buffer of 1.8V i2c ports after ec wakes up. BRANCH=none BUG=b:110170824 TEST=No build errors for npcx ec series. Measured power consumption on yorp and it saved ~1.3mA current after applying this patch at S0ix. Run stress test on poppy and no symptom found. Remove CONFIG_LOW_POWER_IDLE in board driver and no symptom occurred on poppy and yorp. Change-Id: Iaf66c81ca16104839734ba19492f2061113dafb3 Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/1098864 Reviewed-by: Jett Rink <jettrink@chromium.org>
* lpc/espi: convert ec chip code to use granular optionJett Rink2018-05-221-2/+2
| | | | | | | | | | | | | | Break the ec chip code up with the more granular CONFIG_HOSTCMD_(X86|LPC|ESPI) options. BRANCH=none BUG=chromium:818804 TEST=Full stack builds and works on yorp (espi) and grunt (lpc) Change-Id: Ie272787b2425175fe36b06fcdeeee90ec5ccbe95 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1067502 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* chip/npcx: Ensure software watchdog has highest priorityNicolas Boichat2018-04-051-16/+16
| | | | | | | | | | | | | | | | | | | | | Before this change uart_ec_interrupt and software watchdog interrupt handler both had priority 0. Since UART IRQ number is 33, and software watchdog is 44, the UART interrupt handler would have higher prority. Fix this by increasing all interrupt handler priorities, leaving the software watchdog handler alone on priority 0. BRANCH=eve,poppy,fizz BUG=b:76391320 TEST=Cherry-pick CL:979736 (causes a watchdog in UART interrupt handler), check that panicinfo contains a sensible PC in r5 after reset. Change-Id: I97f99af5192a4a9571854a4d3f7c48a4674d605e Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/979738 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* host_events: Bump up host events and masks to 64-bitFurquan Shaikh2017-11-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | With the upcoming change to add a new command to get/set/clear host events and masks, it seems to be the right time to bump up the host events and masks to 64-bit. We are already out of available host events. This change opens up at least 32 bits for new host events. Old EC commands to operate on host events/masks will still deal with lower 32-bits of the events/mask. On the other hand, the new command being added will take care of the entire 64-bit events/masks. This ensures that old BIOS and kernel versions can still work with the newer EC versions. BUG=b:69329196 BRANCH=None TEST=make -j buildall. Verified: 1. hostevent set 0x4000 ==> Sets correct bit in host events 2. hostevent clear 0x4000 ==> Clears correct bit in host events 3. Kernel is able to query and read correct host event bits from EC. Verified using evtest. 4. Coreboot is able to read correct wake reason from EC. Verified using mosys eventlog list. Change-Id: Idcb24ea364ac6c491efc2f8dd9e29a9df6149e07 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/770925 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* npcx/flash: not enable the flash pinmux when using internal flashCHLin2017-10-151-0/+2
| | | | | | | | | | | | | | | | | | | | | | In npcx5, the flash interface pinmux should be turned on in order to access the external flash. However, in npcx7, the internal flash is used. It is meaningless to turn the pinmux on. And it also causes the alternative function of these pins not work normally(such as GPIOA0/GPIOA2) if the pinmux is enabled. This CL uses the preprocessor flag NPCX_INT_FLASH_SUPPORT to conditionally prohibit the execution of flash pinmux code. BRANCH=none BUG=none TEST=No build errors for "make buildall". Build npcx_evb and npcx7_evb boards, make sure the pinmux are correctly configured seperately. Change-Id: Iba2300159f204b65d15852ec1755714df0c64816 Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/704316 Commit-Ready: CH Lin <chlin56@nuvoton.com> Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* npcx: gpio: Optimize gpio_interrupt_type_sel() for code space reductionShawn Nematbakhsh2017-07-271-19/+11
| | | | | | | | | | | | | | | | gpio_interrupt_type_sel() is guaranteed to be called with at least one GPIO_INT_ANY bit set, but our new toolchain doesn't seem to realize it. BUG=chromium:747553 BRANCH=None TEST=`make BOARD=gru -j` with next_gcc, also verify kevin boots to OS. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Ice2a9963983dca2ee9c0c543bf55c27753c42933 Reviewed-on: https://chromium-review.googlesource.com/584820 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* npcx: gpio: Clear GPIO interrupt if no ISR is availableShawn Nematbakhsh2017-07-251-0/+4
| | | | | | | | | | | | | | | | | | | If we have no ISR for an enabled GPIO interrupt (eg. for a UART GPIO interrupt that wakes from low-power idle) then clear it, to avoid interrupt storm. BUG=b:63958831 BRANCH=eve TEST=Verify we can repeatedly wake from low-power idle on eve by hitting 'enter' on the EC console. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I6a01cae33e3bf1a3b5b42c0389c4613dc1cb9b7d Reviewed-on: https://chromium-review.googlesource.com/584011 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@google.com> Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
* npcx: gpio: Lock VCC_RST# alternative bit of DEVALTA.Mulin Chao2017-06-101-0/+2
| | | | | | | | | | | | | | | | This CL locks VCC_RST# alternative bit, NO_VCC1_RST, of DEVALTA in case the developers switch it to GPO77 unexpectedly by setting VCC1_RST_LK bit in DEV_CTL4. BRANCH=none BUG=none TEST=Use rw console command to make sure NO_VCC1_RST bit is locked on npcx7_evb. Change-Id: Ic7882ef1c8050c3daca85bd241d5368f009e4e2e Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/522206 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* npcx: system: fix the incorrect checking of invalid BBRAM(IBBR) bit.CHLin2017-06-081-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | This CL adds: 1. Fixed the incorrect address of BKUP_STS register. 2. Cleared the IBBR bit of BKUP_STS register at initial because its default value is 1(means the content of BBRAM is invalid) whenever VBAT is powered up. 3. Add debug msg when IBBR bit is set to indicate the BBRAM's corruption. 4. Modified the valid BBRAM offset from 1 to 0 and size from 63 to 64. BRANCH=none BUG=b:38187362 TEST=No build error for make buildall; Check IBBR is cleared at initial. Check IBBR is set by changing the VBAT voltage below VBAT MIN. Test console command "reboot ap-off" on poppy. Change-Id: I69d98b50d4e0aec17b55a4a9b5e8f1a412a3fe45 Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/505861 Commit-Ready: CH Lin <chlin56@nuvoton.com> Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* npcx: flash: Add write-protect support for internal flash of npcx7 ecstabilize-9554.BMulin Chao2017-05-121-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | In order to support write-protect mechanism for the internal flash of npcx7 ec, WP_IF, bit 5 of DEV_CTL4, is used to achieve this by controlling the WP_L pin of internal flash. During ec initialization or any utilities related to access status registers, we'll protect them if WP_L is active. Please notice the type of WP_IF is R/W1S. It means we only can unlock write protection of internal flash by rebooting ec. This CL also includes: 1. Add protect_range array of npcx7's internal flash (W25Q80) for write-protect mechanism. 2. Add bypass of bit 7 of DEVCNT. BRANCH=none BUG=none TEST=No build errors for all boards using npcx5 series. (Besides gru) Build poppy board and upload FW to platform. No issues found. Passed flash write-protect checking on npcx796f evb. Change-Id: I0e669ce8b6eaebd85e062c6751e1f3dd809e21e2 Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/501727 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* npcx: gpio: Add support for npcx7 series ec.Mulin Chao2017-04-251-129/+63
| | | | | | | | | | | | | | | | | | | | | | | | | This CL includes: 1. Add gpio_chip-npcx5/7.h files and move all macro functions related to chip family to them. (Move wui macro func from gpio_wui.h to them.) 2. Replace alternative and low-voltage mapping table with macro function NPCX_ALT_TABLE and NPCX_LVOL_TABLE. 3. Add UART wakeup mechanism in __gpio_wk1h_interrupt() ISR. 4. Add gpio register definitions of npcx7 family in registers.h. 5. Add GPIO_LOCKED flag for lock functionality. BRANCH=none BUG=none TEST=No build errors for all boards using npcx5 series (besides gru). Build poppy board and upload FW to platform. No issues found. Passed validation for all GPIO functionalities on npcx5m6g and npcx796f evb. Change-Id: I60c30ce223629a0d8cb767a54a0a9b02a69de9c5 Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/481561 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* npcx: gpio: Change second tachometer source from TB2 to TA2.Mulin Chao2017-04-181-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | In npcx's fan driver, ec selected mode 5 and capturer A as tachometer's input. Choosing TB2 as the second tachometer source is not correct since we didn't initialize the registers for TB2. This patch modified the second tachometer's input from TB2 to TA2 and passed the verification by following changes. 1. Add the second fan settings in pwm_channels, fans, and mft_channels arraies. 2. Modified ALTERNATE marco for pwm-type fans. 3. Set CONFIG_FAN from 1 to 2. 4. Set NPCX_TACH_SEL2 to 1 to test tachometer input 2. (ie.GPIO73/A6) BRANCH=none BUG=none TEST=test dual fans with fanset command on npcx_evb and use faninfo for verifying. Measure the actual rpm by scope. Change-Id: Ia1af2732d9a64e24285d12371223eb0e77e53357 Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/472310 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* npcx: Move pwm open-drain functionality from gpio to pwm driver.Mulin Chao2017-03-241-18/+0
| | | | | | | | | | | | | | | | Setting PWM IO type in gpio driver seems not a proper way. This CL moves this functionality to pwm driver and introduces a new flag PWM_CONFIG_OPEN_DRAIN to achieve it when user declared it in board driver. BRANCH=none BUG=none TEST=test pwm functionality on npcx_evb. Change-Id: I90c60445d1fb10902244ddf0f635d8304e72f4ab Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/458043 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* npcx: gpio: refactor gpio driver for better interrupt latency.Mulin Chao2017-03-211-322/+111
| | | | | | | | | | | | | | | | By generating the wui mapping table for GPIO pins which have interrupt handler like CL 451366 did, we needn't browse all items in original gpio_wui_table to find the MIWU info. It saves code space and improves interrupt lantency. BRANCH=none BUG=none TEST=Test gpio functionality on npcx_evb, reef and poppy. Change-Id: I77e9ad439ecf6a501a7976fe5099dd309dba81ee Signed-off-by: Vincent Palatin <vpalatin@chromium.org> Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/449514
* npcx: gpio: Fixed bug GPIO's ISRs clear the other pending bits.Mulin Chao2017-03-031-5/+6
| | | | | | | | | | | | | | | | | | | Since the interrupts of MIWU group E/F/G/H of table 0 are the same (interrupt 11), we need to handle LPCs' and GPIOs' events at the same ISR. But we also found there is a leak that ec has the chance to skip the other events which don't belong to GPIOs unexpectedly. (For example, LRESET and eSPI Reset) This CL fixed this issue by only clearing pending bits belong to GPIOs in their ISRs. BRANCH=none BUG=b:35648154 TEST=passed warm-reset testing on pyro over 12 hours. Change-Id: Ie626db00b54cff566798b4a593f6b0267a6fadc2 Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/449472 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* gpio: Add function to clear pending interruptDuncan Laurie2017-03-011-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | Currently if an interrupt is pending before it is enabled the interrupt will fire immediately. In most cases this is fine, but if we want to use the interrupt to trigger something like waking the AP it should be sure that it won't immediately fire once enabled. For example: on the Eve board we have the trackpad interrupt run to the AP and the EC in order to support wake from Deep S3 (magic AP state that only the EC can wake it from). This interrupt is used in S0 by the AP while ignored by the EC, and then enabled on the transition to S3 in order to be able to wake. Since it has been active the interrupt may be pending in the EC (depending on the chip), which can result in the interrupt firing immediately and waking the AP. BUG=chrome-os-partner:62224 BRANCH=none TEST=This has been functionally tested on npcx only as that is what I have a use case and system for, the others compile and look right but have not been directly tested. Change-Id: I9e0877d99e7f09f4c30bf9861fbad81c12c059ad Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://chromium-review.googlesource.com/446962 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* npcx: gpio: Only call ISR for enabled interruptsDuncan Laurie2017-02-241-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The GPIOs on npcx are handled in banks of 8, and when processing an interrupt for a particular bank the ISR is executed for each GPIO in the bank that has a pending bit set. If an interrupt in a bank is not enabled (but has fired before so the pending bit is set) but another one in the same bank is enabled and asserts, then the ISR both of the GPIOs will be executed because they both have pending bits set. This results in the ISR for a disabled interrupt getting executed when it should not and leads to unexpected behavior. Masking the GPIOs that are not enabled means only the ISR for the explicitly enabled GPIOs in that bank will be executed. Example: With the Eve board we have PCH_SLP_SUS_L on GPIO(6,2) which is enabled at init time and is in the same WKINTG_1 bank as TRACKPAD_INT_L on GPIO(7,1) which is not enabled, but I am working on a patch to enable it. When going into suspend PCH_SLP_SUS_L asserts, and that is causing the ISR for both PCH_SLP_SUS_L and TRACKPAD_INT_L to be executed. If I try to use TRACKPAD_INT_L as a wake source from DeepS3 this means the system immediately wakes after going to sleep. BUG=chrome-os-partner:62224 BRANCH=none TEST=With an additional patch to enable trackpad wake from S3 on Eve, observe that the system can enter S3 and stay there instead of immediately waking up due to the TRACKPAD_INT_L ISR firing when it is not enabled. Change-Id: Idc66e22c93756faf6c4319980cfb8dfe63e0dfaa Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://chromium-review.googlesource.com/446524 Reviewed-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* npcx: gpio: Add GPIO_INT support for KSI pinsMulin Chao2017-01-191-0/+19
| | | | | | | | | | | | | | | On tablet platform, ec isn't in charge of keyboard and KSI pins are free to use. This CL adds MIWU group and GPIO's ISR for KSI pins if there is no keyboard scan task. BRANCH=none BUG=none TEST=test all KSI pins for GPIO_INT on npcx_evb. Change-Id: I76c8e48c067b6cb84e483eb94b104eb1998987be Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/430554 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* npcx: gpio: Remove DEBUG_GPIO to make gpio_interrupt reentrantShawn Nematbakhsh2016-09-231-4/+0
| | | | | | | | | | | | | | | | | | | | GPIO interrupt priority levels can vary (notably, SHI CS interrupt is higher) so gpio_interrupt must be reentrant. BUG=chrome-os-partner:57434 BRANCH=Kevin TEST=Stress test on kevin 'pd 1 reset' with OEM charger attached, verify pdcmd task never gets wedged with TCPC ALERT stuck low. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: If853b80ebcef622480389a7cc94e851de0f8bb20 Reviewed-on: https://chromium-review.googlesource.com/388745 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> (cherry picked from commit 011da7eb51c10a8e108bae0e489ff3ddc848ee33) Reviewed-on: https://chromium-review.googlesource.com/388749 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* kevin: Use 32.768KHz input clock for improved RTC accuracyShawn Nematbakhsh2016-09-071-0/+4
| | | | | | | | | | | | | | | BUG=chrome-os-partner:56949 BRANCH=None TEST=Run stopwatch for 10 minutes, verify 'rtc' time difference matches stopwatch. Change-Id: I3aed54b17433f9acfe284e9c8846d4e1e7c1a199 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/381571 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
* npcx: Don't enable GPIO interrupts by defaultShawn Nematbakhsh2016-08-231-5/+6
| | | | | | | | | | | | | | | | | | | GPIO interrupts must first be enabled with a call to gpio_enable_interrupt() to prevent ISRs from being run before prerequiste modules are initialized. BUG=chrome-os-partner:56486 BRANCH=None TEST=Manual on kevin, stress test sysjump for ~1 hour (~700 sysjumps) without failure. Change-Id: Ia4006ef1b0c3218dfe5c92fde6713c10b0d22d2a Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/374020 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
* npcx: Add espi driver of npcx5mng for x86-based platform.Mulin Chao2016-08-101-6/+13
| | | | | | | | | | | | | | | | | | | | | | | Add espi driver for x86-based platform which support espi interface such as skylake and so on. Added source: 1. espi.c: Add drivers which supports the utilities of peripheral and virtual-wire channels so far. 2. espi.h: Add espi virtual-wire declaration for power sequence FW. Modified sources: 1. lpc.c: Add interrupts and initialization steps for espi. 2. gpio.c: Add interrupt handler of espi reset. BRANCH=none BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers Change-Id: Ie80afe79d85aba47fc0b72898a8374c2898ec114 Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/366181 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* npcx: Adjust relative IRQ priorities for high-priority UARTShawn Nematbakhsh2016-08-071-14/+14
| | | | | | | | | | | | | | | | | | | Our UART interrupt must be able to preempt our SHI_CS interrupt, otherwise console input may be lost. Adjust our relative IRQ priorities to accommodate this. BUG=chrome-os-partner:55920 BRANCH=None TEST=Run `echo "kbpress 11 4 1" > /dev/pts/17` on kevin 200 times from the recovery screen, verify that all input is received by the EC. Change-Id: I36203511f5883272287ac22d0704098fbd933758 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/366622 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
* Cleanup: gate RTC console/host command behind new config optionsphilipchen2016-06-291-0/+2
| | | | | | | | | | | | | | | | Put RTC code supporting console/host command behind new flags 'CONFIG_CMD_RTC'/'CONFIG_HOSTCMD_RTC' BUG=chromium:613699 TEST=make buildall BRANCH=master Change-Id: Ida52265d124978f48bd6ca522be3badee9f99588 Reviewed-on: https://chromium-review.googlesource.com/356206 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* npcx: Fixed host access pending bit issue in INT11 ISR.Mulin Chao2016-06-141-10/+10
| | | | | | | | | | | | | | | | | | | | Since the pending bit of host access interrupt is set frequently if PCH accesses KBC/PM_Channel/Shared Memory through LPC after entering S0. It's better to add checking enable bit of MIWU of it in case huge latency between gpio interrupt and serving its own ISR in INT11's ISR. Modified sources: 1. gpio.c: Add checking enable bit of MIWU of host access in INT11 ISR. BRANCH=none BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers Change-Id: I1ae57173eb208fa78218bc01cfbc91f9a29c5c81 Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/352362 Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* npcx: gpio: Don't increase priority of SHI_CS for non-SHI boardsShawn Nematbakhsh2016-06-081-0/+4
| | | | | | | | | | | | | | | | Systems that don't use SHI don't need elevated SHI_CS interrupt priority. BUG=None TEST=`make buildall -j` BRANCH=None Change-Id: Ica6e82332bc7ef8f92c00d847cd3ff0df7ede429 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/350570 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* kevin: rk3399: enabling RTC wakeupShelley Chen2016-05-231-1/+14
| | | | | | | | | | | | | | | | | | Enabled CONFIG_CMD_RTC_ALARM. EC_HOST_EVENT_RTC is enabled when the rtc_alarm goes off, alerting the AP to transition from S3->S0. BUG=chrome-os-partner:52218 BRANCH=None TEST=rtc_alarm <num> and see event set in ec console after <num> seconds. Also, check if new bit set through hostevent command in ec before/after rtc_alarm goes off. Change-Id: I53b1705ce0925000f35b9f80752035d198db3310 Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/345474 Reviewed-by: Shawn N <shawnn@chromium.org>
* npcx: Modify gpio's interrupt utilitiesMulin Chao2016-05-181-22/+14
| | | | | | | | | | | | | | | | | | | | | | Setting NVIC_EN register is not a suitable method if you want to turn on/off one GPIO's interrupt. Since there're eight sources belong to the same interrupt, using MIWU_EN register which bit belongs to one MIWU's source is a better way. Modified sources: 1. gpio.c: Replace accessing NVIC_EN register with MIWU_EN in gpio's interrupt utilities. BRANCH=none BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers Change-Id: I282a45f5a3ab7cb032b2282cf7e92cacc5e706b6 Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/342122 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Bill Richardson <wfrichar@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
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