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1. Add GPIO driver support for npcx9.
2. move the GPIO interrupt handler (MIWU) from gpio.h to gpio-npcx5.h,
gpio-npcx7.h, and gpio-npcx9.h separately.
Note: gpio-npcx7.h is a link to gpio-npcx5.h because almost all of the
source codes are the same.
BRANCH=none
BUG=b:165777478
TEST=pass "make buildall"
TEST=with related CLs, build and flash image on the npcx5/7/9 EVB and
yorp; verify GPIO functionality.
Signed-off-by: CHLin <CHLin56@nuvoton.com>
Change-Id: I665507f804ca3772f81f0ff8bd917a633bda2d11
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2402842
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: caveh jalali <caveh@chromium.org>
Commit-Queue: CH Lin <chlin56@nuvoton.com>
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Nuvoton NPCX79nxB serie chips include two UART ports.
In this CL, we add the driver support for these two UART modules.
Develoers can select one of the UART ports as EC console by configuring
"CONFIG_CONSOLE_UART" in board.h
BRANCH=none
BUG=none
TEST=No build errors for make buildall.
TEST="#define CONFIG_CONSOLE_UART 0"; build and flash image on npcx7 EVB;
check EC console working via J21.
TEST="#define CONFIG_CONSOLE_UART 1"; build and flash image on npcx7 EVB;
check EC console working via J22. (Note: J16.3-J16.5 and JP6.2-JP6.3
must be connected together.)
TEST=build images of board npcx_evb, poppy, and grunt, make sure EC
console is functional on these boards.
TEST=#define "CONFIG_CONSOLE_UART 0" and "CONFIG_UART_PAD_SWITCH" in
board.h; build and flash image on npcx7_evb. check uart_alt_pad_read_write
function still works by using the console command like:
https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/659460/1/board/poppy/board.c
Change-Id: I7de91680e5d4f56c7cae66482c0953d8c324dbe7
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/1113269
Commit-Ready: CH Lin <chlin56@nuvoton.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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It was found that for npcx ec's GPIOs that support low-voltage input,
there is an excessive power consumption when they are selected to
low-voltage mode and their Vin is 1.8V.
To bypass this issue when the chip enters deep sleep where current is
important, this CL includes:
1. Disable GPIOs without ISR which are selected to 1.8V and not i2c
ports in gpio_pre_init().
2. Disable input buffer of 1.8V i2c ports before entering deep sleep.
3. Enable input buffer of 1.8V i2c ports after ec wakes up.
BRANCH=none
BUG=b:110170824
TEST=No build errors for npcx ec series. Measured power consumption on
yorp and it saved ~1.3mA current after applying this patch at S0ix. Run
stress test on poppy and no symptom found. Remove CONFIG_LOW_POWER_IDLE
in board driver and no symptom occurred on poppy and yorp.
Change-Id: Iaf66c81ca16104839734ba19492f2061113dafb3
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/1098864
Reviewed-by: Jett Rink <jettrink@chromium.org>
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NPCX5* only has one UART controller, which can be switched
between 2 pads. We keep the default pad for EC console,
however, we allow switching to the alternate pad for short,
infrequent, transactions. Both pads are assumed to use the
same baudrate and other line settings.
When switching pad, we first configure the new pad, then switch
off the old one, to avoid having no pad selected at a given time,
see b/65526215#c26.
Because of the added complexity of npcx_gpio2uart (and the fact
that it uses the global variable "pad" define in uart.c), we
move the implementation to uart.c (npcx_uart2gpio is also moved
for consistency).
When the pad is switched to alternate pad, characters input
and output on the EC console (default pad) would be lost. To
compensate for this, we:
- Switch back to main pad in case of EC panic, so that output
is shown on EC console.
- Immediately abort current alternate pad transaction if a
character is received on the default pad. Note, however,
that the first character will be lost (this can be worked
around by telling user to press enter, and have servod/FAFT
always send 2 blank lines (instead of just one) before
sending a command).
- Inhibit pad switching for 500ms after receiving a character
on default pad. Assuming a reasonable typing speed, this
should allow developers to type console commands relatively
comfortably, while not starving the alternate pad communication
for too long.
The logic above could be simplified significantly by implementing
software flow control (XON/XOFF, see b/67026316).
BRANCH=none
BUG=b:65526215
TEST=While follow-up CL that writes long 1k buffers, the following
works fine:
- type 'uart' in EC console
- Read battery power consumption from servod, which "types" in
the EC console:
while true; do dut-control ppvar_vbat_mw; sleep 1; done
no failure is seen.
TEST=Add this test code in uart_alt_pad_read_write, after the pad
has been switched, and check that panic information is
consistently printed correctly:
{
static int t;
if (t++ > 20)
t = t / ret;
}
Change-Id: I18feed2f8ca4eb85f40389f77dac3a46315310e7
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/659458
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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This CL includes:
1. Add gpio_chip-npcx5/7.h files and move all macro functions
related to chip family to them. (Move wui macro func from
gpio_wui.h to them.)
2. Replace alternative and low-voltage mapping table with macro
function NPCX_ALT_TABLE and NPCX_LVOL_TABLE.
3. Add UART wakeup mechanism in __gpio_wk1h_interrupt() ISR.
4. Add gpio register definitions of npcx7 family in registers.h.
5. Add GPIO_LOCKED flag for lock functionality.
BRANCH=none
BUG=none
TEST=No build errors for all boards using npcx5 series (besides gru).
Build poppy board and upload FW to platform. No issues found.
Passed validation for all GPIO functionalities on npcx5m6g
and npcx796f evb.
Change-Id: I60c30ce223629a0d8cb767a54a0a9b02a69de9c5
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/481561
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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