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In the interest of making long-term branch maintenance incur as little
technical debt on us as possible, we should not maintain any files on
the branch we are not actually using.
This has the added effect of making it extremely clear when merging CLs
from the main branch when changes have the possibility to affect us.
The follow-on CL adds a convenience script to actually pull updates from
the main branch and generate a CL for the update.
BUG=b:204206272
BRANCH=ish
TEST=make BOARD=arcada_ish && make BOARD=drallion_ish
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I17e4694c38219b5a0823e0a3e55a28d1348f4b18
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3262038
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Tom Hughes <tomhughes@chromium.org>
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In npcx5/7, we use two reserved bits in the BSC1 register (offset 0x07
of the MDC register) to indicate what the current image copy is.
In npcx9, these two bits are used by the booter. We need to change them
to another two empty scratch bits which are not used by the booter.
BUG=b:165777478, b:200642229
BRANCH=none
TEST=pass "make buildall"
TEST=check the related bits changed by "sysump ro" and "sysjump rw"
TEST=jump to RW & check sysinfo after reset-pin/watchdog/debug reset
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Signed-off-by: Wealian Liao <whliao@nuvoton.corp-partner.google.com>
Change-Id: I9801efe7fe7645e7b81df9c5cc69372df0a178a8
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3178700
Tested-by: caveh jalali <caveh@chromium.org>
Reviewed-by: Yuval Peress <peress@google.com>
Reviewed-by: caveh jalali <caveh@chromium.org>
Commit-Queue: caveh jalali <caveh@chromium.org>
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This reverts commit 20222d48571fa44c76fdb0ededd0ed042e9f8244.
Reason for revert: brya thinks it's in EC-RW when it's really still in EC-RO.
Original change's description:
> npcx: correct the image copies indication bits for npcx9
>
> In npcx5/7, we use two reserved bits in the BSC1 register (offset 0x07
> of the MDC register) to indicate what the current image copy is.
> In npcx9, these two bits are used by the booter. We need to change them
> to another two empty scratch bits which are not used by the booter.
>
> BUG=b:165777478
> BRANCH=none
> TEST=pass "make buildall"
> TEST=check the related bits changed by "sysump ro" and "sysjump rw"
>
> Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
> Change-Id: I6bcfe6d8752c6fa10022a21956d2e0ceb7f9418e
> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3153119
> Tested-by: CH Lin <chlin56@nuvoton.com>
> Reviewed-by: caveh jalali <caveh@chromium.org>
> Auto-Submit: CH Lin <chlin56@nuvoton.com>
> Commit-Queue: caveh jalali <caveh@chromium.org>
Bug: b:165777478
Change-Id: I24cdfec0d5c8cd998f087525ae21b2a3daea43a7
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3172266
Bot-Commit: Rubber Stamper <rubber-stamper@appspot.gserviceaccount.com>
Tested-by: caveh jalali <caveh@chromium.org>
Commit-Queue: caveh jalali <caveh@chromium.org>
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In npcx5/7, we use two reserved bits in the BSC1 register (offset 0x07
of the MDC register) to indicate what the current image copy is.
In npcx9, these two bits are used by the booter. We need to change them
to another two empty scratch bits which are not used by the booter.
BUG=b:165777478
BRANCH=none
TEST=pass "make buildall"
TEST=check the related bits changed by "sysump ro" and "sysjump rw"
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Change-Id: I6bcfe6d8752c6fa10022a21956d2e0ceb7f9418e
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3153119
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: caveh jalali <caveh@chromium.org>
Auto-Submit: CH Lin <chlin56@nuvoton.com>
Commit-Queue: caveh jalali <caveh@chromium.org>
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There is a workaround to disable the JTAG selection when the JTAG is
enabled unexpectedly by the strap pin. In npcx9, the register to control
the JTAG selection is different. This CL uses the correct register to
let the workaround work correctly.
BRANCH=none
BUG=b:165777478
TEST=pass "make buildall"; check the register is correctly configured;
check JTAG can be disabled when "CONFIG_ENABLE_JTAG_SELECTION" is not
defined and JEN strap pin is pulled down on npcx9_evb.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Change-Id: Ic7a8a7d99335610cbacfb1de285cdd8fbda70848
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2867125
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: caveh jalali <caveh@chromium.org>
Reviewed-by: Keith Short <keithshort@chromium.org>
Commit-Queue: CH Lin <chlin56@nuvoton.com>
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Fixed NPCX_ESPICFG_IOMODE_FIELD and NPCX_ESPICFG_MAXFREQ_FIELD field
length. Added missing bits for ESPICFG and ESPIERR.
BUG=None
TEST=Build
BRANCH=None
Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I99d890804ea7eb4394b64684c03d111371000942
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2784842
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
Reviewed-by: Diana Z <dzigterman@chromium.org>
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1. In npcx7, the PSL (hibernation) wakeup source only can come from
physical PSL_IN pins. In npcx9, the LCT (Long Countdown Timer)
module is introduced to support wakeup from a configurable timeout.
2. support PSL wakeup from the VCC1_RST pin. This function is disabled
by default and enabled (and locked) in the firmware in the npcx9 A1
chip. In the npcx9 A2 chip, this function is enabled (and locked)
by booter.
3. Support pulse mode and open drain (if pulse mode is enabled) for
PSL_OUT pin.
4. support one PSL general-purpose output pin which is powered by VSBY.
BRANCH=none
BUG=b:165777478
TEST=pass "make buildall"
TEST="hibernate 10", check EC wakes up from hibernate after 10 seconds.
make sure the reset cause in the console is "power-on hibernate
rtc-alarm"
TEST="hibernate"; check EC wakes up from hibernate after pressing
VCC1_RST button on the internal test board.
Test=configure the PSL_OUT to pulse mode and "hibernate"; cut off VCC1
power; check EC can wake up from hibernate with any input event.
Test=configure the level of PSL_GPO before hibernation; check the level
is kept after entering hibernation.
Signed-off-by: Wealian Liao <whliao@nuvoton.corp-partner.google.com>
Signed-off-by: CHLin <CHLin56@nuvoton.com>
Change-Id: I98ad41da8557222cf3d09fef9524880731cecde1
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2435164
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: caveh jalali <caveh@chromium.org>
Commit-Queue: CH Lin <chlin56@nuvoton.com>
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This CL makes the following changes to support npcx9.
1. Split the CHIP_FAMILY specific register setting form register.h to
register-npcx5.h and register-npcx7.h.
2. Add npcx9's specific register setting in registers-npcx9.h
3. In npcx9, all 16-bit timers are removed from ITIM module. Change
the hwtimer driver to use 32-bit timer for npcx9.
The table shows the supported and current use of ITIM modules in the
system:
NPCX5/7 NPCX9
Change-Id: I1d00cbb8d36bff37563cfeaf78e338286e779b00
-------------------|---------------------|--------------------|
Supported ITIMs | ITIM16_1-ITIM16_6 | ITIM32_1-ITIM32_6 |
| ITIM32 | |
-------------------|---------------------|--------------------|
System tick timer | ITIM32 | ITIM32_6 |
-------------------|---------------------|--------------------|
Event timer | ITIM16_1 | ITIM32_1 |
-------------------|---------------------|--------------------|
Watchdog timer | ITIM16_5 | ITIM32_5 |
BRANCH=none
BUG=b:165777478
TEST=pass "make buildall"
TEST=boot up EC on the npcx7/npcx9 EVB. Check HOOT_SECOND function is
working; EC watchdog resets after console command "waitms 4000"
TEST=build and flash image for yorp, no symptom occurred.
Signed-off-by: CHLin <CHLin56@nuvoton.com>
Change-Id: Ibf0fa5fa44590de6bb3e1bff677f40aafd70b556
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2402840
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Keith Short <keithshort@chromium.org>
Commit-Queue: CH Lin <chlin56@nuvoton.com>
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