| Commit message (Collapse) | Author | Age | Files | Lines |
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This CL will add macros used to set MIWU interrupt priorities. These
macro can be set by each board to adjust priorities as needed.
BUG=b:279918234
TEST=build agah
Change-Id: Ide840e4ab8cc9aa8deb83b6ad76fa64bc0d83972
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4518230
Auto-Submit: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
Commit-Queue: Daisuke Nojiri <dnojiri@chromium.org>
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Sort all includes in chip with the clang-format rules used by
the zephyr project.
BRANCH=None
BUG=b:247100970
TEST=zmake build -a
TEST=./twister --clobber -v -i
TEST=make -j72 buildall_only runtests
TEST=zmake compare-builds -a
Signed-off-by: Jeremy Bettis <jbettis@google.com>
Change-Id: I13454e38fa3766aa0ba26a058075f51965b8462e
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4053346
Code-Coverage: Zoss <zoss-cl-coverage@prod.google.com>
Commit-Queue: Jeremy Bettis <jbettis@chromium.org>
Tested-by: Jeremy Bettis <jbettis@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
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Normally we don't do this, but enough changes have accumulated that
we're doing a tree-wide one-off update of the name & style.
BRANCH=none
BUG=chromium:1098010
TEST=`repo upload` works
Change-Id: Icd3a1723c20595356af83d190b2c6a9078b3013b
Signed-off-by: Mike Frysinger <vapier@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3891203
Reviewed-by: Jeremy Bettis <jbettis@chromium.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
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BUG=b:236386294
BRANCH=none
TEST=none
Change-Id: I7063e3b6c6c9845b685ef4ca7b32aef89601a807
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3729428
Reviewed-by: Jeremy Bettis <jbettis@chromium.org>
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Enabling an eSPI channel (r.g. Peripheral Channel, Virtual Wire Channel,
etc.) during an eSPI transaction might (with low probability) cause the
eSPI_SIF module to transition to a wrong state and therefore respond
with FATAL_ERROR on an incoming transaction.
This CL workarounds this issue by clearing the bit 4 of NPCX eSPI
specific register#2.
This workaround should be also applied to NPCX7 (except npcx7m6f).
The Zephyr PR:https://github.com/zephyrproject-rtos/zephyr/pull/45294
also fixes this issue.
BRANCH=none
BUG=b:231667217
TEST=pass "make buildall -j4"
TEST=Test on Volteer, make sure the platform bootup to ChromeOS.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Change-Id: If929fe48246e0902b182143031f99af019fca1f0
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3626850
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Keith Short <keithshort@chromium.org>
Reviewed-by: caveh jalali <caveh@chromium.org>
Reviewed-by: Amit Maoz <Amit.Maoz@nuvoton.com>
Commit-Queue: CH Lin <chlin56@nuvoton.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
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This CL sets the power down bit for unused module SDP and I3C to
get better power efficiency.
BUG=b:219388463
BRANCH=none
TEST=pass "make buiilall"
TEST=observe registers by "rw .b 0x4000d008" and "rw .b 0x4000d025"
berfore/after this CL.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Change-Id: Idc399af40588a650e9031c6eadffc70c058d4ac4
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3467378
Reviewed-by: Keith Short <keithshort@chromium.org>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: caveh jalali <caveh@chromium.org>
Commit-Queue: caveh jalali <caveh@chromium.org>
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In npcx5/7, we use two reserved bits in the BSC1 register (offset 0x07
of the MDC register) to indicate what the current image copy is.
In npcx9, these two bits are used by the booter. We need to change them
to another two empty scratch bits which are not used by the booter.
BUG=b:165777478, b:200642229
BRANCH=none
TEST=pass "make buildall"
TEST=check the related bits changed by "sysump ro" and "sysjump rw"
TEST=jump to RW & check sysinfo after reset-pin/watchdog/debug reset
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Signed-off-by: Wealian Liao <whliao@nuvoton.corp-partner.google.com>
Change-Id: I9801efe7fe7645e7b81df9c5cc69372df0a178a8
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3178700
Tested-by: caveh jalali <caveh@chromium.org>
Reviewed-by: Yuval Peress <peress@google.com>
Reviewed-by: caveh jalali <caveh@chromium.org>
Commit-Queue: caveh jalali <caveh@chromium.org>
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This reverts commit 20222d48571fa44c76fdb0ededd0ed042e9f8244.
Reason for revert: brya thinks it's in EC-RW when it's really still in EC-RO.
Original change's description:
> npcx: correct the image copies indication bits for npcx9
>
> In npcx5/7, we use two reserved bits in the BSC1 register (offset 0x07
> of the MDC register) to indicate what the current image copy is.
> In npcx9, these two bits are used by the booter. We need to change them
> to another two empty scratch bits which are not used by the booter.
>
> BUG=b:165777478
> BRANCH=none
> TEST=pass "make buildall"
> TEST=check the related bits changed by "sysump ro" and "sysjump rw"
>
> Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
> Change-Id: I6bcfe6d8752c6fa10022a21956d2e0ceb7f9418e
> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3153119
> Tested-by: CH Lin <chlin56@nuvoton.com>
> Reviewed-by: caveh jalali <caveh@chromium.org>
> Auto-Submit: CH Lin <chlin56@nuvoton.com>
> Commit-Queue: caveh jalali <caveh@chromium.org>
Bug: b:165777478
Change-Id: I24cdfec0d5c8cd998f087525ae21b2a3daea43a7
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3172266
Bot-Commit: Rubber Stamper <rubber-stamper@appspot.gserviceaccount.com>
Tested-by: caveh jalali <caveh@chromium.org>
Commit-Queue: caveh jalali <caveh@chromium.org>
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In npcx5/7, we use two reserved bits in the BSC1 register (offset 0x07
of the MDC register) to indicate what the current image copy is.
In npcx9, these two bits are used by the booter. We need to change them
to another two empty scratch bits which are not used by the booter.
BUG=b:165777478
BRANCH=none
TEST=pass "make buildall"
TEST=check the related bits changed by "sysump ro" and "sysjump rw"
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Change-Id: I6bcfe6d8752c6fa10022a21956d2e0ceb7f9418e
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3153119
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: caveh jalali <caveh@chromium.org>
Auto-Submit: CH Lin <chlin56@nuvoton.com>
Commit-Queue: caveh jalali <caveh@chromium.org>
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BRANCH=none
BUG=b:163885307
TEST=compare_build.sh matches
Change-Id: I50d4263e93945ec0f3fd2d655fd173aa8a666d8f
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3060261
Reviewed-by: Boris Mittelberg <bmbm@google.com>
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This renames IS_SLAVE_CHAN_ENABLE to IS_PERIPHERAL_CHAN_ENABLE.
BRANCH=none
BUG=b:163885307
TEST=buildall and compare_build.sh pass
Change-Id: Iaab11a2485fdcde3992ecb457c204465acfdf732
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2938042
Reviewed-by: Harry Cutts <hcutts@chromium.org>
Commit-Queue: Harry Cutts <hcutts@chromium.org>
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There is a workaround to disable the JTAG selection when the JTAG is
enabled unexpectedly by the strap pin. In npcx9, the register to control
the JTAG selection is different. This CL uses the correct register to
let the workaround work correctly.
BRANCH=none
BUG=b:165777478
TEST=pass "make buildall"; check the register is correctly configured;
check JTAG can be disabled when "CONFIG_ENABLE_JTAG_SELECTION" is not
defined and JEN strap pin is pulled down on npcx9_evb.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Change-Id: Ic7a8a7d99335610cbacfb1de285cdd8fbda70848
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2867125
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: caveh jalali <caveh@chromium.org>
Reviewed-by: Keith Short <keithshort@chromium.org>
Commit-Queue: CH Lin <chlin56@nuvoton.com>
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eSPI PUT_IOWR_SHORT protocol can send a max of 4 bytes of data in a
single transaction. This allows the host to send 4 bytes of the Port80
code at one time. This CL sets the bit OFS0_SEL~OFS3_SEL in the DPAR1
register to let the EC hardware put full 4-bytes of Port80 code to
DP80BUF FIFO. It also groups the 4-byte code into a single 32-bits
variable when necessary by analyzing the offset field in the DP80BUF
register.
BRANCH=none
BUG=b:184872297
TEST=build the image with "#define CONFIG_PORT80_PRINT_IN_INT 1";
connect npcx9_evb to the eSPI host emulator; the host sends a
PUT_IOWR_SHORT transaction to IO address 0x80 with 4 bytes of code
"0xEEE20400"; the EC console shows:
[63.694685 Port 80: 0xeee20400]
Then the host sends a single byte "0xaa" to Port80, the EC console
prints:
[576.531790 Port 80: 0xaa]
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Change-Id: I5dfbc0d08172042cb43d72eeb6f0e7da63feccf0
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2847668
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Raul E Rangel <rrangel@chromium.org>
Commit-Queue: CH Lin <chlin56@nuvoton.com>
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Fixed NPCX_ESPICFG_IOMODE_FIELD and NPCX_ESPICFG_MAXFREQ_FIELD field
length. Added missing bits for ESPICFG and ESPIERR.
BUG=None
TEST=Build
BRANCH=None
Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I99d890804ea7eb4394b64684c03d111371000942
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2784842
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
Reviewed-by: Diana Z <dzigterman@chromium.org>
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This sets a default value of 0 for NPCX_UART_MODULE2 and
NPCX9_PWM1_SEL so that board files don't need to set these.
BRANCH=none
BUG=b:173575131
TEST=buildall
Change-Id: Ief84ed558bb5431f13fb01b963db3bd97fc8d659
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2546639
Reviewed-by: CH Lin <chlin56@nuvoton.corp-partner.google.com>
Reviewed-by: Keith Short <keithshort@chromium.org>
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This CL makes the following changes to support npcx9.
1. Split the CHIP_FAMILY specific register setting form register.h to
register-npcx5.h and register-npcx7.h.
2. Add npcx9's specific register setting in registers-npcx9.h
3. In npcx9, all 16-bit timers are removed from ITIM module. Change
the hwtimer driver to use 32-bit timer for npcx9.
The table shows the supported and current use of ITIM modules in the
system:
NPCX5/7 NPCX9
Change-Id: I1d00cbb8d36bff37563cfeaf78e338286e779b00
-------------------|---------------------|--------------------|
Supported ITIMs | ITIM16_1-ITIM16_6 | ITIM32_1-ITIM32_6 |
| ITIM32 | |
-------------------|---------------------|--------------------|
System tick timer | ITIM32 | ITIM32_6 |
-------------------|---------------------|--------------------|
Event timer | ITIM16_1 | ITIM32_1 |
-------------------|---------------------|--------------------|
Watchdog timer | ITIM16_5 | ITIM32_5 |
BRANCH=none
BUG=b:165777478
TEST=pass "make buildall"
TEST=boot up EC on the npcx7/npcx9 EVB. Check HOOT_SECOND function is
working; EC watchdog resets after console command "waitms 4000"
TEST=build and flash image for yorp, no symptom occurred.
Signed-off-by: CHLin <CHLin56@nuvoton.com>
Change-Id: Ibf0fa5fa44590de6bb3e1bff677f40aafd70b556
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2402840
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Keith Short <keithshort@chromium.org>
Commit-Queue: CH Lin <chlin56@nuvoton.com>
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Add the following changes:
1. add CHIP_VARIANT_NPCX7M7WC in the npcx7 chip configuration files to
define what (RAM, flash, features...) are supported in npcx7m7fc.
2. add the chip id and chip revision id of npcx7m7fc
BRANCH=none
BUG=b:163910671
TEST=pass "make buildall"
TEST=with related CLs, change CHIP_VARIANT to npcx7m7fc in
board/npcx7_evb/build.mk; flash image and run on the internal testing board of
npcx7m7fc; make sure the EC can boot up; check the chip ID and chip
revision ID are correct by console command "version".
Signed-off-by: CHLin <CHLin56@nuvoton.com>
Change-Id: Ibef17148eeba71bbbb63145064a5fa398c0118dc
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2355156
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: caveh jalali <caveh@chromium.org>
Reviewed-by: Keith Short <keithshort@chromium.org>
Commit-Queue: CH Lin <chlin56@nuvoton.com>
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Add CONFIG_HIBERNATE_WAKE_PINS_DYNAMIC to let board config
their wake pins at runtime.
BUG=b:162814191
TEST=make
BRANCH=master
Signed-off-by: Ting Shen <phoenixshen@google.com>
Change-Id: Iae2072ec7239a0daa84222c23733b90153e732f1
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2340730
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Commit-Queue: Ting Shen <phoenixshen@chromium.org>
Tested-by: Ting Shen <phoenixshen@chromium.org>
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Google is working to change its source code to use more inclusive
language. To that end, replace the term "dummy" with inclusive
alternatives.
BUG=b:162781382
BRANCH=None
TEST=make -j buildall
`grep -ir dummy *`
The only results are in "private/nordic_keyboard/sdk8.0.0"
which is not our code.
Signed-off-by: Sam Hurst <shurst@google.com>
Change-Id: I6a42183d998e4db4bb61625f962867fda10722e2
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2335737
Reviewed-by: Tom Hughes <tomhughes@chromium.org>
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The Nuvoton NPCX EC series support a threshold event detector for the
ADC channels. There are three threshold event detectors and they can be
mapped to any ADC channel. The block compares the measured voltage
input to either a programmable threshold or a pair of thresholds and
generates an interrupt if the measured voltage is above or below the
thresholds.
This commit adds support for this feature. A new structure is created,
npcx_adc_thresh_t which allows a board to define the ADC channel that
should be monitored, the assertion and deassertion thresholds, a
callback that can be run when the interrupt fires and a flag for
whether or not the interrupt should fire if the measured value is above
or below the threshold.
BUG=b:148169171
BRANCH=None
TEST=Enable on waddledoo, verify that the ADC dual threshold interrupt
functionality works.
Change-Id: I5a3e517207a71b1298865fe36b80cc6298567e9e
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2030204
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Diana Z <dzigterman@chromium.org>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
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Morphius connects the trackpoint device to EC via the PS/2 interface.
To support it, we implemented the chip level PS/2 driver in this CL.
The PS/2 driver can be used on all series of NPCX EC chips (NPCX5/7).
BUG=b:145575366
BRANCH=none
TEST=No error for "make buildall"
TEST=Apply this and related CLs, connect npcx5/npcx7 EVBs to standard
PS/2 keyboards and PS/2 device emulator with different channels. Verify
that the PS/2 write/read transaction can keep working for several hours
without issue.
Change-Id: I5bae313db2d697999c2da5cf33478be2da754b8c
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1982302
Tested-by: CH Lin <chlin56@nuvoton.com>
Commit-Queue: Edward Hill <ecgh@chromium.org>
Auto-Submit: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Edward Hill <ecgh@chromium.org>
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1. Uses DEBUG_AUDIO_CODEC instead of DEBUG_WOV.
2. Moves console commands under DEBUG_AUDIO_CODEC (saves ~3KB).
BRANCH=none
BUG=b:144064048, b:144063867
TEST=make BOARD=trembyle -j
Change-Id: Ic5b3442809506d71a333b5c1c9cc0dd4776d98bb
Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1986688
Commit-Queue: Yu-Hsuan Hsu <yuhsuan@chromium.org>
Tested-by: Yu-Hsuan Hsu <yuhsuan@chromium.org>
Reviewed-by: Edward Hill <ecgh@chromium.org>
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In npcx7, all I2C modules have separate 32-byte transmit FIFO and
32-byte receive FIFO buffers. In this CL, we add the FIFO mode support
to the I2C driver. This will help to reduce the firmware overhead (i.e.
the occurrence of I2C interrupt) during long I2C transactions by allowing
the EC to write/read more than one byte of data at one time to I2C
module and hence improve the I2C performance.
The FIFO mode is enabled by default on all npcx7 series chips.
BUG=none
BRANCH=none
TEST=No error for "make buildall"
TEST=Connect npcx7 EVB to the I2C slave emulator, do stress test:
1. iterate ~2000 times of single i2c_xfer_unlocked API call.
i.e.
i2c_xfer_unlocked(.., I2C_XFER_SINGLE)
2. iterate ~2000 times of multiple i2c_xfer_unlocked API calls:
i.e.
i2c_xfer_unlocked(.., I2C_XFER_START)
i2c_xfer_unlocked(.., 0)
.
.
i2c_xfer_unlocked(.., I2C_XFER_STOP)
3. Issue 6 I2C transactions by 6 tasks at the same time.
iterates ~2000 times.
TEST=with this CL; build and upload an image (with/without FIFO mode
enabled.) to yorp; no symptom occurs.
Change-Id: I387e8ef6e619acef670273f08ab4150e3d2b75f2
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1827137
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Commit-Queue: CH Lin <chlin56@nuvoton.com>
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BUG=none
BRANCH=none
TEST=buildall
Change-Id: I7f9089ce8028f12a94d8e73dd58a5bb36ebc614f
Signed-off-by: Edward Hill <ecgh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1862090
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
Commit-Queue: Denis Brockus <dbrockus@chromium.org>
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In the original firmware (in the uart_buffering.c), it clears the
SLEEP_MASK_UART immediately after it pushes all characters from its Tx
buffer to UART's FIFO without checking the status of transmission. It
may break the transmission because EC goes to deep sleep before UART TX
(FIFO or shift register) becomes empty. This CL fixes it by:
(1) Don't clear SLEEP_MASK_UART immediately when uart_tx_stop is called.
(2) Enable the NXMIP (No Transmit in Progress) interrupt.
(3) Clear SLEEP_MASK_UART in the UART interrupt handler when NXMIP is
set.
This fix only needs to apply to NPCX7 chips which have UART FIFO support.
BRANCH=none
BUG=b:137143640
TEST=No error for "make buildall"
TEST=run 10 iterations of uart_stress_tester on yorp with command:
./util/uart_stress_tester.py /dev/ttyUSB2 -t 360;
make sure no character lost in each iteration as below:
...
INFO | UartSerial| /dev/ttyUSB2 | Detected as EC UART
INFO | UartSerial| EC | Ready to test
INFO | ChargenTest | Ports are ready to test
INFO | ChargenTest | Test starts
INFO | UartSerial| EC | Test thread starts
INFO | UartSerial| EC | Test thread is done
INFO | UartSerial| EC | 0 char lost / 4147200 (0.0 %)
INFO | ChargenTest | PASS: lost 0 character(s) from the test
INFO | ChargenTest | Test is done
Change-Id: I97b1f572e8b9ebdb5102aa3e98ae2963d768b5b3
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1703944
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Namyoon Woo <namyoon@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Commit-Queue: CH Lin <chlin56@nuvoton.com>
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Ran the following command:
git grep -l 'Copyright (c)' | \
xargs sed -i 's/Copyright (c)/Copyright/g'
BRANCH=none
BUG=none
TEST=make buildall -j
Change-Id: I6cc4a0f7e8b30d5b5f97d53c031c299f3e164ca7
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1663262
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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It was observed that pressing recovery key combination + the other
keys, some keys on the keyboard become invalid after system reboots.
(see b:129908668 for more detail.)
It is because the hardware strap pin for JTAG0 signals is
unintentionally triggered. This CL reverts the selection of JTAG signals
and set them back to keyboard scan function at system initialization.
The revert applies to all real platforms except npcx_evbs.
BRANCH=none
BUG=b:129908668
TEST=pass "make buildall"
TEST=Press the specific key combination, after the system reboots,
the keyboard function works normally. On npcx EVBs, the JTAG0 is still
functional.
Change-Id: I7ede1ea4609466fea50a97b1f60308e4cdfd4544
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/1575887
Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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This CL includes the following changes:
1. add CHIP_VARIANT_NPCX7M7WC in the npcx7 chip configuration files to
define what (RAM, features...) is supported in npcx7m7wc.
2. add the chip id and chip revision id of npcx7m7wc.
3. re-organize the memory of npcx7m7wb from:
current: 320 KB code RAM + 64 KB data RAM.
to : 256 KB code RAM + 128 KB data RAM.
The reason is that the extra 64 KB RAM is excepted to store the WoV
voice data when it operates under RAM mode. Under the limitation of
current memory layout, the 64 KB voice buffer is declared as const
to force it allocated in the code section, which is strange.
This can be fixed after changing the layout.
BRANCH=none
BUG=none
TEST=pass "make buildall"
TEST=with related CLs, change CHIP_VARIANT to npcx7m7wc in
board/npcx7_evb/build.mk; flash image in the internal testing board of
npcx7m7wc; make sure the EC can boot up; check the chip ID and chip
revision ID are correct by console command "version".
TEST=build npcx7m7wb image and test it on npcx7_evb, no symptom found.
Change-Id: I7533c1f5490e151571696ac615da2d0430827a78
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/1543062
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
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Mechanical replacement of bit operation where operand is a constant.
More bit operation exist, but prone to errors.
Reveal a bug in npcx:
chip/npcx/system-npcx7.c:114:54: error: conversion from 'long unsigned int' to 'uint8_t' {aka 'volatile unsigned char'} changes value from '16777215' to '255' [-Werror=overflow]
BUG=None
BRANCH=None
TEST=None
Change-Id: I006614026143fa180702ac0d1cc2ceb1b3c6eeb0
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1518660
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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Requested for linux integration, use BIT instead of 1 <<
First step replace bit operation with operand containing only digits.
Fix an error in motion_lid try to set bit 31 of a signed integer.
BUG=None
BRANCH=None
TEST=compile
Change-Id: Ie843611f2f68e241f0f40d4067f7ade726951d29
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1518659
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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Include compile_time_macros.h to files that will use BIT macro.
BUG=None
BRANCH=None
TEST=unit tests.
Change-Id: I9d44f4b588620f6770f8d522d422f5dd0d237903
Signed-off-by: Gwendal Grignou <gwendal@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1525156
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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This CL includes:
1. add CHIP_VARIANT_NPCX7M6FC in the npcx chip configuration files to
define what (RAM, features...) is supported in npcx7m6fc.
2. add the chip id and chip revision id of npcx7m6fc.
BRANCH=none
BUG=none
TEST=No build errors for make buildall.
TEST=Change CHIP_VARIANT to npcx7m6fc in board/npcx7_evb/build.mk;
flash image in the internal testing board of npcx7m6fc; make sure the
EC can boot up. Check the chip ID and chip revision ID are correct by
console command "version".
TEST=build and flash the yorp image to the platform; make sure no issues
are found.
Change-Id: Ibcb25fc09b21ec3e5738418af16826035ec81e69
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/1343639
Commit-Ready: CH Lin <chlin56@nuvoton.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Jett Rink <jettrink@chromium.org>
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In npcx5/npcx7m6g/npcx7m6f, clearing the IBBR bit in the BKUP_STS
register is not hazardous because the register only implements the IBBR
bit. In npcx7m6fb/npcx7m7wb, the register implements two more bits
(VSBY_STS/VCC1_STS). Using read-modify-write operation to clear IBBR bit
will also clear these two bits unexpected if they are set. It is fine at
this time because the firmware does not rely on these two new bits for
any purpose. But it will be better to change it in case these two bits
are used in the future.
This CL also clears VSBY_STS/VCC1_STS bit (for npcx7m6fb/npcx7m7wb) when
power-on reset.
BRANCH=none
BUG=none
TEST=No build error for make buildall; Check IBBR(VSBY_STS/VCC1_STS)
are cleared at initial when power-on reset. Check warining messages are
printed and IBBR bit is cleared (in function system_check_bbram_on_reset
and bbram_valid).
Change-Id: I6dc1f5d7f35f9d591db62d1b022ea7b8d92f5b92
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/1235733
Commit-Ready: CH Lin <chlin56@nuvoton.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Jonathan Brandmeyer <jbrandmeyer@chromium.org>
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This change updates the erase operation in npcx chip to use 64k/32k/4k
block erase depending upon the alignment of CONFIG_RO_SIZE. This helps
reduce the EC SW sync time from ~9.5 seconds to ~5.4 seconds on NPCX7.
Ideally, we would want to check the offset and size of region to be
erased dynamically and decide which erase operation to use. However,
common flash code checks against CONFIG_FLASH_ERASE_SIZE to ensure
that the area being erased is aligned to that size. Thus, even if we
add dynamic erase at chip level, it isn't going to help.
This change also updates CONFIG_FLASH_BANK_SIZE to be the same as
CONFIG_FLASH_ERASE_SIZE since it is checked by common code. I am
honestly not sure why the CONFIG_FLASH_BANK_SIZE is tightly coupled
with CONFIG_FLASH_ERASE_SIZE. But, based on the usage, it seems to be
a safe change.
On the other hand, changing CONFIG_FLASH_BANK_SIZE helps reduce the
write time as well, thus overall helping with the EC SW Sync time.
Please see go/cros-npcx7-ec-sw-sync for more details.
BUG=b:113530328
BRANCH=nocturne
TEST=Verified that EC SW sync time goes down from 9.5 seconds to 5.4
seconds.
Change-Id: I5908eeeb3e4207a27abe804db8eb9d39ef9d73c4
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1195598
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
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Firmware bugs fix:
----------------------------------------------------------------------
1. wov mode change is malfunctional.
2. wov_set_mic_source set in VAD_0.VAD_INSEL field 0x3 when requested
wov_mic_source is WOV_SRC_STEREO.
3. wov_set_mic_source doesn't disable I2S channel 1 when using only
left or right channel.
4. wov_start/stop_ram_capture is called when needed by the driver,
it is used in wov_set_mode.
5. Never activate Automatic wake-up enabled. VAD_0.VAD_ADC_WAKEUP
remain '0' forever.
6. Set DMIC clock signal output to use fast transitions.
(set DEVALTE.DMCLK_FAST to be '1').
7. for VAD and RAM modes, DMIC clock setting should be 750 KHz.
8. for I2S mode (and RAM and I2S mode), DMIC clock should be 3 MHz.
9. fix issue "WoV driver may cause unsynchronized data in the I2S output"
10. fMUL2 clock tuning to LFCLK reference remain enabled when FMUL2 is enabled.
11. core-FIFO status bits in WOV_STATUS register are cleared when FIFO is reset.
12. i2S-FIFO status bits in WOV_STATUS register are cleared when FIFO is reset.
13. reset I2S FIFO when FIFO is underrun.
14. increase delay to 1msec when resets the FIFOs.
15. set MIC source prior start capturing data.
16. fix issue "enables ADC path in VAD mode when it isn't needed"
17. Increase delay in all places from 10Usec to 100Usec
Firmware enhancement:
----------------------------------------------------------------------
1. Add support for DMIC clock rate of 750 KHz and 1.2 MHz.
2. Add console command to enable/disable fmul2 tunning.
> wov fmul2 <enable|disable>
3. Originally, the console command "wov cfgmod ram" will tie the
function wov_set_mode(WOV_MODE_RAM) and start RAM capture together.
In the CL, we split it into two console commands:
> wov cfgmod ram
> wov capram
4. Add APIs to set DMIC clk rate for different mode (VAD/RAM/I2S) and
thier related console commands.
> cfgdckV <0.75|1.0|1.2|2.4|3.0>
> cfgdckR <0.75|1.0|1.2|2.4|3.0>
> cfgdckI <0.75|1.0|1.2|2.4|3.0>
This change allows to modify setting (ex: fmul2 tunning on/off) after
the wov mode is set to RAM and before the voice capture to RAM starts.
BRANCH=none
BUG=b:74600211, b:74617334, b:72213375
TEST=No build errors for make buildall.
TEST=Test bugs described above are fixed.
TEST=Test enhancement described above is well functional.
Change-Id: Id97b51fbd3e6e495d48aedf000a427538d91adf7
Signed-off-by: Dror Goldstein <dror.goldstein@nuvoton.com>
Signed-off-by: Simon Liang <CMLiang@nuvoton.com>
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/942286
Commit-Ready: CH Lin <chlin56@nuvoton.corp-partner.google.com>
Tested-by: CH Lin <chlin56@nuvoton.corp-partner.google.com>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Scott Collyer <scollyer@chromium.org>
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This CL changes the default value of Nuvoton internal register,
FMUL_WIN_DLY, from 0x8A to 0x81 on npcx7 ec series. It increases the tuning rate
of the FMULs to improve audio quality. For consistency, this is done across all
NPCX7 devices.
BRANCH=none
BUG=b:74600211
TEST=make buildall; Run cold-reset stress test over 3 days on grunt. No symptoms
occurred.
Change-Id: I5ad0c115da4254413d43269140eb71092c11b3b2
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/1134815
Reviewed-by: Jett Rink <jettrink@chromium.org>
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Nuvoton NPCX79nxB serie chips include two UART ports.
In this CL, we add the driver support for these two UART modules.
Develoers can select one of the UART ports as EC console by configuring
"CONFIG_CONSOLE_UART" in board.h
BRANCH=none
BUG=none
TEST=No build errors for make buildall.
TEST="#define CONFIG_CONSOLE_UART 0"; build and flash image on npcx7 EVB;
check EC console working via J21.
TEST="#define CONFIG_CONSOLE_UART 1"; build and flash image on npcx7 EVB;
check EC console working via J22. (Note: J16.3-J16.5 and JP6.2-JP6.3
must be connected together.)
TEST=build images of board npcx_evb, poppy, and grunt, make sure EC
console is functional on these boards.
TEST=#define "CONFIG_CONSOLE_UART 0" and "CONFIG_UART_PAD_SWITCH" in
board.h; build and flash image on npcx7_evb. check uart_alt_pad_read_write
function still works by using the console command like:
https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/659460/1/board/poppy/board.c
Change-Id: I7de91680e5d4f56c7cae66482c0953d8c324dbe7
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/1113269
Commit-Ready: CH Lin <chlin56@nuvoton.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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ID pins are considered additional KSOs while keycode scanning works
for the existing KSI0 ~ KSI7. While diriving ID pins, the state of
interconnection between ID pins and KSI pins could be used for
identifiers to tell keyboard itself. (e.g. US, Japan,and UK keyboard)
BRANCH=master
BUG=b:80168723
TEST="make -j buildall"
TEST=Verified 5 distinct keyboard samples w/ different Language ID values
on the same reworked Coral, which VOL_UP and VOL_DOWN were reworked
for ID pins. crrev.com/c/1053617 is my experimental patch on top of
this for further verification
Change-Id: I1d6e647df74c50d60bc1264c045b2587d0bf23d8
Signed-off-by: paris_yeh <pyeh@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1068951
Commit-Ready: Paris Yeh <pyeh@chromium.org>
Tested-by: Paris Yeh <pyeh@chromium.org>
Reviewed-by: Paris Yeh <pyeh@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
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Add CEC stub implementation and enable it for Fizz. All
it does is print a message when the driver is initialized.
Signed-off-by: Stefan Adolfsson <sadolfsson@chromium.org>
BUG=b:76467407
BRANCH=none
TEST=Check that "CEC initialized" is printed on the
console when the EC boots.
CQ-DEPEND=CL:1030219
Change-Id: I1cf674e664e091354e344e0c08a69bd09f415904
Reviewed-on: https://chromium-review.googlesource.com/1030220
Commit-Ready: Stefan Adolfsson <sadolfsson@chromium.org>
Tested-by: Stefan Adolfsson <sadolfsson@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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In this CL, we changed chip variants npcx7m6xb to npcx7m6fb and npcx7m7w
to npcx7m7wb for better clafiication since it introduced new parameter
"b" for chip generation in the same family series.
In new npcx7 series naming rule, it follows:
Format: NPCX7(M)(N)(G/K/F)(B/C)
param M: 8: 128-pins package, 9: 144-pins package
param N: 5: 128KB RAM Size, 6: 256KB RAM Size, 7: 384KB RAM Size
param G/K/F/W: Google EC depends on specific features.
param B/C: Chip generation in npcx7. (Generation A is ignored. It
follows nameing rule in npcx5.)
The all chip variants of npcx7 used in boards are also listed below:
npcx7m6g - for npcx7 ec without internal flash on npcx_evb.
npcx7m6f - for npcx7 ec with internal flash.
npcx7m6fb - for npcx7 ec with internal flash, enhanced features.
npcx7m7wb - for npcx7 ec with internal flash, enhanced features + WOV.
BRANCH=none
BUG=none
TEST=No build errors for npcx7 series.
Change-Id: I896ee33209efa5d7157c90515005db5f36318c76
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/1025471
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
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NPCX79nxB chips add UART FIFO support with 16-bytes of TX/RX buffers.
This CL enables the UART FIFO mode when NPCX79nxB chips are used.
The UART interrupt priority is decreased from 1 to 4 because now it has
the capability to buffter data in the FIFO when ec is serving the
interrupts with higher priority.
BRANCH=none
BUG=none
TEST=No build errors for make buildall.
TEST=stress test the uart port by shell command "while true; do echo
'taskinfo'>/dev/pts/19; sleep 0.1; done".
Change-Id: Ib09c1b5550d0db249201fc4fdd8d3b28c24b8a8e
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/1012002
Commit-Ready: CH Lin <chlin56@nuvoton.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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This CL adds the driver support for the WoV module which inludes the
following files:
- wov.c
- wov_chip.h
- apm.c
- apm_chip.h
It also supports the console commad "wov" which can test different
configuration and audio quality by entering different parameters.
The detail description of WoV console command is listed below:
------------------------------------------------------------------------
[Note]: Before changing any of settings, please make sure the operation
mode is on the "OFF" state. (ie. run the command wov cfgmod off
first) .
> wov init
Initialize WoV interface, including pin mux and interrupt
registration etc.
> wov mute <enable / disable >
mute enable / disable.
> wov cfgsrc <mono | stereo | left | right>
set audio source, ex: wov cfgsrc left, means audio source from left
MIC.
> wov cfgbis <16|18|20|24>
set audio resolution, ex: wov cfgbit 16 means audio resolution are
16bits.
> wov cfgsfs <8000|12000|16000|24000|32000|48000>
set audio sampling frequency rate, ex: wov cfgsfs 48000 means audio
sampling rate are 48Khz.
> wov cfgbck <32fs|48fs|64fs|128fs|256fs>
set I2S bit clock rate, ex: wov cfgsfs 48000 and wov cfgbck 32fs
means audio sampling rate are 1536Khz (32*48000).
> wov cfgfmt <i2s|right|left|pcma|pcmb|tdm>
set I2S but format, ex: wov cfgfmt right means audio I2S format are
Right-Justify.
> wov cfgmod <off|vad|ram|i2s|rami2s>
set audio operation mode ,ex: wov cfgmod i2s means audio output via
I2S bus.
> wov cfgtdm <0~496 0~496 0~3>
set TDM time slot, the first values is left channel delay counter,
the second is right channel, and the 3rd is startup counting condition.
(chosen LRCK raising or falling edge) .
[Note: this command is just working on cfgmod equal to tdm]
> wov cfgget
retrieve above settings.
> wov vadsens
(currently not support, reserve for next version)
> wov gain (0~31)
set audio data gain value, ex: wov gain 10 means setting audio digital
gain are 10dB.
> wov cfgdck <1.0 | 2.4 | 3.0 >
set digital MIC PDM clock rate. ex: wov cfgdck 2.4 means PDM clock
are 2.4Mhz.
-----------------------------------------------------------------------
This CL also adds the chip ID (0x24) for npcx7m7w. So the console
command "version" can show the chip is npcx7m7w.
BRANCH=none
BUG=none
TEST=No build errors for make buildall.
TEST="BOARD=npcx7_evb make"; Flash the image on EVB; Test WoV function
with console commands described above.
Change-Id: Ief2b3e89edbd3e6d2a9d82d317a93c9f0b7a20cd
Signed-off-by: Dror Goldstein <dror.goldstein@nuvoton.com>
Signed-off-by: Simon Liang <CMLiang@nuvoton.com>
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/897314
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Scott Collyer <scollyer@chromium.org>
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According to NPCX data sheets (NPCX5 and NPCX7), ESPI_MAXFREQ should
be decided based on the value of FMCLK. Since we are setting FMCLK to
30MHz on NPCX5, eSPI_MAXFREQ needs to be set to 33MHz.
This change sets ESPI_MAXFREQ_MAX depending upon the value of FMCLK.
BUG=b:73504527
BRANCH=fizz?
TEST=Verified that on soraka ESPI_MAXFREQ is set to 33MHz. Also, ran
some reboot tests to ensure that there is no regression in boot time.
Change-Id: Iaee89078741cf44c7ac232e2ee14d75384f68a35
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://chromium-review.googlesource.com/925843
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-by: caveh jalali <caveh@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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the npcx7 can only run eSPI at (up to) 50MHz while the npcx5 can go up
to 66MHz. so, set the max speed to whatever the hardware can actually
do. the bit pattern for 66MHz is "reserved" on the npcx7, so let's
not even define it in the npcx7 case.
BUG=b:72838699, b:71859563
BRANCH=none
TEST="make buildall" passes; boots on meowth
Change-Id: I428caf72a41fe58008df4624c475dafadca4a0bc
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/910321
Commit-Ready: caveh jalali <caveh@chromium.org>
Tested-by: caveh jalali <caveh@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
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Nami EC has EC_HIBERNATE pin connected to a silego (U91). When this
pin is asserted, U91 shuts down ROP_PMIC_ENVR3, which turns off the
EC. Thus, we don't use the internal hibernate/wake-up feature in npcx.
BUG=b:72641658
BRANCH=none
TEST=Test system will shutdown and doesn't auto
wake up when type hibernate in ec console. And wake up by AC plugin,
LID open, or power button.
Change-Id: Ib9e02f7e41087e5972eedf4855d88a4c45c75bb4
Signed-off-by: Elthan_Huang <elthan_huang@compal.corp-partner.google.com>
Reviewed-on: https://chromium-review.googlesource.com/890569
Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org>
Tested-by: Raymond Chou <raymond_chou@compal.corp-partner.google.com>
Reviewed-by: Raymond Chou <raymond_chou@compal.corp-partner.google.com>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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In this CL, we add the following changes to support the CHIP_VARIANT
npcx7m6xb and npcx7m7w:
1. Define the code RAM, data RAM, BBRAM base address/size.
2. Initialize the wov.c file for WoV driver development. (It will be
compiled only when CHIP_VARIANT=npcx7m7w in the build.mk and
CONFIG_WAKE_ON_VOICE is defined in board.h)
3. Fix the the incorrect offset of PWDWN_CTRL7 register.
BRANCH=none
BUG=none
TEST=No build errors for make buildall.
TEST=Change CHIP_VARIANT to npcx7m7w/npcx7m6xb in
board/npcx7_evb/build.mk; "BOARD=npcx7_evb make"; Check ec image can be
built. Flash the image on EVB; make sure EVB bootup.
Change-Id: I87bccb9097f8f0a6c67f96a8d90adf201ae9e773
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/858637
Commit-Ready: CH Lin <chlin56@nuvoton.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
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This CL fixed the issue that ec cannot enter low power mode, which
increases more power consumption in s5, by not setting ESPIRSTWE bit.
For more detail, please see the npcx5's errata rev1_7, No.2.21.
BRANCH=none
BUG=b:69351155
TEST=No build errors for "make buildall".
TEST=build and flash soraka, run commands to read the power consumption:
dut-control pp3300_dsw_ec_cfg_reg:0x7327k
dut-control pp3300_dsw_ec_mw -t 20 | grep "@@"
the average power consumption measured reduces from 42.x to 10.x mw.
TEST=do cold reboot stress test for 4 hours and no symptom occurred.
Change-Id: Ic6fd7fe14ae8acaefd4e1a99ca1625254f67d708
Signed-off-by: CHLin <CHLIN56@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/778709
Commit-Ready: CH Lin <chlin56@nuvoton.com>
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
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Define NPCX_UART_* macros instead of having so many ifdef
NPCX_UART_MODULE2 in the code.
Also, do not set NPCX_WKEDG bit in npcx_uart2gpio: instead
set it in uart_config just just like NPCX7 does it.
BRANCH=none
BUG=b:65526215
TEST=On Lux, EC console works, so does pad-switching EC-EC comm.
TEST=Flash soraka, using "idlestats", check that EC goes into
deep sleep, and that it can be woken up typing in EC console.
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Change-Id: I84b4f980fa79ed43640df4afc23cdc24cca21d99
Reviewed-on: https://chromium-review.googlesource.com/730029
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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NPCX5* only has one UART controller, which can be switched
between 2 pads. We keep the default pad for EC console,
however, we allow switching to the alternate pad for short,
infrequent, transactions. Both pads are assumed to use the
same baudrate and other line settings.
When switching pad, we first configure the new pad, then switch
off the old one, to avoid having no pad selected at a given time,
see b/65526215#c26.
Because of the added complexity of npcx_gpio2uart (and the fact
that it uses the global variable "pad" define in uart.c), we
move the implementation to uart.c (npcx_uart2gpio is also moved
for consistency).
When the pad is switched to alternate pad, characters input
and output on the EC console (default pad) would be lost. To
compensate for this, we:
- Switch back to main pad in case of EC panic, so that output
is shown on EC console.
- Immediately abort current alternate pad transaction if a
character is received on the default pad. Note, however,
that the first character will be lost (this can be worked
around by telling user to press enter, and have servod/FAFT
always send 2 blank lines (instead of just one) before
sending a command).
- Inhibit pad switching for 500ms after receiving a character
on default pad. Assuming a reasonable typing speed, this
should allow developers to type console commands relatively
comfortably, while not starving the alternate pad communication
for too long.
The logic above could be simplified significantly by implementing
software flow control (XON/XOFF, see b/67026316).
BRANCH=none
BUG=b:65526215
TEST=While follow-up CL that writes long 1k buffers, the following
works fine:
- type 'uart' in EC console
- Read battery power consumption from servod, which "types" in
the EC console:
while true; do dut-control ppvar_vbat_mw; sleep 1; done
no failure is seen.
TEST=Add this test code in uart_alt_pad_read_write, after the pad
has been switched, and check that panic information is
consistently printed correctly:
{
static int t;
if (t++ > 20)
t = t / ret;
}
Change-Id: I18feed2f8ca4eb85f40389f77dac3a46315310e7
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/659458
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
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In this CL, we introduced new bit fields of eSPI registers on npcx5/7
for the incoming patches. We also remove useless registers such as
VWGPMS, VWGPSM and PING in order to let the driver look more clearly.
This CL also includes:
1. Fixed typo from ESPIIWE to ESPIWE.
2. Introduce ESPIWE bits fields on npcx5/7.
3. Introduce new bit fields in ESPISTS of npcx7.
4. Remove useless VW1-4, VW1IE1-4 bits in ESPISTS and ESPIIE registes.
5. Introduce new bit field, WE, in VWEVMSn register of npcx7.
BRANCH=none
BUG=none
TEST=No build errors for npcx5/7 series. Using "suspend_stress_test -c
1000" to do stress test and no symptom occurred on poppy. Both warmboot
and coldboot stress test for 3 hours and no symptom occurred on poppy.
Change-Id: Ie8aa3dbd148588b0d9a756572d66604a6836a760
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Reviewed-on: https://chromium-review.googlesource.com/672026
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Reviewed-by: Amit Maoz <Amit.Maoz@nuvoton.com>
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