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* PB: Make CONFIG_POWER_BUTTON_INIT_IDLE commonDaisuke Nojiri2020-06-131-32/+0
| | | | | | | | | | | | | | | | | Currently CONFIG_POWER_BUTTON_INIT_IDLE is available only for NPCX chips. This patch moves the code to common/power_button.c. There is no functionality change. BUG=b:37536389 BRANCH=none TEST=Verify no functionality change on Puff. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Change-Id: Ib4b1182900acea21e5210a2f9a699da18fe55611 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2242661 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* NPCX797WC: correct image size to avoid overflowing WP_ROPeter Marheine2020-06-091-37/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The -WC chip has half as much flash as the -WB but the same amount of RAM, which causes the EC_RO section in the output FMAP to be larger than the actual read-only section of flash because code RAM is not more than twice the size of the on-chip flash, which is required because RO also contains the bootloader header. Update the definitions for this chip to generate a smaller image that still fits in Flash after the RO header is added. Because this breaks assumptions about used memory being equal to available memory, remove the RAM size checks and reorganize the chip blocks to define code and data memory in the same block to obviate any need for RAM size checks. BUG=b:158052612 TEST=Verify flash map is not broken: dump_fmap -hh build/dalboz/ec.bin, where prior to this change it complains that sections overlap: 0x00000000:0x0003f03f EC_RO 0x00000040:0x0003f03f FR_MAIN 0x00000184:0x000001a3 RO_FRID 0x0002bf40:0x0002c09d FMAP 0x00000000:0x0003ffff WP_RO 0x00040000:0x0007efff EC_RW 0x00040144:0x00040163 RW_FWID Flashing the new image to a Dalboz boots and jumps to RW correctly. BRANCH=None Change-Id: I2ac28a7f973c4ae715828687edaad5f0110a2950 Signed-off-by: Peter Marheine <pmarheine@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2230949 Reviewed-by: Andrew McRae <amcrae@chromium.org>
* npcx: Use AP_IDLE instead of AP_OFF to restore AP powerDaisuke Nojiri2020-05-231-8/+11
| | | | | | | | | | | | | | | | | | | | | When CONFIG_POWER_BUTTON_INIT_IDLE is defined, the AP power state is restored after power loss (e.g. black out for chromebox). This feature is implemented by EC_RESET_FLAG_AP_OFF. When AP_OFF is set, EC forces the AP to stay off even if the AP is sequencing up. This patch will prevent RW from shutting off the AP unintentionally after sysjump. BUG=b:154778457 BRANCH=none TEST=Verify test_that suite:faft_bios passes. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Change-Id: I8f64023bd58d5679194dfa389851edf2234c58be Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2213730 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* npcx/system: Clean up bbram_data_readDaisuke Nojiri2020-05-231-3/+3
| | | | | | | | | | | | | | This patch replaces calls to bbram_data_read for BBRM_DATA_INDEX_SAVED_RESET_FLAGS with chip_read_reset_flags. BUG=none BRANCH=none TEST=buildall Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Change-Id: I008ff594c1d754eb4cc814d4020e587c36f24cda Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2213358 Reviewed-by: Yicheng Li <yichengli@chromium.org>
* npcx: add chip family codeCHLin2020-04-211-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | If a hardware feature is supported across two or more chip families but not supported in the older chip family, using the chip family code can simplify the guard of the new feature. For example, we can use: #if (NPCX_FAMILY_VERSION >= NPCX_FAMILY_NPCX7) Implementation of the new feature #endif instead of: #if defined(CHIP_FAMILY_NPCX7) | defined(CHIP_FAMILY_NPCX8) .... Implementation of the new feature #endif BUG=none BRANCH=none TEST=No error for "make buildall" Signed-off-by: CHLin <CHLIN56@nuvoton.com> Change-Id: I09614428034f64f16ed446b73bf0797ee81538c9 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2142834 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: CH Lin <chlin56@nuvoton.com> Tested-by: CH Lin <chlin56@nuvoton.com>
* Rename Cortex-M MMFS to CFSRPeter Marheine2020-03-191-6/+6
| | | | | | | | | | | | | | | | | Taken as as 32-bit register, ARM call the register at 0xe000ed28 CFSR; the Configurable Fault Status Register. MMFS is the low byte of this value, so it's misleading to refer to the whole 32-bit value as MMFS; instead call it CFSR to make it clear that the value we store encompasses the MMFSR, BFSR and UFSR. BUG=None BRANCH=None TEST=make buildall Change-Id: Ifd62e0a6f27a2e6ddfa509b84c389d960347ff85 Signed-off-by: Peter Marheine <pmarheine@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2104807 Reviewed-by: Keith Short <keithshort@chromium.org>
* npcx/lpc: Don't enable PM channel OBE interrupt at initWealian2020-03-111-3/+2
| | | | | | | | | | | | | | | | | | Like what is done in the CL:2073282 for KBC. OBE interrupt enable shouldn't be set in lpc_init(). The default value of OBF bit is 0. It's will send a spurious interrupt to NVIC. BUG=none BRANCH=none TEST=No error for "make buildall" TEST=Test host command on yorp overnight by the following command: "while true; do ectool version; done" Change-Id: If9172a18b737f2d6c3c7930fcdc9aaf5ef4c8533 Signed-off-by: Wealian <whliao@nuvoton.corp-partner.google.com> Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2091133 Reviewed-by: Edward Hill <ecgh@chromium.org>
* keyboard: Add a new config for the keyboard customizationZhuohao Lee2020-03-101-3/+9
| | | | | | | | | | | | | | | In order to support a non-chromeos keyboard matrix, we can add a new config CONFIG_KEYBOARD_CUSTOMIZATION to customize the keyboard matrix in the board setting. BUG=b:148034320 BRANCH=firmware-hatch-12672.B TEST=build pass Change-Id: I6a32a1f79aeb09805c5f47f8540ea25f67a34f7f Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2035444 Reviewed-by: Jett Rink <jettrink@chromium.org>
* include/lpc.h: Expose lpc_aux_put_charRaul E Rangel2020-03-021-3/+8
| | | | | | | | | | | | | | | * Expose lpc_aux_put_char so we can call it from common/keyboard_8042. * Renamed lpc_mouse_put_char to lpc_aux_put_char so it's more generic. * Added the send_irq parameter for parity with lpc_keyboard_put_char. BUG=b:145575366 BRANCH=none TEST=Verified it builds Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I61854ed7c9b9ad1c50e55735747cfb25ca15762b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2079694 Reviewed-by: Edward Hill <ecgh@chromium.org>
* common/system: Unify ec_current_image and system_image_copy_tTom Hughes2020-02-281-14/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | "enum ec_current_image" is exposed in ec_commands.h (and used by non-EC code, such as biod). We also have an "enum system_image_copy_t" that is the exact same thing (though has a few more definitions). A followup CL (I714b6bd8c0d7192386404c25a831e38438fa5238) adds the "sysinfo" host command, so we want to be able to expose all the potential image variants. Rather than maintain two enums that can potentially get out of sync, unify the code to use a single enum. We choose to keep the "enum ec_current_image", since external code depends on it. To verify that this change results in no changes to the generated binaries: ./util/compare_build.sh --board all BRANCH=none BUG=b:146447208 TEST=./util/compare_build.sh --board=all Change-Id: I13776bc3fd6e6ad635980476a35571c52b1767ac Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2036599 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Namyoon Woo <namyoon@chromium.org>
* chip/npcx/lpc: Don't enable Output Buffer Empty by defaultRaul E Rangel2020-02-271-2/+2
| | | | | | | | | | | | | | | OBE is enabled by lpc_keyboard_put_char and lpc_mouse_put_char and the disabled by lpc_kbc_obe_interrupt. No reason to enable the interrupt on initialization. BUG=b:145575366 BRANCH=none TEST=Verified OBE interrupt still fires. Change-Id: Iba3f97b2bf4a6c5f09833f808c52901bd8406b4f Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2073282 Reviewed-by: Edward Hill <ecgh@chromium.org>
* chip/npcx/lpc: Set bit 5 when sending AUX responses.Raul E Rangel2020-02-271-0/+5
| | | | | | | | | | | | | | The linux kernel expects bit 5 to be set in the status register when the output buffer contains and AUX packet. BUG=b:145575366 BRANCH=none TEST=Verified bit 5 is set when sending aux packets Change-Id: I0d3944ea6fd04224d9f9bcf0e1b0b3c8633ad786 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2073281 Reviewed-by: Edward Hill <ecgh@chromium.org>
* chip/nxcp/lpc: Fix race condition when reading 8042 data.Raul E Rangel2020-02-271-4/+9
| | | | | | | | | | | | | | | | | When reading NPCX_HIKMDI it deasserts the IBF status flag. This means the AP is allowed to write to the input buffer. Because NPCX_HIKMDI is read twice, that means the AP could have written to the input buffer between reads. This results in losing one of the interrupts. This only happens if DEBUG_LPC is enabled. BUG=b:145575366 BRANCH=none TEST=Verified we don't lose any writes by examining logs. Change-Id: I2904c316fcad55001e8d297f4a0a73073b07702b Signed-off-by: Raul E Rangel <rrangel@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2073280 Reviewed-by: Edward Hill <ecgh@chromium.org>
* npcx7: SMB: Fix the incorrect selection of clock sourceWealian Liao2020-02-131-10/+13
| | | | | | | | | | | | | | | | | | | | The SMB driver currently uses the APB2 as the clock source for SMB4-SMB7, which is not correct. Luckily, the incorrect setting won't cause any real issue until now because the APB2 and APB3 are set to the same value. This CL fixes it by changing the clock source to the correct one (i.e. APB3.) BUG=b:149359617 BRANCH=none TEST=No error for "make buildall" TEST=Test all SMB ports on npcx7 EVB with the SMB slave device. Change-Id: I10aa0554b1c84d85e355bdefa0a0643b59aa1b25 Signed-off-by: Wealian <whliao@nuvoton.corp-partner.google.com> Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2053865 Reviewed-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: caveh jalali <caveh@chromium.org>
* npcx: Add support for ADC threshold interruptsAseda Aboagye2020-02-053-6/+224
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The Nuvoton NPCX EC series support a threshold event detector for the ADC channels. There are three threshold event detectors and they can be mapped to any ADC channel. The block compares the measured voltage input to either a programmable threshold or a pair of thresholds and generates an interrupt if the measured voltage is above or below the thresholds. This commit adds support for this feature. A new structure is created, npcx_adc_thresh_t which allows a board to define the ADC channel that should be monitored, the assertion and deassertion thresholds, a callback that can be run when the interrupt fires and a flag for whether or not the interrupt should fire if the measured value is above or below the threshold. BUG=b:148169171 BRANCH=None TEST=Enable on waddledoo, verify that the ADC dual threshold interrupt functionality works. Change-Id: I5a3e517207a71b1298865fe36b80cc6298567e9e Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2030204 Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
* npcx: Add driver support for PS/2 interfaceCHLin2020-01-306-6/+497
| | | | | | | | | | | | | | | | | | | | | | Morphius connects the trackpoint device to EC via the PS/2 interface. To support it, we implemented the chip level PS/2 driver in this CL. The PS/2 driver can be used on all series of NPCX EC chips (NPCX5/7). BUG=b:145575366 BRANCH=none TEST=No error for "make buildall" TEST=Apply this and related CLs, connect npcx5/npcx7 EVBs to standard PS/2 keyboards and PS/2 device emulator with different channels. Verify that the PS/2 write/read transaction can keep working for several hours without issue. Change-Id: I5bae313db2d697999c2da5cf33478be2da754b8c Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1982302 Tested-by: CH Lin <chlin56@nuvoton.com> Commit-Queue: Edward Hill <ecgh@chromium.org> Auto-Submit: CH Lin <chlin56@nuvoton.com> Reviewed-by: Edward Hill <ecgh@chromium.org>
* npcx: enable the host interface mouse channelCHLin2020-01-301-2/+20
| | | | | | | | | | | | | | | | | | | | | | In Morphius, the trackpoint data is passed through EC to the host by the legacy ports (60h/64h). In this CL, we enable the host interface mouse channel (LDN = 05h). Mouse interrupt (IRQ 12) will be asserted when the trackpoint data is written to the HIMDO register. It will be de-asserted once the host reads the data via IO port 60h. BUG=b:145575366 BRANCH=none TEST=No error for "make buildall" TEST=Apply this and related CL, connect npcx EVB to host emulator. Execute console command "kbcmouse data". Make sure the host can see IRQ12 and read correct data from IO port 60h. Change-Id: I4a4e9fb6c079c164b6a5e617587dd2f2cdf55164 Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2003002 Reviewed-by: Edward Hill <ecgh@chromium.org> Commit-Queue: CH Lin <chlin56@nuvoton.com> Tested-by: CH Lin <chlin56@nuvoton.com>
* dedede: Add z-state supportAseda Aboagye2020-01-211-2/+4
| | | | | | | | | | | | | | | | | | | | | | Dedede has support for the new low power "Z-state". In this state. the EC and H1 are unpowered, but power will be restored to the EC once one of the wakeup events occurs. These events are ACOK, lid open, and a power button press. This commit simply enables the Z-state when the EC hibernates. BUG=b:147819424 BRANCH=None TEST=build and flash waddledoo, enter `hibernate`, verify that EC power is turned off and can be restored by pressing the power button or plugging in a charger. Change-Id: I4f93efd0632f457354f4bf6bf0274b19a9cd799c Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2006215 Tested-by: Aseda Aboagye <aaboagye@chromium.org> Auto-Submit: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Diana Z <dzigterman@chromium.org>
* npcx: Do not reload the OFMCLK when system-jumpCHLin2020-01-151-12/+19
| | | | | | | | | | | | | | | | | | | When the OFMCLK is reloaded, it will be stopped until the clock generation becomes stable. During this narrow window, any eSPI response from EC will be abnormal. However, we needn't change the OFMCLK during system-jump because it should be set only once when EC powers on. BUG=b:145369656 BRANCH=none TEST=Pass "make buildall" TEST=The symptom no longer occurs for 3 hours stress test. Change-Id: Idcc745f11119ba3781787b8b5e77ea620264e908 Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1994685 Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Commit-Queue: CH Lin <chlin56@nuvoton.com>
* audio_codec: npcx: use DEBUG_AUDIO_CODECTzung-Bi Shih2020-01-142-5/+7
| | | | | | | | | | | | | | | | 1. Uses DEBUG_AUDIO_CODEC instead of DEBUG_WOV. 2. Moves console commands under DEBUG_AUDIO_CODEC (saves ~3KB). BRANCH=none BUG=b:144064048, b:144063867 TEST=make BOARD=trembyle -j Change-Id: Ic5b3442809506d71a333b5c1c9cc0dd4776d98bb Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1986688 Commit-Queue: Yu-Hsuan Hsu <yuhsuan@chromium.org> Tested-by: Yu-Hsuan Hsu <yuhsuan@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org>
* audio_codec: npcx: deprecate legacy option CONFIG_WAKE_ON_VOICETzung-Bi Shih2020-01-143-4/+4
| | | | | | | | | | | | | | | | | | | | | CONFIG_WAKE_ON_VOICE consists 3 features in NPCX: - DMIC - I2S_RX - WOV These features has broken down into smaller CONFIG options. Deprecates CONFIG_WAKE_ON_VOICE and prepares to separate smaller features in NPCX. BRANCH=none BUG=b:144064048, b:144063867 TEST=make BOARD=trembyle -j Change-Id: Ieaa123299ea687644f19066cf95ef150a18bf252 Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1986687 Commit-Queue: Yu-Hsuan Hsu <yuhsuan@chromium.org> Tested-by: Yu-Hsuan Hsu <yuhsuan@chromium.org> Reviewed-by: Edward Hill <ecgh@chromium.org>
* audio_codec: npcx: migrate DMIC and I2S_RX featuresTzung-Bi Shih2020-01-144-166/+138
| | | | | | | | | | | | | | | Migrates DMIC and I2S_RX to new audio codec framework. BRANCH=none BUG=b:144064048, b:144063867 TEST=make BOARD=trembyle -j Change-Id: Ifbc6d939110311578c4aa0655ede92b1df714774 Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1986686 Reviewed-by: Edward Hill <ecgh@chromium.org> Commit-Queue: Yu-Hsuan Hsu <yuhsuan@chromium.org> Tested-by: Yu-Hsuan Hsu <yuhsuan@chromium.org>
* npcx: Add support for CONFIG_WP_ACTIVE_HIGHAseda Aboagye2020-01-031-0/+12
| | | | | | | | | | | | | | | | | NPCX was missing support for an inverted write protect polarity, this commit simply adds that support. BUG=b:146172102 BRANCH=None TEST=`make -j buildall` Change-Id: I3324d7f7cfa268a2d55f87d3b1943717e26c856c Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1986311 Tested-by: Aseda Aboagye <aaboagye@chromium.org> Auto-Submit: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Diana Z <dzigterman@chromium.org> Commit-Queue: Diana Z <dzigterman@chromium.org>
* npcx: Disable ITIM after watchdog_stop_and_unlock()Tim Wawrzynczak2019-12-031-3/+3
| | | | | | | | | | | | | | | | | | | | | | watchdog_stop_and_unlock() depends upon the ITIM32 module to ensure that it has been at least 3 watchdog ticks since the last time the watchdog has been touched. If it has been > 100ms since then, there will be no problem, but if it has been less than 100ms, then because the ITIM32 module was disabled, then the system will get stuck in the while (time_since32() ...) loop. This will eventually cause the watchdog to kick in and reboot the EC, which will also cause the AP to reboot. BUG=b:145371494, b:140207603 BRANCH=firmware-hatch-12672.B TEST=sanity testing (alt+volup+h still works) and buildall (this bug was nearly impossible to reproduce) Change-Id: I5e32f4940f03fee90b3aa809b185c13ed66ce7f1 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1946773 Reviewed-by: Andrew McRae <amcrae@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* npcx7: i2c: enable FIFO mode to transmit and receive dataCHLin2019-11-223-80/+378
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In npcx7, all I2C modules have separate 32-byte transmit FIFO and 32-byte receive FIFO buffers. In this CL, we add the FIFO mode support to the I2C driver. This will help to reduce the firmware overhead (i.e. the occurrence of I2C interrupt) during long I2C transactions by allowing the EC to write/read more than one byte of data at one time to I2C module and hence improve the I2C performance. The FIFO mode is enabled by default on all npcx7 series chips. BUG=none BRANCH=none TEST=No error for "make buildall" TEST=Connect npcx7 EVB to the I2C slave emulator, do stress test: 1. iterate ~2000 times of single i2c_xfer_unlocked API call. i.e. i2c_xfer_unlocked(.., I2C_XFER_SINGLE) 2. iterate ~2000 times of multiple i2c_xfer_unlocked API calls: i.e. i2c_xfer_unlocked(.., I2C_XFER_START) i2c_xfer_unlocked(.., 0) . . i2c_xfer_unlocked(.., I2C_XFER_STOP) 3. Issue 6 I2C transactions by 6 tasks at the same time. iterates ~2000 times. TEST=with this CL; build and upload an image (with/without FIFO mode enabled.) to yorp; no symptom occurs. Change-Id: I387e8ef6e619acef670273f08ab4150e3d2b75f2 Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1827137 Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Jett Rink <jettrink@chromium.org> Commit-Queue: CH Lin <chlin56@nuvoton.com>
* Ensure CEC bus pin is not driven lowFelix Ekblom2019-11-221-0/+3
| | | | | | | | | | | | | | | | | | We have seen cases where after a cold EC reboot the pin is low until the first CEC message is sent by AP (after which the bus is left in a well defined state again) This is a follow up to https://crrev.com/c/1346990 which initializes the pull up in case not done by the RO FW. BRANCH=none BUG=b:144548408 TEST=CEC pin only goes low for ~40ms instead of 30s. Signed-off-by: Felix Ekblom <felixe@chromium.org> Change-Id: I3c98f8858f407279ad1bd086210969d69df2230b Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1928993 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* keyscan: decouple keyboard_raw functionality from the presence of TASK_KEYSCANAlexandru M Stan2019-11-191-0/+2
| | | | | | | | | | | | | | | | | | | | | | With the addition of external i2c keyboard controllers, chips that don't necessarly have gpios going to a keyboard can now still have a TASK_KEYSCAN. Therefore it's wrong to assume we want the chip/*/keyboard_raw code included. There was no easy way to make an ways on option (eg: CONFIG_KEYBOARD_RAW) that could get #undefd in strategic places. The place that would always define it would be in include/config.h but I don't believe that executes before the build.mk rules. BUG=b:135895590 TEST=Other boards with keyboards still happy. TEST=No compile errors (regarding missing keyboard GPIOS) when declaring TASK_KEYSCAN on a fresh stm32 board. BRANCH=master Change-Id: I061812a6941a11784950280648912edd5844bd79 Signed-off-by: Alexandru M Stan <amstan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1693862 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* Cleanup: Correct GPIO alternate function parameterVijay Hiremath2019-11-011-6/+9
| | | | | | | | | | | | | | | Added code to correct the GPIO alternate function parameter at Chipset level. Optionally board level functions can cleanup the code in additional change lists. BUG=b:139427854 BRANCH=none TEST=make buildall -j Change-Id: I1171ca36a703291070fc89f972f84414adcf04fc Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1880974 Reviewed-by: Keith Short <keithshort@chromium.org>
* eSPI: Configure SLP_S3, SLP_S4 separatelyAbe Levkoy2019-10-301-1/+1
| | | | | | | | | | | | | | | | | | Split the configuration option CONFIG_HOSTCMD_ESPI_VW_SLP_SIGNALS into separate options controlling SLP_S3 and SLP_S4. Allow volteer to configure SLP_S3 as a GPIO and SLP_S4 as an eSPI virtual wire. Cause a build error if virtual wires are configured, but eSPI is not. BUG=b:139553375,b:143288478 TEST=make buildall TEST=Build volteer with CONFIG_HOSTCMD_ESPI_VW_S4 defined but CONFIG_HOSTCMD_ESPI undefined; observe build error BRANCH=none Change-Id: I8c6737e2ccb1a77a882e5fa65c6eddb342209b61 Signed-off-by: Abe Levkoy <alevkoy@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1881758 Reviewed-by: Keith Short <keithshort@chromium.org>
* NPCX GPIO: Assert that gpio_get/set_level is passed a GPIO signalEdward Hill2019-10-251-0/+4
| | | | | | | | | | | | | | | Ensure that IOEX and VW signals are not accidentally passed to NPCX's gpio_get_level or gpio_set_level. BUG=b:138600691 BRANCH=none TEST=saw assert when passing IOEX signal to gpio_set_level Change-Id: Ib3eea074a104820cea4095897f4174a84e8368d6 Signed-off-by: Edward Hill <ecgh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1854781 Reviewed-by: Denis Brockus <dbrockus@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org>
* main: Initialize I2C pretty earlyAlexandru M Stan2019-10-241-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Some devices (like the keyboard, CBI) need I2C access pretty early. Until now I2C would get initialized pretty late in a hook, which was far too late for some stuff. As a result from this change, CONFIG_I2C_MASTER now implies the i2c_init() function will be called at board boot. Some chips (cr50, host tests) needed a stub i2c_init in order to compile cleanly. BUG=b/138384267 TEST=EFS doesn't happen significantly later than it used to TEST=Recovery keys now work with I2C keyboard on jacuzzi TEST=make buildall TEST=Sanity check i2c behavior (booting, "i2scan", "battery") on a variety of ECs: * ampton (ite EC, x86 AP) * bobba (npcx EC, x86 AP) * jacuzzi (stm32f0 EC, ARM AP) * cheza (npcx EC, ARM AP) BRANCH=master Change-Id: Ifa830e8e509ff16b36b4dcc86617869b1cb86ac3 Signed-off-by: Alexandru M Stan <amstan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1772490 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* NPCX ESPI: fix some typosEdward Hill2019-10-162-8/+8
| | | | | | | | | | | | BUG=none BRANCH=none TEST=buildall Change-Id: I7f9089ce8028f12a94d8e73dd58a5bb36ebc614f Signed-off-by: Edward Hill <ecgh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1862090 Reviewed-by: Denis Brockus <dbrockus@chromium.org> Commit-Queue: Denis Brockus <dbrockus@chromium.org>
* npcx: Ensure the watchdog isn't stopped while it is invalid to do soJett Rink2019-10-093-10/+31
| | | | | | | | | | | | | | | | | | | We cannot unlock the watchdog timer within 3 watch dog ticks of touching it per the datasheet. This is actually around 100ms so we should protect against this. Note: To avoid bringing in other dependencies into the npcx_monitor_fw, the "old" method of stopping the watchdog is used (no waiting first). BRANCH=none BUG=b:140207603 TEST=eliminates cold reset issue. Change-Id: I440d36fb9aecdd6d78bae6fc4002208198a3357f Signed-off-by: Jett Rink <jettrink@chromium.org> Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1842592 Reviewed-by: ML Chao <mlchao@nuvoton.corp-partner.google.com>
* npcx7: fix RAM powerdown regressionCaveh Jalali2019-10-081-2/+3
| | | | | | | | | | | | | | | | chromium:1518660 introduced a subtle change in which RAM bank power-down bits are set. this change reverts to the original bit pattern and masks the reserved bits as suggested by nuvoton. BUG=b:141715856 BRANCH=none TEST=boots on atlas. Change-Id: Idfbedd73fd46aa639f12c9991911d96f15739174 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1833153 Reviewed-by: Caveh Jalali <caveh@google.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* npcx: espi: guard to call power_signal_interruptCHLin2019-10-081-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | The source of the SLP_Sx power signals can come from only either GPIO or virtual wire. The firmware now assumes that, when the GPIO is chosen, (i.e. CONFIG_HOSTCMD_ESPI_VW_SLP_SIGNALS is not enabled.) there should be no virtual wire SLP_Sx event is triggered. However if the host accidentally sends a SLP_Sx VW to EC, EC will call the power_singal_interrput(signal) by passing an invalid enum signal number. (i.e. The index is of the range of GPIO table.) It may cause the system problematic when the firmware uses the enum signal number to access the GPIO table. BUG=b:141730279 BRANCH=none TEST=No error for "make buildall" TEST=Test on trembyle, the crash symptom can be fixed. Change-Id: I0fa606f812b377d6616e314ca1f1c9675a04e2a8 Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1844658 Reviewed-by: Edward Hill <ecgh@chromium.org> Commit-Queue: Edward Hill <ecgh@chromium.org> Tested-by: Edward Hill <ecgh@chromium.org>
* npcx: espi: clear pending bit while setting VW interruptCHLin2019-10-081-0/+3
| | | | | | | | | | | | | | | | | | | | | According to the datasheet, firmware should clear MIWU pending register (WKPND) after configuring WKMOD/WKEDG/WKAED register and before enabling WKEN register. Otherwise, the module might cause a false wake-up or interrupt event. BUG=b:141730279 BRANCH=none TEST=No error for "make buildall" TEST=Test on yorp, check the fake virtual wire events are no longer generated and the system crash symptom is fixed when CONFIG_BRINGUP is defined. Change-Id: I89e055b4174419658cdd823f04acff41aa14cfe6 Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1844660 Reviewed-by: Edward Hill <ecgh@chromium.org> Commit-Queue: Edward Hill <ecgh@chromium.org> Tested-by: Edward Hill <ecgh@chromium.org>
* printf: Fix formatting errorsEvan Green2019-10-051-4/+6
| | | | | | | | | | | | | | | | | | | This change fixes the printf formatting errors found by the compile-time prinf format checker. The errors fall into a few categories: 1. Incorrect size specifier (missing or extra l). 2. Missing or extra arguments. 3. Bad line splitting. BUG=chromium:984041 TEST=make -j buildall BRANCH=none Change-Id: I5618097a581210b9fcbfc81560dec050ae30b61c Signed-off-by: Evan Green <evgreen@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1819653 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* printf: Convert %l to %llEvan Green2019-10-051-2/+2
| | | | | | | | | | | | | | | | | | | | | In order to make our printf more standard, utilize %ll for long long arguments, rather than %l. This does cost a little bit in flash space for that extra l in a couple of places, but enables us to turn on compile-time printf format checking. For this commit only, the semantics are such that both %l and %ll take 64-bit arguments. In the next commit, %l goes to its correct behavior of taking a sizeof(long) argument. BUG=chromium:984041 TEST=make -j buildall BRANCH=none Cq-Depend:chrome-internal:1863686,chrome-internal:1860161,chrome-internal:1914029 Change-Id: I18081b55a8dbf5ef8ec15fc499ca75e59d31da58 Signed-off-by: Evan Green <evgreen@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1819652 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* host_command: Change host command return value to enum ec_statusTom Hughes2019-10-026-19/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the host command handler callback function returns an int, it's easy to accidentally mix up the enum ec_error_list and enum ec_status types. The host commands always expect an enum ec_status type, so we change the return value to be of that explicit type. Compilation will then fail if you accidentally try to return an enum ec_error_list value. Ran the following commands and then manually fixed up a few remaining instances that were not caught: git grep --name-only 'static int .*(struct host_cmd_handler_args \*args)' |\ xargs sed -i 's#static int \(.*\)(struct host_cmd_handler_args \*args)#\ static enum ec_status \1(struct host_cmd_handler_args \*args)##' git grep --name-only 'int .*(struct host_cmd_handler_args \*args)' |\ xargs sed -i 's#int \(.*\)(struct host_cmd_handler_args \*args)#\ enum ec_status \1(struct host_cmd_handler_args \*args)##' BRANCH=none BUG=chromium:1004831 TEST=make buildall -j Cq-Depend: chrome-internal:1872675 Change-Id: Id93df9387ac53d016a1594dba86c6642babbfd1e Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1816865 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* chip/npcx: fix cprints argumentsCaveh Jalali2019-10-011-2/+2
| | | | | | | | | | | | | | | this fixes the format string used in cprints. the intent was clearly string concatenation, but instead 2 strings were passed to cprints. BUG=none BRANCH=none TEST=buildall passes, boots on atlas Change-Id: I8942c4f5fd99b490a3da8a6a289d23454509e69d Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1826177 Reviewed-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* cleanup: fix byte access and ifdefs for BBRAM_PD2Jett Rink2019-09-301-8/+1
| | | | | | | | | | | | | | Ensure that PD2 is accessed as a single byte instead of 4 bytes and remove unnecessary ifdef guards in all chip implementations. BRANCH=none BUG=none TEST=builds Change-Id: I319d8d6a8456662235ab4d8dcda6bda7e8ed7c15 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1809938 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* audio_codec: replace legacy console channelTzung-Bi Shih2019-09-171-2/+2
| | | | | | | | | | | | | | | CC_WOV is going to be replaced by CC_AUDIO_CODEC. BRANCH=none BUG=b:122027734, b:123268236 TEST=make BOARD=npcx7_evb -j Change-Id: Ib263375c02b69a82eb97ef0a7b9ede4571104af1 Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1697886 Commit-Queue: Sean Abraham <seanabraham@chromium.org> Reviewed-by: Cheng-Yi Chiang <cychiang@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* Revert "npcx: ensure we don't unlock watchdog too soon"Caveh Jalali2019-09-124-32/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 031c5d2d62dd891622ded885756c03021e934ef2. Reason for revert: introduced compilation errors: chip/npcx/spiflashfw/npcx_monitor.c: In function 'sspi_flash_upload': chip/npcx/spiflashfw/npcx_monitor.c:290:2: error: implicit declaration of function 'watchdog_stop_and_unlock' [-Werror=implicit-function-declaration] watchdog_stop_and_unlock(); ^~~~~~~~~~~~~~~~~~~~~~~~ Original change's description: > npcx: ensure we don't unlock watchdog too soon > > We cannot unlock the watchdog timer with 3 watch dog ticks of touching > it per the datasheet. This is actually around 100ms so we should protect > against this. > > BRANCH=none > BUG=b:140207603 > TEST=eliminates cold reset issue. > > Change-Id: Iaef59dad9f5640d64d5d430aea87bd16c2efd30d > Signed-off-by: Jett Rink <jettrink@chromium.org> > Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1790302 > Reviewed-by: Scott Collyer <scollyer@chromium.org> > Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> > Reviewed-by: ML Chao <mlchao@nuvoton.corp-partner.google.com> > Reviewed-by: Furquan Shaikh <furquan@chromium.org> > Tested-by: Furquan Shaikh <furquan@chromium.org> > Commit-Queue: Furquan Shaikh <furquan@chromium.org> Bug: b:140207603 Change-Id: I540fa53c2c568cb789400d55b807a672b182302a Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1799293 Reviewed-by: Caveh Jalali <caveh@google.com> Commit-Queue: Caveh Jalali <caveh@google.com> Tested-by: Caveh Jalali <caveh@google.com>
* npcx: ensure we don't unlock watchdog too soonJett Rink2019-09-124-13/+32
| | | | | | | | | | | | | | | | | | | | We cannot unlock the watchdog timer with 3 watch dog ticks of touching it per the datasheet. This is actually around 100ms so we should protect against this. BRANCH=none BUG=b:140207603 TEST=eliminates cold reset issue. Change-Id: Iaef59dad9f5640d64d5d430aea87bd16c2efd30d Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1790302 Reviewed-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: ML Chao <mlchao@nuvoton.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org>
* audio_codec: refactor I2S RXTzung-Bi Shih2019-09-031-0/+2
| | | | | | | | | | | | | | | | Refactor by the following items: - use more specific name "i2s rx" - use verbose symbol names to separate namespaces - remove unused TDM-related code BRANCH=none BUG=b:122027734, b:123268236 TEST=make BOARD=kukui_scp -j && make BOARD=npcx7_evb -j Change-Id: I8ccda5b5bbd9cf144bd68ba25249c8243b3086ac Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1564500 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* include: Move RESET_FLAG_* into ec_commands.h as EC_RESET_FLAG_*You-Cheng Syu2019-08-263-25/+26
| | | | | | | | | | | | | | | | | | | | | | | RESET_FLAGS_* are used when setting/reading the field ec_reset_flags of struct ec_response_uptime_info, which is defined in ec_commands.h. So it might be better to put those macros there. To be consistent with the other macros in the file, add "EC_" prefixes to them. BUG=b:109900671,b:118654976 BRANCH=none TEST=make buildall -j Cq-Depend: chrome-internal:1054910, chrome-internal:1054911, chrome-internal:1045539 Change-Id: If72ec25f1b34d8d46b74479fb4cd09252102aafa Signed-off-by: You-Cheng Syu <youcheng@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1520574 Tested-by: Yu-Ping Wu <yupingso@chromium.org> Commit-Ready: Yu-Ping Wu <yupingso@chromium.org> Legacy-Commit-Queue: Commit Bot <commit-bot@chromium.org> Reviewed-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* npcx: i2c: adjust i2c bus frequency when it is set to 100kHz.Mulin Chao2019-08-121-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When npcx i2c module's bus frequency is set to 100KHz, it operates in normal mode and its bus frequency, fSCL, follows the formula listed below: fSCL = fCLK / (4*SCLFRQ), ie. SCLFRQ = fCLK / (4*fSCL) where fCLK is the source clock frequency of i2c module and SCLFRQ defines the SCL output period in SMBCTL2/3 registers. But integer division in this formula is equal to the floor of regular division if it isn't divisible. So far, all i2c modules' source clock frequency is 15MHz and if the desired i2c bus frequency is 100KHz, the SCLFRQ will be: SCLFRQ = fCLK/(4*fSCL) = 15MHz/(4*100kHz) = floor(37.5) = 37 And the actual i2c frequency is: fSCL = fCLK/(4*SCLFRQ) = 15MHz/(4*37) = 101.35KHz That's why we observe the i2c frequency is slightly higher than 100kHz. To fix this issue, this CL replaces integer division with the ceiling value of the formula to make sure bus frequency is lower than 100KHz and meet i2c spec when it operates in normal mode. BRANCH=none BUG=b:138350407 TEST=No build errors for npcx series. Measure the actual i2c bus which is configured to 100KHz after applying this CL. The actual frequency is 98.7 KHz on npcx5/7 evbs. Change-Id: I71e2c3090bc91c7b9945c01c04c9ac5ac656c893 Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1741566 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Commit-Queue: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
* npcx: make i2c slave address uint16_t to be standardDenis Brockus2019-07-231-1/+1
| | | | | | | | | | | | | | | | | | | | EC code changed over to a 7-bit slave address and stored in a uint16_t to generically be able to handle 10-bit addresses, if they are ever needed, as well as common bit flags in the most significant bits. This code does not use more than the 8 least significant bits but to be EC consistent, I am making this 16 bits. BUG=none BRANCH=none TEST=make buildall -j Change-Id: Ic5f4b3500ae7b3c18380b188efbc37c01d58d7e9 Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1714136 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
* npcx7: UART: wait for Tx empty before enabling deep-sleepCHLin2019-07-234-2/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the original firmware (in the uart_buffering.c), it clears the SLEEP_MASK_UART immediately after it pushes all characters from its Tx buffer to UART's FIFO without checking the status of transmission. It may break the transmission because EC goes to deep sleep before UART TX (FIFO or shift register) becomes empty. This CL fixes it by: (1) Don't clear SLEEP_MASK_UART immediately when uart_tx_stop is called. (2) Enable the NXMIP (No Transmit in Progress) interrupt. (3) Clear SLEEP_MASK_UART in the UART interrupt handler when NXMIP is set. This fix only needs to apply to NPCX7 chips which have UART FIFO support. BRANCH=none BUG=b:137143640 TEST=No error for "make buildall" TEST=run 10 iterations of uart_stress_tester on yorp with command: ./util/uart_stress_tester.py /dev/ttyUSB2 -t 360; make sure no character lost in each iteration as below: ... INFO | UartSerial| /dev/ttyUSB2 | Detected as EC UART INFO | UartSerial| EC | Ready to test INFO | ChargenTest | Ports are ready to test INFO | ChargenTest | Test starts INFO | UartSerial| EC | Test thread starts INFO | UartSerial| EC | Test thread is done INFO | UartSerial| EC | 0 char lost / 4147200 (0.0 %) INFO | ChargenTest | PASS: lost 0 character(s) from the test INFO | ChargenTest | Test is done Change-Id: I97b1f572e8b9ebdb5102aa3e98ae2963d768b5b3 Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1703944 Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Namyoon Woo <namyoon@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Commit-Queue: CH Lin <chlin56@nuvoton.com>
* Remove __7b, __8b and __7bfDenis Brockus2019-07-201-8/+8
| | | | | | | | | | | | | | | | | | | The extentions were added to make the compiler perform most of the verification that the conversion was being done correctly to remove 8bit addressing as the standard I2C/SPI address type. Now that the compiler has verified the code, the extra extentions are being removed BUG=chromium:971296 BRANCH=none TEST=make buildall -j TEST=verify sensor functionality on arcada_ish Change-Id: I36894f8bb9daefb5b31b5e91577708f6f9af2a4f Signed-off-by: Denis Brockus <dbrockus@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1704792 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
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