| Commit message (Collapse) | Author | Age | Files | Lines |
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This implements missing I2C driver functions to get or set the I2C bus
speed on NPCX family chips.
BRANCH=none
BUG=b:201039003
TEST=with follow-on patches, switched I2C bus speed between 400 kHz
and 1 MHz.
Change-Id: Ie0d8de1ca2c4884e52f5fe947ad19a50b0c76fb9
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3170292
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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This adds code to the npcx I2C driver to keep track of the speed setting
used to configure the port. This can be used to determine the current
speed setting without decoding chip registers.
BRANCH=none
BUG=b:201039003
TEST=with follow-on patches, switched I2C bus speed between 400 kHz
and 1 MHz.
Change-Id: Ib7a61e23ec406deff80afead2e2aa6b64578ea1d
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3181502
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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BRANCH=none
BUG=b:201039003
TEST=buildall passes
Change-Id: I5b34e5266f28452d30d76489e4afaef4cb2287e2
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3181501
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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This splits the implementation of i2c_freq_changed() into a per-port
worker function and a top-level iterator function. This change makes
i2c_port_set_freq() available to set a port's I2C speed.
BRANCH=none
BUG=b:201039003
TEST=with follow-on patches, switched I2C bus speed between 400 kHz
and 1 MHz.
Change-Id: Ifb5613ac3a59cbd64f01f3a396f978db5e77d9f1
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3170291
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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This reverts commit 20222d48571fa44c76fdb0ededd0ed042e9f8244.
Reason for revert: brya thinks it's in EC-RW when it's really still in EC-RO.
Original change's description:
> npcx: correct the image copies indication bits for npcx9
>
> In npcx5/7, we use two reserved bits in the BSC1 register (offset 0x07
> of the MDC register) to indicate what the current image copy is.
> In npcx9, these two bits are used by the booter. We need to change them
> to another two empty scratch bits which are not used by the booter.
>
> BUG=b:165777478
> BRANCH=none
> TEST=pass "make buildall"
> TEST=check the related bits changed by "sysump ro" and "sysjump rw"
>
> Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
> Change-Id: I6bcfe6d8752c6fa10022a21956d2e0ceb7f9418e
> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3153119
> Tested-by: CH Lin <chlin56@nuvoton.com>
> Reviewed-by: caveh jalali <caveh@chromium.org>
> Auto-Submit: CH Lin <chlin56@nuvoton.com>
> Commit-Queue: caveh jalali <caveh@chromium.org>
Bug: b:165777478
Change-Id: I24cdfec0d5c8cd998f087525ae21b2a3daea43a7
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3172266
Bot-Commit: Rubber Stamper <rubber-stamper@appspot.gserviceaccount.com>
Tested-by: caveh jalali <caveh@chromium.org>
Commit-Queue: caveh jalali <caveh@chromium.org>
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In npcx5/7, we use two reserved bits in the BSC1 register (offset 0x07
of the MDC register) to indicate what the current image copy is.
In npcx9, these two bits are used by the booter. We need to change them
to another two empty scratch bits which are not used by the booter.
BUG=b:165777478
BRANCH=none
TEST=pass "make buildall"
TEST=check the related bits changed by "sysump ro" and "sysjump rw"
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Change-Id: I6bcfe6d8752c6fa10022a21956d2e0ceb7f9418e
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3153119
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: caveh jalali <caveh@chromium.org>
Auto-Submit: CH Lin <chlin56@nuvoton.com>
Commit-Queue: caveh jalali <caveh@chromium.org>
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The npcx eSPI driver only prints if eSPI_DEBUG is on. Without ESPI_DEBUG,
critical eSPI errors are hidden and it may not be obvious why the
system is failing. This change forces eSPI bus error messages to always
print.
This is inside of an interrupt_handler, so printing too much could
cause other interrupts to be missed. The error message is short and it
did not cause additional errors during testing. Since eSPI bus errors
are often fatal, this risk is acceptable.
BUG=None
TEST=Boot image with known eSPI errors, see error message
Boot with known good image, see no error message
Remove condition, boot good image, eSPI functions normally
BRANCH=None
Change-Id: Ic1431800560091001b73dafcd77362e061323c1a
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3111457
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Diana Z <dzigterman@chromium.org>
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This reorganizes adc.h and adc_chip.h so that general code only needs to
know about adc.h. adc_chip.h is now included by adc.h directly and does
not need to be included in general code.
BRANCH=none
BUG=b:181271666
TEST=buildall passes (with next patch in series)
Cq-Depend: chromium:3120316
Change-Id: I8bc107c6900e831a57f7a7fb8668eb08bb179d6c
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3120315
Reviewed-by: Keith Short <keithshort@chromium.org>
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The current API for system_get_scratchpad mixes the status and the value
being read. Update the signature to allow both.
BRANCH=none
BUG=b:195481980
TEST=make testall && zmake testall
Signed-off-by: Yuval Peress <peress@chromium.org>
Change-Id: I3a5f5ad523d507c53a5d474806f58afafb82e70c
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3074828
Commit-Queue: Denis Brockus <dbrockus@chromium.org>
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
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Update SPI host interface config option for inclusive language.
BUG=b:163885307
BRANCH=none
TEST=compare_build.sh
Signed-off-by: Keith Short <keithshort@chromium.org>
Change-Id: I808d5960fa3e746626465bedc626a95e0f0aaa3f
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3066271
Commit-Queue: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
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BRANCH=none
BUG=b:163885307
TEST=compare_build.sh matches
Change-Id: I50d4263e93945ec0f3fd2d655fd173aa8a666d8f
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3060261
Reviewed-by: Boris Mittelberg <bmbm@google.com>
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BRANCH=none
BUG=none
TEST=compare_build.sh matches
Change-Id: Idd8bab55d02bafdbab6b0e136326ef47a464dc4c
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3060259
Reviewed-by: Boris Mittelberg <bmbm@google.com>
Reviewed-by: CH Lin <chlin56@nuvoton.com>
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BRANCH=none
BUG=b:181607131
TEST=compare_build.sh matches
Change-Id: I045ae5f148fe6233abf921d99f381b2cce6966ad
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3060260
Reviewed-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
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NPCX alternate switch function uses the GPIO number to select which
register should be set. Currently, we have a scenario to enable
CONFIG_PS2 & use ADC5(GPIO37) or ADC6(GPIO34) with NPCX9. The
CONFIG_PS2 condition hides the alternate table for ADC5/6. It makes
GPIO37 & GPIO34 are both set to PS2 function.
This CL adds NPCX_PS2_MODULE_2 & NPCX_PS2_MODULE_3 options to assign
PS2 function for alternate pin explicitly.
BUG=none
BRANCH=none
TEST=make buildall
TEST=Enable CONFIG_PS2 & check ADC5/6 functionality.
Signed-off-by: Wealian Liao <whliao@nuvoton.corp-partner.google.com>
Change-Id: Id02fb8ecfd488db133351119be84c357dc18da15
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3058151
Reviewed-by: caveh jalali <caveh@chromium.org>
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Compiler in nocturne cros SDK doesn't allow for variable declaration
inside for loop. This patch removes variable declaration inside for
loop in code which is used by nocturne board.
This patch doesn't introduce any logical changes.
BUG=b:160676144
BRANCH=none
TEST=Make sure EC points to commit on cros/main.
On nocturne SDK:
cros_workon-nocturne start chromeos-ec
emerge-nocturne chromeos-ec chromeos-bootimage
Make sure that firmware compiles
Signed-off-by: Patryk Duda <pdk@semihalf.com>
Change-Id: I75ff21d966d5e353d1f7873695127bac4357fb32
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2965922
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
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The names conflict when enabling both Zephyr's flash driver and
CONFIG_FLASH_CROS option. Rename all the APIs in include/flash.h
BUG=b:187192628
BRANCH=none
TEST=make buildall -j4
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Change-Id: If1fd0ea28fa9f5cec1c1daa8f72f63eb7a0e6500
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2931749
Commit-Queue: Keith Short <keithshort@chromium.org>
Reviewed-by: Keith Short <keithshort@chromium.org>
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
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This renames IS_SLAVE_CHAN_ENABLE to IS_PERIPHERAL_CHAN_ENABLE.
BRANCH=none
BUG=b:163885307
TEST=buildall and compare_build.sh pass
Change-Id: Iaab11a2485fdcde3992ecb457c204465acfdf732
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2938042
Reviewed-by: Harry Cutts <hcutts@chromium.org>
Commit-Queue: Harry Cutts <hcutts@chromium.org>
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VW_PERIPHERAL_BTLD_STATUS_DONE
This replaces VW_SLAVE_BTLD_STATUS_DONE with
VW_PERIPHERAL_BTLD_STATUS_DONE.
BRANCH=none
BUG=b:163885307
TEST=buildall, compare_build.sh pass
Change-Id: I0b8c71fa7e590dc89357e22aafce0b67717af183
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2938041
Reviewed-by: Harry Cutts <hcutts@chromium.org>
Commit-Queue: Harry Cutts <hcutts@chromium.org>
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This updates some comments to be OSHWA friendly.
BRANCH=none
BUG=b:163885307
TEST=buildall and compare_build.sh pass
Change-Id: I9fdcf1a64febccb3622379ffb5f4e31efeb8bb12
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2938040
Reviewed-by: Harry Cutts <hcutts@chromium.org>
Commit-Queue: Harry Cutts <hcutts@chromium.org>
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This fixes a missing white space in a comment.
BUG=none
BRANCH=none
TEST=buildall passes
Change-Id: Ifde65ab45be7fa6881195ecf723d999d9991f2aa
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2921289
Reviewed-by: Boris Mittelberg <bmbm@google.com>
Commit-Queue: Boris Mittelberg <bmbm@google.com>
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There is a workaround to disable the JTAG selection when the JTAG is
enabled unexpectedly by the strap pin. In npcx9, the register to control
the JTAG selection is different. This CL uses the correct register to
let the workaround work correctly.
BRANCH=none
BUG=b:165777478
TEST=pass "make buildall"; check the register is correctly configured;
check JTAG can be disabled when "CONFIG_ENABLE_JTAG_SELECTION" is not
defined and JEN strap pin is pulled down on npcx9_evb.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Change-Id: Ic7a8a7d99335610cbacfb1de285cdd8fbda70848
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2867125
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: caveh jalali <caveh@chromium.org>
Reviewed-by: Keith Short <keithshort@chromium.org>
Commit-Queue: CH Lin <chlin56@nuvoton.com>
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Errata 2.22 requires that we disable the peripheral support while
enabling the peripheral channel. This workaround was only required for
NPCX5. This change removes the errata for NPCX7+. This workaround was
also racy. If the host read the capabilities before the PLTRST# interrupt
handler completed, then it might think that the device doesn't support
the peripheral channel.
BUG=b:188188172, b:188935533
BRANCH=none
TEST=Boot guybrush to the OS.
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I38bc7016280ab99135b1a9af8c76e4cceebfb605
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2912927
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
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The PLTRST# handler has a race condition. It sets the peripheral channel
ready bit before the IO ports are memory mapped. This means that the AP
can start sending IO requests before the mappings are ready.
BUG=b:188188172, b:188935533
BRANCH=none
TEST=On guybrush make an EC call after eSPI init. I no longer see a
failure. Also verify zork still boots.
Suggested-by: Rob Barnes <robbarnes@google.com>
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I09c58ef989b8bb90d7662afc63d23dc5498c293b
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2912090
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
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eSPI PUT_IOWR_SHORT protocol can send a max of 4 bytes of data in a
single transaction. This allows the host to send 4 bytes of the Port80
code at one time. This CL sets the bit OFS0_SEL~OFS3_SEL in the DPAR1
register to let the EC hardware put full 4-bytes of Port80 code to
DP80BUF FIFO. It also groups the 4-byte code into a single 32-bits
variable when necessary by analyzing the offset field in the DP80BUF
register.
BRANCH=none
BUG=b:184872297
TEST=build the image with "#define CONFIG_PORT80_PRINT_IN_INT 1";
connect npcx9_evb to the eSPI host emulator; the host sends a
PUT_IOWR_SHORT transaction to IO address 0x80 with 4 bytes of code
"0xEEE20400"; the EC console shows:
[63.694685 Port 80: 0xeee20400]
Then the host sends a single byte "0xaa" to Port80, the EC console
prints:
[576.531790 Port 80: 0xaa]
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Change-Id: I5dfbc0d08172042cb43d72eeb6f0e7da63feccf0
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2847668
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Raul E Rangel <rrangel@chromium.org>
Commit-Queue: CH Lin <chlin56@nuvoton.com>
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If platform uses PSL (Power Switch Logic) for hibernating and RTC is
also supported, this CL determines whether ec is woken up by RTC with
overflow event (16 weeks). If so, let it go to hibernate mode
immediately for better power consumption.
BRANCH=none
BUG=b:171919875
TEST= test console command "hibernate" with NPCX_LCT_MAX = 1000 and
enable chipset_task on npcx9 EVB.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Change-Id: I52543ee3cd980d444758c6a0cab32c34bd690b9a
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2835259
Reviewed-by: Wai-Hong Tam <waihong@google.com>
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In the original watchdog driver, we use an ITIM (auxiliary) timer to
check the watchdog counter periodically (every 1100 ms). If the counter
value is less than WDCNT_DELAY, which means more than 1600 ms has passed
since the last watchdog reloads, the watchdog panic should be issued.
However, this mechanism may cause the watchdog to happen randomly at
1600~2700 ms. This is because the aux timer and watchdog timer are not
aligned. In this CL, we aligned the watchdog timer and aux timer by
reloading both watchdog count and aux timer count in HOOK_TICK.
BRANCH=none
BUG=b:184681421
TEST=
1. "watims 1200", see panic trace printed but no EC reset.
2. "waitms 2000", see panic trace printed and EC reset.
2. "crash watchdog", see panic trace printed and EC reset.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Change-Id: Ic86d1b238d40fda76af9c38561e5669c13167a32
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2814041
Tested-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Wai-Hong Tam <waihong@google.com>
Commit-Queue: CH Lin <chlin56@nuvoton.com>
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Fixed NPCX_ESPICFG_IOMODE_FIELD and NPCX_ESPICFG_MAXFREQ_FIELD field
length. Added missing bits for ESPICFG and ESPIERR.
BUG=None
TEST=Build
BRANCH=None
Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I99d890804ea7eb4394b64684c03d111371000942
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2784842
Reviewed-by: Denis Brockus <dbrockus@chromium.org>
Reviewed-by: Diana Z <dzigterman@chromium.org>
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It was observed that in byra, when the "apshutdown" console command is
executed, the power state of EC is messed up. This was caused by the
SLP_Sx virtual wire is not updated due to the ungraceful global reset.
This CL adds a config option to let npcx EC reset SLP_Sx VW when
eSPI_RST is asserted.
Note: don't enable this config if the platform implements deep Sx entry
(e.g. KBL) for the reason per Intel eSPI spec. (scenario 3 in Table 7):
These pins retain state (0 or 1) until PCH/SoC exits Deep-Sx and PMC
sends a VW message to the EC with the new states for these pins.
BRANCH=none
BUG=b:179977907
TEST=pass "make buildall"
TEST=With the config defined, see the SLP_S4 virtual wire reset when
eSPI_RST is asserted.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Change-Id: I413b3d211537295b32c49b6e4a1797e48a26ec5f
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2766428
Tested-by: CH Lin <chlin56@nuvoton.com>
Tested-by: caveh jalali <caveh@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Commit-Queue: caveh jalali <caveh@chromium.org>
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Move the GPIO tables and the USB PRL states from .rodata to .data on
boards that support CONFIG_CHIP_DATA_IN_INIT_ROM.
This saves 1600 to 1900 bytes of flash space (and reduces RAM space by
the similar amount).
Boards affected:
delbin_npcx796fc
eldrid_npcx796fc
halvor
lindar
lingcod
magolor_legacy
malefor
metaknight_legacy
terrador
todor
trondo
voema
volteer_apmodeentry
volteer
waddledoo
BUG=none
BRANCH=none
TEST=make buildall
TEST=boot Volteer, run gpioget
Signed-off-by: Keith Short <keithshort@chromium.org>
Change-Id: I1a9f421981fb8db4d7ddd62b21d609a401862491
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2677087
Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
Commit-Queue: Abe Levkoy <alevkoy@chromium.org>
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Nothing uses this anymore, we can free up these indexes for future
use.
BUG=b:178689388
BRANCH=none
TEST=buildall
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: Id7df3091edc3a8d8d07ebdfb0347a26a51389163
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2668690
Reviewed-by: Edward Hill <ecgh@chromium.org>
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Rather than passing in the port and iterating over the global
spi_devices variable, pass in the specific spi_device that is being
enabled/disabled. The spi_device_t struct has the port.
This change makes the functions in spi.h more consistent since they now
all take a spi_device_t*. This change is the first step in making the
SPI configuration more dynamic.
BRANCH=none
BUG=b:177908650
TEST=git grep 'spi_enable(CONFIG' => no results
TEST=make buildall
TEST=Flash dragonclaw v0.2 and view console to verify FP sensor ID
Signed-off-by: Tom Hughes <tomhughes@chromium.org>
Change-Id: I64124e0ebcf898e88496acb77703b5f59ae931c2
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2654081
Commit-Queue: Abe Levkoy <alevkoy@chromium.org>
Reviewed-by: Abe Levkoy <alevkoy@chromium.org>
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The NPCX flash layout was setting the erase size based on RO image size
to ensure the host can erase the entire image using.
When 1/2 flash is smaller than code RAM, the NPCX reserves one 4 KiB
flash block for the NPCX header. This has the side effect of reducing
the erase block size from 64 KiB to 4 KiB, and introduces a boot time
regression when processing flash blocks.
CL:2325764 modified the common flash support to allow the host to
program up to CONFIG_WP_STORAGE_SIZE bytes for the RO image and
CONFIG_EC_WRITABLE_STORAGE_SIZE bytes for the RW image.
Set the erase size to a fixed value of 64 KiB, with build checks
to verify the total flash size is a multiple of 64 KiB.
Both the RO and RW image starting addresses are already aligned to at
least a 64 KiB boundary, so there is no impact when the RW firmware
is upgraded.
BUG=b:175115527
BRANCH=volteer
TEST=make buildall
TEST=Boot EC on Delbin with NPCX797FC
TEST=Increase the RW image size to 0x3ed1c (maximum is 0x3F000) and
verify EC software sync is successful at updating the image.
Signed-off-by: Keith Short <keithshort@chromium.org>
Change-Id: I8823da2b909dfa36646b411a146001c618ce0e8c
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2643579
Reviewed-by: caveh jalali <caveh@chromium.org>
Commit-Queue: caveh jalali <caveh@chromium.org>
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NPCX chip uses MFT as a tachometer module. The counter clock select is
not synced with the datasheet. For the LFCLK, the value of clock select
should be set to 4. This CL fix the LFCLK clock enumeration.
BUG=b:178376892
BRANCH=None
TEST=pass buildall
TEST=use PWM to generate the waveform to the tachometer. Check that the
tachometer gets the correct value by 'faninfo'.
Signed-off-by: Wealian Liao <whliao@nuvoton.corp-partner.google.com>
Change-Id: I22f47e0de403b144a8604e818db8f230764b4fc0
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2649292
Reviewed-by: Keith Short <keithshort@chromium.org>
Commit-Queue: Keith Short <keithshort@chromium.org>
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This corrects a confusing comment on what pwm_set_duty().
BRANCH=none
BUG=none
TEST=none
Change-Id: I6b3a094dafcbe10004ffbd76426e3398d8ef59de
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2639853
Reviewed-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Keith Short <keithshort@chromium.org>
Commit-Queue: Keith Short <keithshort@chromium.org>
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The original code fills out the entire TX buffer with status byte.
AP keeps pulsing the clock and tries reading status. EC DAM may
read the TX buffer during the write to response AP. A race may
happen.
Should leave a gap, like the gap for the PREAMABLE, when filling
TX buffer. The critical section of filling the TX buffer should be
done within the gap. It guarantees no race as DAM just reads the
old status. It may result one- or two-byte extra status response.
BRANCH=Trogdor
BUG=b:177021164,b:168682309
TEST=Reflashing different firmware images to trigger TCPC update.
No error happens for >20 rounds.
Change-Id: I842d7011f85ef9323fba2af01b9062a5166d38f4
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2628456
Reviewed-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
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In Zephyr CONFIG_FLASH_SIZE is a Kconfig value that is used
throughout. The issue is that the units don't match. In
Zephyr the value is in KiB instead of bytes. This refactor
simply renames CONFIG_FLASH_SIZE in platform/ec to include
the unit (via _BYTES).
BRANCH=none
BUG=b:174873770
TEST=make buildall
be generated by the build instead of per board
Signed-off-by: Yuval Peress <peress@chromium.org>
Change-Id: I44bf3c7a20fcf62aaa9ae15715be78db4210f384
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2627638
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Tom Hughes <tomhughes@chromium.org>
Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
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NPCX chip uses the MTC module as the RTC counter. However, in PSL
hibernate, MTC will stop counting. NPCX9 supports the LCT module which
could count continuously when VCC1 power is off. The CL uses LCT to
compensate for the MTC counter value after PSL hibernate wake-up. The
LCT maximum counting value is 16 weeks.
BRANCH=none
BUG=b:165777478, b:171919875
TEST=pass "make buildall"
TEST=Check the RTC value in the following scenario:
1. "hibernate" and wake up EC by PSL input.
2. "hibernate 30" and wake up EC after timeout.
3. "hibernate 30" and wake up EC by PSL input before timeout.
Signed-off-by: Wealian Liao <whliao@nuvoton.corp-partner.google.com>
Change-Id: I39e370a437f40749acbd3a35a8b37ebec70f1bf2
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2506864
Reviewed-by: Keith Short <keithshort@chromium.org>
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This is no longer needed as Zephyr does not rely on chip directory
anymore.
BUG=b:175249000
BRANCH=none
TEST=none
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I6f42ba1a16be5e874530f42412b4bf9c2853ee65
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2615131
Commit-Queue: Yuval Peress <peress@chromium.org>
Reviewed-by: Yuval Peress <peress@chromium.org>
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In npcx9, the internal flash is accessed via FIU/UMA (implementing in
chip/npcx/flash.c). It won’t use the common/spi_flash.c to access the
internal flash. This CL remove the two default configs related to the
SPI flash in the npcx9 chip config and fix the npcx9_evb setting for
the SPI flash.
BRANCH=none
BUG=b:165777478
TEST=buildall pass
Signed-off-by: Wealian Liao <whliao@nuvoton.corp-partner.google.com>
Signed-off-by: CHLin <CHLin56@nuvoton.com>
Change-Id: I7c525791d001fa2833b7d895f277768948783938
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2600807
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Keith Short <keithshort@chromium.org>
Commit-Queue: Keith Short <keithshort@chromium.org>
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This reverts commit a3dd3c3a941794bd6efcdfac0b70bfae7441ed29.
Reason for revert: chromium:1161113
board/npcx9_evb/board.c:103:4:error:
CONFIG_SPI_FLASH_PORTundeclared here
Original change's description:
> npcx9: remove unnecessary default CONFIGs for internal flash
>
> In npcx9, the internal flash is accessed via FIU/UMA (implementing in
> chip/npcx/flash.c). It won’t use the common/spi_flash.c to access the
> internal flash. Let’s remove these two default CONFIGs to prevent
> people from confusing.
>
> BRANCH=none
> BUG=b:165777478
> TEST=buildall pass
>
> Signed-off-by: Wealian Liao <whliao@nuvoton.corp-partner.google.com>
> Signed-off-by: CHLin <CHLin56@nuvoton.com>
> Change-Id: Id04dc9ff5402262b5cdf0815ae953ced777b5d96
> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2597124
> Reviewed-by: caveh jalali <caveh@chromium.org>
Bug: chromium:1161113
Change-Id: I57fb92418e71f8ce0ffd77bad34d4e5055552af1
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2600713
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Commit-Queue: Hung-Te Lin <hungte@chromium.org>
Tested-by: Hung-Te Lin <hungte@chromium.org>
Auto-Submit: Hung-Te Lin <hungte@chromium.org>
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In npcx9, the internal flash is accessed via FIU/UMA (implementing in
chip/npcx/flash.c). It won’t use the common/spi_flash.c to access the
internal flash. Let’s remove these two default CONFIGs to prevent
people from confusing.
BRANCH=none
BUG=b:165777478
TEST=buildall pass
Signed-off-by: Wealian Liao <whliao@nuvoton.corp-partner.google.com>
Signed-off-by: CHLin <CHLin56@nuvoton.com>
Change-Id: Id04dc9ff5402262b5cdf0815ae953ced777b5d96
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2597124
Reviewed-by: caveh jalali <caveh@chromium.org>
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Revert CL:2576439 and try again, this time checking for
EC_RESET_FLAG_HIBERNATE before setting EC_RESET_FLAG_INITIAL_PWR.
The problem with the first attempt was on sysjump to RW after wake
from hibernate. Then gpio_pre_init() saw EC_RESET_FLAG_INITIAL_PWR
but not EC_RESET_FLAG_HIBERNATE and so added an unwanted 2 second
delay because system_common_pre_init() hadn't yet restored the flags
from before the jump. Moving the check for EC_RESET_FLAG_HIBERNATE
into check_reset_cause() avoids this issue.
BUG=b:173180800
BRANCH=zork
TEST=no 2 second delay on wake from hibernate, for both RO boot
and jump to RW.
Signed-off-by: Edward Hill <ecgh@chromium.org>
Change-Id: Ia1bfba5740d77961ccc7e140da80be1070700b1e
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2592501
Reviewed-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Peter Marheine <pmarheine@chromium.org>
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There is an option in the task_set_event function which force
the calling task to wait for an event. However, the option is never
used thus remove it.
This also will help in the Zephyr migration process.
BUG=b:172360521
BRANCH=none
TEST=make buildall
Signed-off-by: Dawid Niedzwiecki <dn@semihalf.com>
Change-Id: Ic152fd3d6862d487bcc0024c48d136556c0b81bc
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2521599
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Tom Hughes <tomhughes@chromium.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
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Waking from PSL hibernate is power-on for EC but not for H1, so
we should not add the 2 second delay for CONFIG_BOARD_RESET_AFTER_POWER_ON
in this case.
BUG=b:173180800
BRANCH=zork
TEST=no 2 second delay on wake from hibernate
Signed-off-by: Edward Hill <ecgh@chromium.org>
Change-Id: Ib0c8f2ca7f197626b20a11e21ace44a5046db18b
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2576439
Reviewed-by: Peter Marheine <pmarheine@chromium.org>
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This sets a default value of 0 for NPCX_UART_MODULE2 and
NPCX9_PWM1_SEL so that board files don't need to set these.
BRANCH=none
BUG=b:173575131
TEST=buildall
Change-Id: Ief84ed558bb5431f13fb01b963db3bd97fc8d659
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2546639
Reviewed-by: CH Lin <chlin56@nuvoton.corp-partner.google.com>
Reviewed-by: Keith Short <keithshort@chromium.org>
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This change accomplishes 2 things:
1. It refactors the zephyr/shim directory to structure around
chip specific compilation. In this example, we're focusing
on npcx7m6fb which is used in volteer but others can be
added easily.
2. It shims the common/i2c_master.c by providing an alternate
implementation of i2c_xfer_unlocked that calls down to the
Zephyr API i2c_write_read instead of the chip specific
i2c_xfer_no_retry or chip_i2c_xfer_with_notify.
The shim layer is made possible by the addition of
zephyr/shim/include/i2c/i2c.h which adds a functions that
needs to be implemented per chip (npcx7 family in this case)
and allows us to map the current port int which is defined
in chip/${CHIP}/registers.h (chip/npcx/registers-npcx7.h in
our case). This function (i2c_get_device_for_port) maps the
platform/ec port int to a const struct device * which is
needed in the Zephyr I2C APIs.
BRANCH=none
BUG=b:171302975
TEST=clean_build.sh projects/experimental/volteer/ and make BOARD=eve
Signed-off-by: Yuval Peress <peress@chromium.org>
Change-Id: I210f4758337bf384d0d6f103eef8b89126887d11
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2504285
Reviewed-by: Simon Glass <sjg@chromium.org>
Commit-Queue: Simon Glass <sjg@chromium.org>
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The new I2C_STRIP_FLAGS macro was added to avoid conflict with
Zephyr's macro. This CL performs the migration to that new API.
BRANCH=none
BUG=b:172067439
TEST=make runtests -j and built for various boards: eve, volteer,
arcada_ish, atlas, hatch, kohaku, nocturne, samus, and scarlet
Change-Id: I0583b647435db96ec268f186252b367bdc4118a6
Signed-off-by: Yuval Peress <peress@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2511097
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Commit-Queue: Jett Rink <jettrink@chromium.org>
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Rename atomic_read_clear to atomic_clear to be consistent with the rest
of the atomic functions, which return the previous value of the
variable.
BUG=b:169151160
BRANCH=none
TEST=buildall
Signed-off-by: Dawid Niedzwiecki <dn@semihalf.com>
Change-Id: I2588971bd7687879a28ec637cf5f6c3d27d393f4
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2505143
Reviewed-by: Tom Hughes <tomhughes@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
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Make the unused pins as GPIO and disable any alt-function.
BRANCH=None
BUG=b:169595541
TEST=make buildall -j
Change-Id: I6b7c16dd68654b38c8a12654207438315fe86c2c
Signed-off-by: Wai-Hong Tam <waihong@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2508862
Reviewed-by: CH Lin <chlin56@nuvoton.com>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
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It is done as a part of porting to Zephyr.
Since the implementation of atomic functions is done for all architectures
use atomic_* instead of deprecated_atomic_*.
Sometimes there was a compilation error "discards 'volatile' qualifier"
due to dropping "volatile" in the argument of the functions, thus
some pointers casts need to be made. It shouldn't cause any issues,
because we are sure about generated asm (store operation will be
performed).
BUG=b:169151160
BRANCH=none
TEST=buildall
Signed-off-by: Dawid Niedzwiecki <dn@semihalf.com>
Change-Id: I98f590c323c3af52035e62825e8acfa358e0805a
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2478949
Tested-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Tom Hughes <tomhughes@chromium.org>
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