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* npcx: Preserve default values of HW_WIREFurquan Shaikh2018-03-021-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | NPCX7 requires that the HW_WIRE bits 2-0 of VWEVSM2 register are set so that the hardwire signals for SCI, SMI and RCIN are connected to VW input of eSPI_SIF module. NPCX5 did this by default, however NPCX7 has made it configurable. NPCX7 however sets the HW_WIRE bits 2-0 to 1 at reset. So, this change ensures that they are preserved while initializing VWEVSM2 registers BUG=b:74111394 BRANCH=None TEST=Verified that SCI works on glkrvp and meowth with NPCX7. Change-Id: I9da6f45b4aa0b72b68db6192cb7567f09b072f0c Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/943801 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Divya S Sasidharan <divya.s.sasidharan@intel.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: ML Chao <mlchao@nuvoton.corp-partner.google.com> Reviewed-by: Jett Rink <jettrink@chromium.org>
* npcx/fan: Make all fans in RPM mode workDaisuke Nojiri2018-02-281-2/+1
| | | | | | | | | | | | | | | Currently, if there is a fan which isn't in RPM mode, the rest of the fans are not controlled even if they're in RPM mode. This patch gives a chance to all the fans. BUG=b:35543471 BRANCH=none TEST=none Change-Id: I6f930bad313bc2a31497f46647ab2b08e328dfff Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/940813 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* npcx7: WoV: Add support for Wake-on-Voice (WoV) moduleCHLin2018-02-288-4/+3755
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This CL adds the driver support for the WoV module which inludes the following files: - wov.c - wov_chip.h - apm.c - apm_chip.h It also supports the console commad "wov" which can test different configuration and audio quality by entering different parameters. The detail description of WoV console command is listed below: ------------------------------------------------------------------------ [Note]: Before changing any of settings, please make sure the operation mode is on the "OFF" state. (ie. run the command wov cfgmod off first) . > wov init Initialize WoV interface, including pin mux and interrupt registration etc. > wov mute <enable / disable > mute enable / disable. > wov cfgsrc <mono | stereo | left | right> set audio source, ex: wov cfgsrc left, means audio source from left MIC. > wov cfgbis <16|18|20|24> set audio resolution, ex: wov cfgbit 16 means audio resolution are 16bits. > wov cfgsfs <8000|12000|16000|24000|32000|48000> set audio sampling frequency rate, ex: wov cfgsfs 48000 means audio sampling rate are 48Khz. > wov cfgbck <32fs|48fs|64fs|128fs|256fs> set I2S bit clock rate, ex: wov cfgsfs 48000 and wov cfgbck 32fs means audio sampling rate are 1536Khz (32*48000). > wov cfgfmt <i2s|right|left|pcma|pcmb|tdm> set I2S but format, ex: wov cfgfmt right means audio I2S format are Right-Justify. > wov cfgmod <off|vad|ram|i2s|rami2s> set audio operation mode ,ex: wov cfgmod i2s means audio output via I2S bus. > wov cfgtdm <0~496 0~496 0~3> set TDM time slot, the first values is left channel delay counter, the second is right channel, and the 3rd is startup counting condition. (chosen LRCK raising or falling edge) . [Note: this command is just working on cfgmod equal to tdm] > wov cfgget retrieve above settings. > wov vadsens (currently not support, reserve for next version) > wov gain (0~31) set audio data gain value, ex: wov gain 10 means setting audio digital gain are 10dB. > wov cfgdck <1.0 | 2.4 | 3.0 > set digital MIC PDM clock rate. ex: wov cfgdck 2.4 means PDM clock are 2.4Mhz. ----------------------------------------------------------------------- This CL also adds the chip ID (0x24) for npcx7m7w. So the console command "version" can show the chip is npcx7m7w. BRANCH=none BUG=none TEST=No build errors for make buildall. TEST="BOARD=npcx7_evb make"; Flash the image on EVB; Test WoV function with console commands described above. Change-Id: Ief2b3e89edbd3e6d2a9d82d317a93c9f0b7a20cd Signed-off-by: Dror Goldstein <dror.goldstein@nuvoton.com> Signed-off-by: Simon Liang <CMLiang@nuvoton.com> Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/897314 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Scott Collyer <scollyer@chromium.org>
* npcx/fan: Avoid turning on disabled fansDaisuke Nojiri2018-02-261-0/+3
| | | | | | | | | | | | | | | Fan enable state is controlled in common/fan.c. This patch prevents npcx fan driver from enabling it. BUG=b:73127788 BRANCH=none TEST=Verify no 'Fan 0 stalled' is printed in S3 and S5. Verify the fan spins in S0. Change-Id: I549253a64c91d8a23bb793c3506b5daf1f7642be Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/937941 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* npcx: Set ESPI_MAXFREQ based on FMCLK valueFurquan Shaikh2018-02-201-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | According to NPCX data sheets (NPCX5 and NPCX7), ESPI_MAXFREQ should be decided based on the value of FMCLK. Since we are setting FMCLK to 30MHz on NPCX5, eSPI_MAXFREQ needs to be set to 33MHz. This change sets ESPI_MAXFREQ_MAX depending upon the value of FMCLK. BUG=b:73504527 BRANCH=fizz? TEST=Verified that on soraka ESPI_MAXFREQ is set to 33MHz. Also, ran some reboot tests to ensure that there is no regression in boot time. Change-Id: Iaee89078741cf44c7ac232e2ee14d75384f68a35 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://chromium-review.googlesource.com/925843 Commit-Ready: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-by: caveh jalali <caveh@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* lpc: Removing unnecessary register writesJett Rink2018-02-161-6/+1
| | | | | | | | | | | | | | | | | | | | According to Nuvoton datasheet, when SHM windows are in IO mode, only the bottom 16-bits of registers @ offset xF4 and xF8 are used. "This register is ignored when WRAM1_IO bit in WIN_CFG register is set to 1 (LPC / eSPI Peripheral Channel I/O access with 16-bit address). This register is set to its default value by Host Domain reset." BRANCH=none BUG=none TEST=boot grunt and verify host communication still works. Change-Id: I3e48ea1b09355eaf6967b9f7522bc3d35459b76b Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/919006 Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
* npcx: set eSPI speed to max supported by hardwareCaveh Jalali2018-02-152-3/+12
| | | | | | | | | | | | | | | | | | the npcx7 can only run eSPI at (up to) 50MHz while the npcx5 can go up to 66MHz. so, set the max speed to whatever the hardware can actually do. the bit pattern for 66MHz is "reserved" on the npcx7, so let's not even define it in the npcx7 case. BUG=b:72838699, b:71859563 BRANCH=none TEST="make buildall" passes; boots on meowth Change-Id: I428caf72a41fe58008df4624c475dafadca4a0bc Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/910321 Commit-Ready: caveh jalali <caveh@chromium.org> Tested-by: caveh jalali <caveh@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* npcx: do not power down eSPI when enabledCaveh Jalali2018-02-122-4/+11
| | | | | | | | | | | | | | | | | | | | if we're using eSPI for connectivity to the AP, we should never power it down... powering it down just causes transient errors on eSPI. BUG=b:72838699 BRANCH=none TEST=booted on meowth, no more eSPI bus errors. Change-Id: I737a03bb745868c7e8e02ffd5607db4d2da74c30 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/910320 Commit-Ready: Caveh Jalali <caveh@google.com> Tested-by: Caveh Jalali <caveh@google.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
* Nami: Enable hibernate using silegoElthan_Huang2018-02-122-3/+4
| | | | | | | | | | | | | | | | | | | | Nami EC has EC_HIBERNATE pin connected to a silego (U91). When this pin is asserted, U91 shuts down ROP_PMIC_ENVR3, which turns off the EC. Thus, we don't use the internal hibernate/wake-up feature in npcx. BUG=b:72641658 BRANCH=none TEST=Test system will shutdown and doesn't auto wake up when type hibernate in ec console. And wake up by AC plugin, LID open, or power button. Change-Id: Ib9e02f7e41087e5972eedf4855d88a4c45c75bb4 Signed-off-by: Elthan_Huang <elthan_huang@compal.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/890569 Commit-Ready: Daisuke Nojiri <dnojiri@chromium.org> Tested-by: Raymond Chou <raymond_chou@compal.corp-partner.google.com> Reviewed-by: Raymond Chou <raymond_chou@compal.corp-partner.google.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* lpc: Prevent watchdog reset caused by KBC IBF interrupt on chromebox.Mulin Chao2018-02-081-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | Since there is no KEYPROTO task on chromebox such as fizz and sion, lpc driver doesn't declare KBC IBF/OBE ISRs for these events. If host put data in ec's KBC input buffer unexpectedly, exception_panic() will be executed in default_handler. Then we will see ec print "=== PROCESS EXCEPTION: 29 ====== xPSR: 01000000 ===" message without any hard fault and reset. This CL fixed this symptom by turning off KBC if there is no KEYPROTO task. We also run suspend stress test on fizz and no watchdog reset symptom occurred. BRANCH=none BUG=b:72353876 TEST=No build errors. Run suspend stress test on fizz and no watchdog reset occurred. Change-Id: I4744fac0d6fb2628849c728d4860509434fa2cbb Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/899706 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@google.com>
* cleanup: formatting debug messageJett Rink2018-02-011-4/+3
| | | | | | | | | | | | | Adding newline to separate messages better BRANCH=none TEST=none BUG=none Change-Id: Ie454dfc532310c480f350c9b15280bf96634b322 Signed-off-by: Jett Rink <jettrink@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/897909 Reviewed-by: Edward Hill <ecgh@chromium.org>
* Nami: force to set RESET_FLAG_RESET_PINElmo_Lan2018-01-301-1/+1
| | | | | | | | | | | | | | | | | Like other KBL designs (eve, poppy and followers). EC is not able to distinguish between power up and reset. BUG=b:71839731 BRANCH=none TEST=Verify Nami power on flag by EC console. Change-Id: Ice8b80259b8405f28b508918d5b3cfe37a8b1eb9 Signed-off-by: Elmo_Lan <elmo_lan@compal.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/891042 Commit-Ready: Raymond Chou <raymond_chou@compal.corp-partner.google.com> Tested-by: Elmo Lan <elmo_lan@compal.corp-partner.google.com> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Elmo Lan <elmo_lan@compal.corp-partner.google.com>
* npcx7: Add definition/configuration for npcx7m6xb/npcx7m7wCHLin2018-01-175-10/+51
| | | | | | | | | | | | | | | | | | | | | | | | In this CL, we add the following changes to support the CHIP_VARIANT npcx7m6xb and npcx7m7w: 1. Define the code RAM, data RAM, BBRAM base address/size. 2. Initialize the wov.c file for WoV driver development. (It will be compiled only when CHIP_VARIANT=npcx7m7w in the build.mk and CONFIG_WAKE_ON_VOICE is defined in board.h) 3. Fix the the incorrect offset of PWDWN_CTRL7 register. BRANCH=none BUG=none TEST=No build errors for make buildall. TEST=Change CHIP_VARIANT to npcx7m7w/npcx7m6xb in board/npcx7_evb/build.mk; "BOARD=npcx7_evb make"; Check ec image can be built. Flash the image on EVB; make sure EVB bootup. Change-Id: I87bccb9097f8f0a6c67f96a8d90adf201ae9e773 Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/858637 Commit-Ready: CH Lin <chlin56@nuvoton.com> Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* npcx/uart: Pull up communication line during transactionNicolas Boichat2018-01-041-0/+9
| | | | | | | | | | | | | | | | | Boards needs to define GPIO_EC_COMM_PU, which needs to be driven high during EC-EC transaction. This makes sure that the line does not go low, even when the base goes away during the transaction. BRANCH=none BUG=b:68954760 TEST=EC-EC communication works with this change. TEST=With signal analyzer, check that UART line is always kept high while transaction is in progress. Change-Id: Iad7b26a9a93b674aa4fff0bc3a72a13e6782515d Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/845544 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* npcx: modify the npcxspiflash little firmware to support UUTCHLin2018-01-036-116/+161
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The original ec_npcxspiflash lfw is used by the openocd to program SPI flash via Servo JTAG. In order to support UUT mode to program SPI flash, this CL modified the lfw with the following changes: 1. Rename the lfw ec_npcxflash to npcx_monitor to unify the naming. 2. The npcx_monitor will read the first 4 bytes from the area of monitor header. If the monitor identifies the first 4 bytes is a UUT tag, it will read parameters(SPI_OFFSET/IMAGE_SIZE) from the relative offset of monitor header. Otherwise, it will read parameter from the general register r0/r1 which will be restored by openocd script in advance. 3. Add monitor_hdr.c to generate the monitor header binary files (monitor_hdr_ro.bin/monitor_hdr_rw.bin)) automatically after compiled. The memory layout to restore the reuqired binaries are listed below: ec firmware(RO/RW) - the start address of Code RAM area. monitor header - 0x200C3000 npcx_monitor - 0x200C3020 BRANCH=none BUG=none TEST=No build errors for "make buildall". TEST=Follow instructions in CL:826763; make sure the ec firmware is updated and ec can boot up. CQ-DEPEND=CL:828341 Change-Id: I5de997a4dee5449d578972e2f929c6e08c5dff67 Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/826909 Commit-Ready: CH Lin <chlin56@nuvoton.com> Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* system: Log PC and task id on watchdogPhilip Chen2017-12-111-14/+0
| | | | | | | | | | | | | | | | | | | | | | | | | For debug, in common code let's log the watchdog PC and task id as our SW panic params. BUG=chromium:790006 BRANCH=none TEST=manually test scarlet rev2 from a1-a3, b1-b2: (a1) Add 'while(1);' in button ISR (a2) Boot and press the button (a3) When watchdog is triggeried, check with 'panicinfo' that saved R5 is the PC for button ISR. (b1) 'crash watchdog' in EC console (b2) Check with 'panicinfo' that CONSOLE task id is saved in EXCEPTION and PC is saved in R5. Change-Id: I64d2fcf594dd24b0951e002ab8e80ebcac2d1def Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/803618 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* system: Allow hibernate to clear AP_OFF flagDaisuke Nojiri2017-12-051-1/+9
| | | | | | | | | | | | | | | | | | | After firmware update, cr50 toggles the EC's reset line, expecting the system will boot. This isn't the case for Chromebox because it sets AP_OFF flag on a clean shutdown (to restore the previous power state after power loss & restore). This patch adds EC_REBOOT_HIBERNATE_CLEAR_AP_OFF to EC reboot command. It makes EC first clear AP_OFF then hibernate. BUG=b:69721737 BRANCH=none TEST=Verify Fizz reboot after cr50 update. Change-Id: If3207d7284f244ca1adf0d516ef744dbc739a9c1 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/802632 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* npcx: unset ESPIRSTWE bit to prevent ec cannot enter low power modeCHLin2017-11-282-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | This CL fixed the issue that ec cannot enter low power mode, which increases more power consumption in s5, by not setting ESPIRSTWE bit. For more detail, please see the npcx5's errata rev1_7, No.2.21. BRANCH=none BUG=b:69351155 TEST=No build errors for "make buildall". TEST=build and flash soraka, run commands to read the power consumption: dut-control pp3300_dsw_ec_cfg_reg:0x7327k dut-control pp3300_dsw_ec_mw -t 20 | grep "@@" the average power consumption measured reduces from 42.x to 10.x mw. TEST=do cold reboot stress test for 4 hours and no symptom occurred. Change-Id: Ic6fd7fe14ae8acaefd4e1a99ca1625254f67d708 Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/778709 Commit-Ready: CH Lin <chlin56@nuvoton.com> Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* host_events: Bump up host events and masks to 64-bitFurquan Shaikh2017-11-212-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | With the upcoming change to add a new command to get/set/clear host events and masks, it seems to be the right time to bump up the host events and masks to 64-bit. We are already out of available host events. This change opens up at least 32 bits for new host events. Old EC commands to operate on host events/masks will still deal with lower 32-bits of the events/mask. On the other hand, the new command being added will take care of the entire 64-bit events/masks. This ensures that old BIOS and kernel versions can still work with the newer EC versions. BUG=b:69329196 BRANCH=None TEST=make -j buildall. Verified: 1. hostevent set 0x4000 ==> Sets correct bit in host events 2. hostevent clear 0x4000 ==> Clears correct bit in host events 3. Kernel is able to query and read correct host event bits from EC. Verified using evtest. 4. Coreboot is able to read correct wake reason from EC. Verified using mosys eventlog list. Change-Id: Idcb24ea364ac6c491efc2f8dd9e29a9df6149e07 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/770925 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* system: Add wait-ext option to ec reboot commandScott Collyer2017-11-151-14/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | EC_IN_RW signal is used to determine if the switch to dev mode can be safely made. However, EC_IN_RW needs the EC_RST_L line driven low in order to be reset. In faft tests that utilize crosEcSoftrecPower method, EC_RST_L is not being driven by servo to fix other test failures related to keeping EC and AC reboots in sync. This CL adds a new argument 'wait-ext' to the EC reboot command. When this option is used, instead of the EC generating a reset via it's system watchdog, it will wait 10 seconds for EC_RST_L to be driven. BUG=b:64603944 BRANCH=coral CQ-DEPEND=I086687c3dd7591460099267880d56ab8265d2e4b TEST=Ran "/usr/bin/test_that --board=coral <ip addr> firmware_DevMode" mutliple times and verified that it passes. Previoulsy, this test always fails when the EC is in RW before it starts. Also tested platform_ServoPowerStateController_USBPluggedin and verified it passed. Change-Id: I614f9156066d5719601ee43e29c7a064f9bba6e2 Signed-off-by: Scott Collyer <scollyer@google.com> Reviewed-on: https://chromium-review.googlesource.com/737524 Commit-Ready: Scott Collyer <scollyer@chromium.org> Tested-by: Scott Collyer <scollyer@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* npcx: Use compatible MPU configShawn Nematbakhsh2017-11-142-48/+7
| | | | | | | | | | | | | | | | MPU is already configured for access restriction in cortex-m core code so take care not to conflict. BUG=chromium:782244 BRANCH=None TEST=Build + boot on kevin, verify hibernate doesn't panic. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I9903cbc69002529ebbfa3fc1be3de4f74264e4aa Reviewed-on: https://chromium-review.googlesource.com/759157 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* npcx: fixed the assembly code of deep idle bypassCHLin2017-11-091-6/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The original assembly code of deep sleep bypass will cause build error if both CONFIG_LOW_POWER_IDLE and CONFIG_LTO are defined when buildiing board glkrvp/zoombini. This CL fixed it by change the bypass assembly code from: asm ("push {r0-r5}\n" "ldr r0, =0x100A8000\n" "wfi\n" "ldm r0, {r0-r5}\n" "pop {r0-r5}\n" "isb\n" ); to: asm ("push {r0-r5}\n" "wfi\n" "ldm %0, {r0-r5}\n" "pop {r0-r5}\n" "isb\n" :: "r" (0x100A8000) ); BRANCH=none BUG=none TEST=No build errors for "make buildall". TEST=build zoombini/glkrvp with CONFIG_LOW_POWER_IDLE and CONFIG_LTO, no build errors. TEST=build npcx7_evb/npcx_evb and do stress test for deep idle->wakeup on EVB, no symptom observed. Change-Id: I90b13b4baf418e3f4b3234d4811e3978b6436aac Signed-off-by: Vincent Palatin <vpalatin@chromium.org> Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/756535 Commit-Ready: CH Lin <chlin56@nuvoton.com> Tested-by: CH Lin <chlin56@nuvoton.com>
* port80: Provide default routine for logging port80 resumeFurquan Shaikh2017-10-311-7/+0
| | | | | | | | | | | | | | Add a common hook handler on CHIPSET_RESUME to log port80 resume message instead of duplicating the same code in all chip lpc_resume. BUG=b:68669668 BRANCH=None TEST=Verified that port80 resume is logged on S0ix and S3 resume. Change-Id: I313692f5499717d0d8f62be2ba3b8566c46e4dde Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/745362 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* lpc: Add and use lpc_resume_clear_masksFurquan Shaikh2017-10-311-10/+0
| | | | | | | | | | | | | | | | | | | | | Add a new LPC helper routine lpc_resume_clear_masks that can be used to clear SCI, SMI and wake masks upon resume from S3. This is done to mask the events until host explicitly unmasks them. It also ensures that these masks do not get reset on resume from S0ix where the host does not re-configure these masks. BUG=b:68669668 BRANCH=None TEST=Verified following: 1. make -j buildall 2. On resume from S0ix, SCI mask is not reset. 3. On resume from S3, SCI mask is reset and then set again by host request. Change-Id: I17a86bd60ef066b3716fb79ecce62f311eb45509 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/745533 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* npcx: espi: fixed bug that ec cannot wakeup from deep idle by VW eventsMulin Chao2017-10-292-9/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | According npcx ec wake-up mechanism by espi VW events, the driver needs to make sure the IE/WE bits in VWEVMSn and the VWUPD bit in ESPIWE registers are both set. Or ec won't wakeup by VW signals until the other wake-up events occured. (WE bit of VWEVMSn is introduced on npcx7.) In this CL, we turn on IE/WE bit in VWEVMSn registers during espi driver initialization and toggle the bits of ESPIWE register for VW and general events such as ESPI_RST and so on when ec turn on/off host interface's interrupts to make sure ec can wake-up from deep idle by espi events in time. BRANCH=none BUG=none TEST=No build errors for npcx5/7 series. Using "suspend_stress_test -c 1000" to do stress test and no symptom occurred on poppy. Both warmboot and coldboot stress test for 5 hours and no symptom occurred on poppy. Change-Id: I853532508bf9da5f3abc39e20ab848e659ca5e26 Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/725559 Reviewed-by: Amit Maoz <amit.maoz@nuvoton.corp-partner.google.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* npcx/uart: Disallow deep sleep when alternate pad is selectedNicolas Boichat2017-10-251-6/+23
| | | | | | | | | | | | | | | | | | | Also, fix uart_rx_available to only call clock_refresh_console_in_use when the default pad is selected. BRANCH=none BUG=b:65526215 TEST=On Lux, EC console works, so does pad-switching EC-EC comm, and idlestats shows that the EC goes to deep sleep. TEST=In uart_alt_pad_write_read, increase usleep time in loop from 100 to 10000 (the shorter 100us time prevents EC from going into deep sleep during the transaction), no transaction error in EC-EC communication when system goes into deep sleep. Change-Id: I3855b07f37def0ac9cfd700318ba64c432d3c42b Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/735103 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* npcx/uart: Simplify UART register handlingNicolas Boichat2017-10-252-56/+63
| | | | | | | | | | | | | | | | | | | Define NPCX_UART_* macros instead of having so many ifdef NPCX_UART_MODULE2 in the code. Also, do not set NPCX_WKEDG bit in npcx_uart2gpio: instead set it in uart_config just just like NPCX7 does it. BRANCH=none BUG=b:65526215 TEST=On Lux, EC console works, so does pad-switching EC-EC comm. TEST=Flash soraka, using "idlestats", check that EC goes into deep sleep, and that it can be woken up typing in EC console. Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Change-Id: I84b4f980fa79ed43640df4afc23cdc24cca21d99 Reviewed-on: https://chromium-review.googlesource.com/730029 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* chip/npcx: Add support for pad-switching UARTNicolas Boichat2017-10-254-38/+247
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | NPCX5* only has one UART controller, which can be switched between 2 pads. We keep the default pad for EC console, however, we allow switching to the alternate pad for short, infrequent, transactions. Both pads are assumed to use the same baudrate and other line settings. When switching pad, we first configure the new pad, then switch off the old one, to avoid having no pad selected at a given time, see b/65526215#c26. Because of the added complexity of npcx_gpio2uart (and the fact that it uses the global variable "pad" define in uart.c), we move the implementation to uart.c (npcx_uart2gpio is also moved for consistency). When the pad is switched to alternate pad, characters input and output on the EC console (default pad) would be lost. To compensate for this, we: - Switch back to main pad in case of EC panic, so that output is shown on EC console. - Immediately abort current alternate pad transaction if a character is received on the default pad. Note, however, that the first character will be lost (this can be worked around by telling user to press enter, and have servod/FAFT always send 2 blank lines (instead of just one) before sending a command). - Inhibit pad switching for 500ms after receiving a character on default pad. Assuming a reasonable typing speed, this should allow developers to type console commands relatively comfortably, while not starving the alternate pad communication for too long. The logic above could be simplified significantly by implementing software flow control (XON/XOFF, see b/67026316). BRANCH=none BUG=b:65526215 TEST=While follow-up CL that writes long 1k buffers, the following works fine: - type 'uart' in EC console - Read battery power consumption from servod, which "types" in the EC console: while true; do dut-control ppvar_vbat_mw; sleep 1; done no failure is seen. TEST=Add this test code in uart_alt_pad_read_write, after the pad has been switched, and check that panic information is consistently printed correctly: { static int t; if (t++ > 20) t = t / ret; } Change-Id: I18feed2f8ca4eb85f40389f77dac3a46315310e7 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/659458 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* ec: add initial nautilus boardChris Wang2017-10-231-1/+3
| | | | | | | | | | | | | | For now use the files from poppy. To be changed later on. BUG=b:66458931 TEST=emerge-nautilus chromeos-ec/make buildall -j Change-Id: If829d7307f834f1f30878934623c0e9ee77b907d Signed-off-by: Chris Wang <chriswang@ami.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/701996 Commit-Ready: Grace Kao <grace.kao@intel.com> Tested-by: Grace Kao <grace.kao@intel.com> Reviewed-by: Philip Chen <philipchen@chromium.org>
* host_event: Move host events and mask handling into common codeFurquan Shaikh2017-10-171-86/+17
| | | | | | | | | | | | | | | | | | | | Instead of duplicating the handling of host events and host event masks in chip lpc drivers, add routines in common code to provide basic functions like setting/getting of masks, setting/getting of events and handling of masks transitions across sysjump. BUG=None BRANCH=None TEST=make -j buildall. Verified following: 1. Event masks are correctly retained across sysjumps. 2. Wake from S3 works fine. 3. Wake from S0ix works fine. 4. SCI generated correctly. Change-Id: Ie409f91b12788e4b902b2627e31ba5ce40ff1d27 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/707771 Reviewed-by: Shawn N <shawnn@chromium.org>
* npcx/flash: not enable the flash pinmux when using internal flashCHLin2017-10-152-0/+6
| | | | | | | | | | | | | | | | | | | | | | In npcx5, the flash interface pinmux should be turned on in order to access the external flash. However, in npcx7, the internal flash is used. It is meaningless to turn the pinmux on. And it also causes the alternative function of these pins not work normally(such as GPIOA0/GPIOA2) if the pinmux is enabled. This CL uses the preprocessor flag NPCX_INT_FLASH_SUPPORT to conditionally prohibit the execution of flash pinmux code. BRANCH=none BUG=none TEST=No build errors for "make buildall". Build npcx_evb and npcx7_evb boards, make sure the pinmux are correctly configured seperately. Change-Id: Iba2300159f204b65d15852ec1755714df0c64816 Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/704316 Commit-Ready: CH Lin <chlin56@nuvoton.com> Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* chip/stm32/clock: Allow the host to reset rtc alarmPhilip Chen2017-10-021-1/+1
| | | | | | | | | | | | | | | | | | | | | When the host sets rtc alarm wake time = 0, it wants to reset and disable the alarm. Also, align the implementation in npcx with that in stm32 to check both delay_s and delay_us. BUG=b:66971951, b:63908519 BRANCH=none TEST='ectool rtcsetalarm 3'. After alarm goes off, run 'ectool rtcgetalarm' and then see 'Alarm not set'. Change-Id: I693f1c72cba492e837891c716f79e2aa4da59b2a Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/691256 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-by: Brian Norris <briannorris@chromium.org>
* npcx: espi: Fixed the bug which ec cannot enter deep sleep on npcx7.Mulin Chao2017-09-281-0/+8
| | | | | | | | | | | | | | | | | | | In npcx7, we introduced a new bit, VWUPDW, in ESPISTS register to indicate a Master-to-Slave VW signal was updated and the relevant WE bit is 1. But there's no relevant IE bit in ESPIIE for VWUPDW, old mechanism for clearing pending bits of ESPISTS will ignore this bit. And ec cannot enter deep sleep anymore since this bit is set. This CL fixed this bug by setting bit 17 of mask variable if ec is npcx7 series. BRANCH=none BUG=none TEST=No build errors for npcx5/7 series. Change-Id: I80c57d3c230e9d06ba134538ccdcd29f290bb7bf Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/672183 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Amit Maoz <Amit.Maoz@nuvoton.com>
* npcx: espi: Add new bit fields of eSPI regs and remove useless ones.Mulin Chao2017-09-281-36/+71
| | | | | | | | | | | | | | | | | | | | | | | | | In this CL, we introduced new bit fields of eSPI registers on npcx5/7 for the incoming patches. We also remove useless registers such as VWGPMS, VWGPSM and PING in order to let the driver look more clearly. This CL also includes: 1. Fixed typo from ESPIIWE to ESPIWE. 2. Introduce ESPIWE bits fields on npcx5/7. 3. Introduce new bit fields in ESPISTS of npcx7. 4. Remove useless VW1-4, VW1IE1-4 bits in ESPISTS and ESPIIE registes. 5. Introduce new bit field, WE, in VWEVMSn register of npcx7. BRANCH=none BUG=none TEST=No build errors for npcx5/7 series. Using "suspend_stress_test -c 1000" to do stress test and no symptom occurred on poppy. Both warmboot and coldboot stress test for 3 hours and no symptom occurred on poppy. Change-Id: Ie8aa3dbd148588b0d9a756572d66604a6836a760 Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/672026 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Amit Maoz <Amit.Maoz@nuvoton.com>
* cleanup: Remove jtag_pre_init()Shawn Nematbakhsh2017-09-074-32/+25
| | | | | | | | | | | | | | | Use our newly-created chip_pre_init() for doing JTAG initialization. BUG=chromium:747629 BRANCH=None TEST=`make buildall -j` Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Ic5771895a214a9f1aa9bd289eef576f52adf973f Reviewed-on: https://chromium-review.googlesource.com/629676 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* npcx: bypass for CSAE issue if CONFIG_LOW_POWER_IDLE is disabledMulin Chao2017-09-051-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | In order to prevent keeping the CSAE bit at 1 forever impacts the eSPI performance, the npcx driver enables host access wakeup functionality before ec enters deep sleep or wfi. But this bypass also should be added in __idle() of core/cortex-m/task.c if CONFIG_LOW_POWER_IDLE is disabled. This CL also narrows the bypass only when host interface is eSPI. BRANCH=eve BUG=b:64730183 TEST=No build errors for make buildall. Disable CONFIG_LOW_POWER_IDLE functionality on poppy and use following script "count=0; while :; do echo "--- iteration --- $count"; time flashrom -p ec -r ec.bin; sleep 1; count=$((${count}+1)); done" to test eSPI performances over 300 times. No errors occur and all tests' efficiency are the same as removing CSAE bypass. Change-Id: I8b6b69e37318208c185747151c06b3e6bdfd2f4e Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/644967 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* EFS: Rename CONFIG_VBOOT_EC to _EFSDaisuke Nojiri2017-08-291-1/+1
| | | | | | | | | | | | | | This patch renames CONFIG_VBOOT_ET to CONFIG_VBOOT_EFS. It also adds the macro to config.h. BUG=none BRANCH=none TEST=make buidlall Change-Id: I7cb9f4c73da635b36119db74bac6fe26e77a07d2 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/639955 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* npcx: Don't enable CONFIG_CMD_FLASH_TRISTATE when internal flash is usedCHLin2017-08-231-0/+3
| | | | | | | | | | | | | | | | | | | The bit controlling the tri-state of FIU pins is reserved when the internal flash is used and should not be modified. This CL adds a compiler error to prevent this kind of misuse. BRANCH=none BUG=none TEST=No build errors for "make buildall". "BORAD=npcx7_evb make" with CONFIG_CMD_FLASH_TRISTATE defined, make sure the error message is printed. Change-Id: I020c8ab9e02b9a377879bbd2a337943e77a369d6 Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/624828 Commit-Ready: CH Lin <chlin56@nuvoton.com> Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* npcx: bypasses for SHM reading fail via eSPI and CSAE impact efficiencyMulin Chao2017-08-212-12/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In eSPI systems, when the host performs a data read from the Shared Memory space, the returned data may be corrupted. This is a result of the Core-to-Host access enable bit being toggled (by toggling CSAE bit in SIBCTRL register) during an eSPI transaction. The bypass for this symptom is to set CSAE bit to 1 during initialization and remove the toggling of CSAE bit from other EC firmware code. But keeping the CSAE bit at 1 forever also impacts the eSPI performance a lots. When the core clock is stalled by sleep, deep sleep or wfi instruction, the eSPI Peripheral Channel transaction is stalled if this bit is set. The bypass for this symptom is to wake up the core by eSPI peripheral channel transaction and let eSPI module handle the remaining packet. BRANCH=eve BUG=b:64730183 TEST=No build errors for make buildall. Flash poppy ec image, make sure it can boot to OS. Run "ectool version" over 100000 times, no error occurs. Use following script "count=0; while :; do echo "--- iteration --- $count"; time flashrom -p ec -r ec.bin; sleep 5; count=$((${count}+1)); done" to test eSPI performances over 1000 times. No errors occur and all tests' efficiency are the same as removing CSAE bypass. Change-Id: I1b9051c5a3d368a5917882d9d1c3bb00481a53ad Signed-off-by: CHLin <CHLIN56@nuvoton.com> Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/620301 Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* npcx: shi: add the support for SHI module version 2CHLin2017-08-174-44/+210
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In npcx7, we introduce an enhanced version of Serial Host Interface (SHI) module. This CL adds the support for it. It includes: 1. Increase the size of IBF/OBF from 64 bytes to 128 bytes. 2. Add IBULVL/IBFLVL2 in SHICFG4/SHICFG5 which can configure at which level the IBF pointer reaches to trigger an interrupt to core. The current setting of these two register fields are: IBFLVL - 64 (half full) IBFLVL2 - 8 (the size of host command protocol V3 header) 3. Dedicated CS high/low interrupts. In old SHI module, the way to generate CS high interrupt event is via EOR bit. However, it has a defect that EOR won't be set to 1 when CS is de-asserted if there is no SHI CLK generated. It makes the handling of glitch condition more complicated. In the new SHI module, we introduce the CS high/low interrupts (by enabling the CSnFEN/CSnREEN) to make it easier to handle the glitch. The new SHI module is enabled during SHI initialization when the chip family is npcx7. BRANCH=none BUG=none TEST=No build errors for "make buildall". Test host command communication is ok between npcx7 EVB and a host emulator. Make sure the glitch condition can be detected and handled. Also test the driver on gru, make sure it won't break the operation of old SHI module. Change-Id: If297fd32a0ec2c9e340c60c8f1942868fa978fbc Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/607812 Commit-Ready: CH Lin <chlin56@nuvoton.com> Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* Revert "npcx: workaround the bug that SHM data read via eSPI may be corrupted"Nicolas Boichat2017-08-161-3/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit ddbfe690e294e595c6ed3511dcf417410d9b2804. Reason for revert: Causes move cursor movements to be choppy, and device to be very unresponsive during flashrom EC operations. Original change's description: > npcx: workaround the bug that SHM data read via eSPI may be corrupted > > In eSPI systems, when the Host performs a data read from the Shared > Memory space, the returned data may be corrupted. This is a result of > the Core-to-Host access enable bit being toggled (by toggling CSAE bit > in SIBCTRL register) during an eSPI transaction. > > The workaround in this CL is to set CSAE bit to 1 during initialization > and remove the toggling of CSAE bit from other EC firmware code. > (i.e., let the CSAE bit be always 1.) > > BRANCH=none > BUG=none > TEST=No build errors for make buildall. Flash poppy ec image, make sure > it can boot to OS. Run "ectool version" over 100000 times, no error > occurs. > > Change-Id: I7aac6805ece64e8f77964d4acb026d9871cd2ebe > Signed-off-by: CHLin <CHLIN56@nuvoton.com> > Reviewed-on: https://chromium-review.googlesource.com/590396 > Commit-Ready: Shawn N <shawnn@chromium.org> > Tested-by: CH Lin <chlin56@nuvoton.com> > Reviewed-by: Shawn N <shawnn@chromium.org> BUG=b:64730183 TEST=flashrom -p ec -r ecr.bin, device still responsive. Change-Id: Idaeef2707df990b2441a77a15807698d41018449 Reviewed-on: https://chromium-review.googlesource.com/618366 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Furquan Shaikh <furquan@chromium.org>
* npcx: system: Remove useless comparisonMartin Roth2017-08-131-1/+1
| | | | | | | | | | | | | | Because x is unsigned it's always greater or equal to zero. BUG=b:64477774 TEST=Build Change-Id: Iaf62be4aecf2738c123cf062099852a192285751 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://chromium-review.googlesource.com/606455 Commit-Ready: Martin Roth <martinroth@chromium.org> Tested-by: Martin Roth <martinroth@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* npcx: espi: Remove useless comparisonMartin Roth2017-08-131-1/+1
| | | | | | | | | | | | | | Because m is unsigned, it can't be less than 0. BUG=b:64477774 TEST=Build Change-Id: Iec93f396be1f01bc1c38b3285b93daacff6a15db Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://chromium-review.googlesource.com/606454 Commit-Ready: Martin Roth <martinroth@chromium.org> Tested-by: Martin Roth <martinroth@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* npcx: espi: Fix errors with unsigned variableMartin Roth2017-08-131-2/+4
| | | | | | | | | | | | | | | | Because sig_idx was declared as uint8_t, if espi_vw_get_signal_index() returned an error value of -1, it wouldn't get caught. This would cause the arrays to access the wrong locations later. BUG=b:64477774 TEST=Build Change-Id: Ibe21d51c00ae3511a66a6976e18495c3f7683a78 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://chromium-review.googlesource.com/606453 Commit-Ready: Martin Roth <martinroth@chromium.org> Tested-by: Martin Roth <martinroth@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* npcx: Define CONFIG_DATA_RAM_SIZEDaisuke Nojiri2017-08-072-10/+10
| | | | | | | | | | | | | | | | | | This patch defines CONFIG_DATA_RAM_SIZE, which indicates the size of the RAM used for data, thus can be marked as non-executable. If it's not defined, it defaults to CONFIG_RAM_SIZE. Thus, other chips are not affected. BUG=b:36037354 BRANCH=none TEST=buildall. Run 'sysjump disable' on Reef and verify mpu_protect_ram is successful. Change-Id: I54d74fd1dabff7e1013fff2542fd02c3646803d1 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/596518 Reviewed-by: Aaron Durbin <adurbin@chromium.org>
* npcx: workaround the bug that SHM data read via eSPI may be corruptedCHLin2017-07-311-12/+3
| | | | | | | | | | | | | | | | | | | | | | | | In eSPI systems, when the Host performs a data read from the Shared Memory space, the returned data may be corrupted. This is a result of the Core-to-Host access enable bit being toggled (by toggling CSAE bit in SIBCTRL register) during an eSPI transaction. The workaround in this CL is to set CSAE bit to 1 during initialization and remove the toggling of CSAE bit from other EC firmware code. (i.e., let the CSAE bit be always 1.) BRANCH=none BUG=none TEST=No build errors for make buildall. Flash poppy ec image, make sure it can boot to OS. Run "ectool version" over 100000 times, no error occurs. Change-Id: I7aac6805ece64e8f77964d4acb026d9871cd2ebe Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/590396 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* npcx: Drop unused cmd_params from lpc.cStefan Reinauer2017-07-281-2/+0
| | | | | | | | | | | | | | | cmd_params is static, const and unused. Drop it. BUG=none BRANCH=none TEST=USE=coreboot-sdk emerge-fizz chromeos-ec succeeds. Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Change-Id: I62444d81affde9e3e0d4da1d1ee2d5d51a337bb6 Reviewed-on: https://chromium-review.googlesource.com/590676 Commit-Ready: Stefan Reinauer <reinauer@google.com> Tested-by: Stefan Reinauer <reinauer@google.com> Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
* npcx: gpio: Optimize gpio_interrupt_type_sel() for code space reductionShawn Nematbakhsh2017-07-271-19/+11
| | | | | | | | | | | | | | | | gpio_interrupt_type_sel() is guaranteed to be called with at least one GPIO_INT_ANY bit set, but our new toolchain doesn't seem to realize it. BUG=chromium:747553 BRANCH=None TEST=`make BOARD=gru -j` with next_gcc, also verify kevin boots to OS. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Ice2a9963983dca2ee9c0c543bf55c27753c42933 Reviewed-on: https://chromium-review.googlesource.com/584820 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* npcx: gpio: Clear GPIO interrupt if no ISR is availableShawn Nematbakhsh2017-07-251-0/+4
| | | | | | | | | | | | | | | | | | | If we have no ISR for an enabled GPIO interrupt (eg. for a UART GPIO interrupt that wakes from low-power idle) then clear it, to avoid interrupt storm. BUG=b:63958831 BRANCH=eve TEST=Verify we can repeatedly wake from low-power idle on eve by hitting 'enter' on the EC console. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I6a01cae33e3bf1a3b5b42c0389c4613dc1cb9b7d Reviewed-on: https://chromium-review.googlesource.com/584011 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@google.com> Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
* npcx: Add support for chip variant npcx7m6gCHLin2017-07-162-3/+3
| | | | | | | | | | | | | | | | | | | | | This CL adds CHIP_VARIANT_NPCX7M6G to support another npcx7 ec SKU. Please note that the default setting in npcx7_evb is npcx7m6f. For the EVB using the 128-pins EC package, please change CHIP_VARIANT from npcx7m6f to npcx7m6g in build.mk. BRANCH=none BUG=none TEST=No build errors for make buildall; Set CHIP_VARIANT=npcx7m6g in board/npcx7_evb/build.mk; Build the image and test on EVB. Change-Id: I2f857e4f6524eab45930bac3cc209409d4a53ee8 Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/569320 Commit-Ready: Jun Lin <riverq@gmail.com> Tested-by: Jun Lin <riverq@gmail.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
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