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* npcx: Adjust relative IRQ priorities for high-priority UARTShawn Nematbakhsh2016-08-079-33/+29
| | | | | | | | | | | | | | | | | | | Our UART interrupt must be able to preempt our SHI_CS interrupt, otherwise console input may be lost. Adjust our relative IRQ priorities to accommodate this. BUG=chrome-os-partner:55920 BRANCH=None TEST=Run `echo "kbpress 11 4 1" > /dev/pts/17` on kevin 200 times from the recovery screen, verify that all input is received by the EC. Change-Id: I36203511f5883272287ac22d0704098fbd933758 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/366622 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
* Revert "shi: Enable SHI interrupt from CS interrupt"Shawn Nematbakhsh2016-08-051-27/+20
| | | | | | | | | | | | | | | This reverts commit 25f19f5bbd1f557d73c64079de9cd242b8e1f6ed, which was causing host command issues after sysjump. IBUFSTAT seems to behave strangely. Additional investigation is required. BUG=chrome-os-partner:55710,chrome-os-partner:55795 BRANCH=None TEST=Verify host commands continue to work after sysjump. Change-Id: Id94a9c4677bcae597b9353e081418e649e823564 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/366173 Reviewed-by: Randall Spangler <rspangler@chromium.org>
* shi: Enable SHI interrupt from CS interruptShawn Nematbakhsh2016-08-021-20/+27
| | | | | | | | | | | | | | | | | | | | | | | Enable the SHI interrupt only after we have received and begun processing our host command. Disable the SHI interrupt once our transaction is complete (with either success or error status). This will prevent the SHI interrupt from being asserted at the same time as the CS interrupt, which can lead to the SHI interrupt being serviced first. Also, it avoids needless, non-useful SHI interrupts during error transactions. BUG=chrome-os-partner:55710,chrome-os-partner:55795 BRANCH=None TEST=Manual on gru. Stress test flashrom w/ unpowered Donette attached (for host command spam), verify no errors encountered after 100 minutes. Change-Id: I0ab20b0202ebcfe15c04b272ec67001a6a358dad Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/364698 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
* npcx: shi: Improve host command handling reliabilityShawn Nematbakhsh2016-07-291-11/+3
| | | | | | | | | | | | | | | | | | | | - Pass-thru to IBF handler code in case both IBHF and IBF interrupts are pending, in order to properly keep track our Tx byte count. - Don't disable the SHI IRQ in our host command handler callback since system-wide interrupts are already disabled. BUG=chrome-os-partner:55711,chrome-os-partner:55721 BRANCH=None TEST=Manual on gru with subsequent commit. Verify `flashrom -p ec -r file.bin` passes 100x with no errors or warnings. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I6225ffde1fe0127c7484933fe4a151d22f42415c Reviewed-on: https://chromium-review.googlesource.com/364234 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
* npcx: Consecutively sample IBUFSTAT until reading the same value twiceCHLin2016-07-291-6/+24
| | | | | | | | | | | | | | | | | | | | | | It has rare chance for FW to get a unexpected value when reading IBUFSTAT. This is because the clock source of SHI and CPU are asynchronous. The reading value is invalid if IBUFSTAT is during transition state. Use two consecutive equal reading can make sure the value is valid. BUG=chrome-os-partner:34346 TEST=run "while true; do ectool version; done" on gru, verify each failure happens about 50000 host commands BRANCH=none Change-Id: Ie246561d201dd87d89cb2424c23d016dcdcd47c9 Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/362734 Commit-Ready: Randall Spangler <rspangler@chromium.org> Tested-by: CH Lin <chlin56@nuvoton.com> Tested-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
* kevin / gru: Increase size of code RAMShawn Nematbakhsh2016-07-261-1/+1
| | | | | | | | | | | | | | | | Reduce size of UART Tx buffer to 1024 bytes on all npcx platforms and increase size of code memory by 6K bytes on Kevin. BUG=chrome-os-partner:52876 BRANCH=None TEST=`make buildall -j` with subsequent commit. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Ib9e52a4406f84cfc434984f8819d7ef02b70beb4 Reviewed-on: https://chromium-review.googlesource.com/363591 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* chip/npcx: interrupt on both edges of PLTRST_LAaron Durbin2016-07-211-8/+12
| | | | | | | | | | | | | | | | | | | | | | Different actions need to be taken on PLTRST_L depending on if it is asserted or deasserted. The vstore module needs to reset its locks when PLTRST_L is asserted (host is in reset). The interrupt was previously on occurring on a deassertion of PLTRST_L (rising edge). That's not conducive for handling actions which are required for assertion (falling edge). Lastly, fix the CONFIG_CHIPSET_RESET_HOOK logic to be called when PLTRST_L is asserted. BUG=chrome-os-partner:55471 BRANCH=None TEST=Able to boot and reboot without getting vboot hash saving errors. Also am able to see the assertion/deassertion messages on the console. Change-Id: I70eac3309a5876de775ec5c34dab2e9aa8bbb42c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/362000 Reviewed-by: Shawn N <shawnn@chromium.org>
* npcx: shi: Properly mux pins as GPIO when disabling SHIShawn Nematbakhsh2016-07-211-7/+12
| | | | | | | | | | | | | | | | | | | | | MODULE_SHI is used for the SPI master interface pins, so don't reconfigure those. Instead manually configure the SHI pins using the appropriate DEVALT bit. BUG=chrome-os-partner:54328 BRANCH=None TEST=Manual on kevin. Verify SHI continues to function on cold boot, sysjump and resume from S3. Verify SPI sensors now function on resume from S3 - `accelinit 0` succeeds. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I63f028968f3d0dbc9d7ca7dacc70c9c399f7a180 Reviewed-on: https://chromium-review.googlesource.com/362061 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Caesar Wang <wxt@rock-chips.com> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
* Fix interrupt disabling problem for gpio volume button.younghun kim2016-07-201-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | Remove "task_disable_irq()" function call in EC_RTC_ALARM_CLEAR case. Host command "RTC_SET_ALARM" with 0 second does not disable volume key interrupt. BUG=chrome-os-partner:55401 BRANCH=none TEST=check EC UART log message. If you press volume up/down button - Before HC 0x47 (RTC_SET_ALARM Command with 0 second) Log : Button 'Volume Up/Down' was released. - After HC0x47 Log : Button 'Volume Up/Down' was released. GPIO volume key is still enable. Change-Id: I8d8a4fa4927046b76a49ac4833b6a710db2e05be Signed-off-by: younghun kim <young-h.kim@samsung.com> Reviewed-on: https://chromium-review.googlesource.com/361670 Commit-Ready: Wonjoon Lee <woojoo.lee@samsung.com> Tested-by: Younghun Kim <young-h.kim@samsung.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* npcx: Clear IRQ11B bit when PM 1 is in enhanced modeCHLin2016-07-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | The bit IRQ11B of register HIIRQC is meaningful only when PM Channel 1 is in PC87570-Compatible. In previous commit, we deprecate use of PC87570 mode but set the bit unintentionally. This will not cause any bug but may make confused when reading the code. Modified sources: 1. lpc.c: CLear IRQ11B in register HIIRQC. BUG=chrome-os-partner:34346 TEST=make buildall -j; verify on Wheatley BRANCH=none Signed-off-by: CHLin <CHLIN56@nuvoton.com> Change-Id: I594222c29557add847a1f689859fdf558d64fdd3 Reviewed-on: https://chromium-review.googlesource.com/358536 Commit-Ready: CH Lin <chlin56@nuvoton.com> Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-by: Amit Maoz <Amit.Maoz@nuvoton.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* common: add EC_RTC_ALARM_CLEAR to ec_commands.hStephen Barber2016-07-091-1/+0
| | | | | | | | | | | | | | | | | | | EC_RTC_ALARM_CLEAR should live in ec_commands.h so other EC clients such as the kernel can make use of it. Signed-off-by: Stephen Barber <smbarber@chromium.org> BRANCH=none BUG=chrome-os-partner:52219 TEST=kernel can clear existing alarm Change-Id: I88aefed7e6c37a5aa2e4306c078e90d671c410d0 Reviewed-on: https://chromium-review.googlesource.com/359352 Commit-Ready: Stephen Barber <smbarber@chromium.org> Tested-by: Stephen Barber <smbarber@chromium.org> Reviewed-by: Stephen Barber <smbarber@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* npcx: deprecate use of PC87570 mode on PM chan 1stabilize-8530.Bstabilize-8530.96.Bstabilize-8530.93.Bstabilize-8530.89.Bstabilize-8530.80.Bstabilize-8530.77.Bstabilize-8530.71.Bstabilize-8530.35.Brelease-R53-8530.BCHLin2016-06-301-5/+9
| | | | | | | | | | | | | | | | | | | In NPCX5m5g/NPCX5m6g, PM channel 1 can support both PC87570-Compatible and enhcnced mode. In next generation of chip, only enhanced mode will be supported. Set the enhanced mode as default in the firmware to support all gereration of chips. BUG=chrome-os-partner:34346 TEST=make buildall -j; verify on Wheatley BRANCH=none Change-Id: Ide9e17a1fe8a0d2bfdc33efe2336a10702660679 Signed-off-by: CHLin <CHLIN56@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/357752 Commit-Ready: CH Lin <chlin56@nuvoton.com> Tested-by: CH Lin <chlin56@nuvoton.com> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
* npcx: shi: Use worst-case logic for applying 256B bypassShawn Nematbakhsh2016-06-291-3/+3
| | | | | | | | | | | | | | | | | | | | SHI_OBUF_VALID_OFFSET may wrap on buffer full, leaving us with an incorrect tally of bytes transmitted. Always assume the worst case, that SHI_OBUF_VALID_OFFSET is at maximum, when deciding to apply 256B bypass. BUG=chrome-os-partner:54566 BRANCH=None TEST=Manual on gru. Verify 'flashrom -p ec -r read.bin' does not produce CRC errors. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I7c0ccc1b555838854584a3be8ced50057eaea961 Reviewed-on: https://chromium-review.googlesource.com/356771 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shelley Chen <shchen@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
* Cleanup: gate RTC console/host command behind new config optionsphilipchen2016-06-292-1/+6
| | | | | | | | | | | | | | | | Put RTC code supporting console/host command behind new flags 'CONFIG_CMD_RTC'/'CONFIG_HOSTCMD_RTC' BUG=chromium:613699 TEST=make buildall BRANCH=master Change-Id: Ida52265d124978f48bd6ca522be3badee9f99588 Reviewed-on: https://chromium-review.googlesource.com/356206 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* npcx: shi: Avoid 'unexpected state' console spamShawn Nematbakhsh2016-06-281-5/+21
| | | | | | | | | | | | | | | | | | | If SHI finds itself in an unexpected state, we may try to print an error message for each IBF / IBHF interrupt, which is excessively spammy and may even lead to EC watchdog. Avoid console spam by not duplicating IBF / IBHF / IBEOR error prints, if our state doesn't change. BUG=chrome-os-partner:54502 BRANCH=None TEST=Manual on gru. Verify only one print is seen when SHI fails due to missed initialization. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I331c64c24fa3a68d7c17e052240691076d3532cc Reviewed-on: https://chromium-review.googlesource.com/356239 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* npcx: shi: Ensure SHI is initialized prior to enabling CS interruptShawn Nematbakhsh2016-06-281-8/+14
| | | | | | | | | | | | | | | | | | | shi_init() must be called before shi_enable(). BUG=chrome-os-partner:54810 BRANCH=None TEST=Manual on gru. Power-up EC, verify no SHI error prints are encountered. Boot to OS, run "sysjump rw", verify that host commands continue to be handled correctly. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I6ff0db87115f5b1f358d7d98e7b7050ee3e3fe0a Reviewed-on: https://chromium-review.googlesource.com/356178 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Douglas Anderson <dianders@chromium.org> Tested-by: Vadim Bendebury <vbendeb@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* npcx: i2c: Don't do i2c_unwedge / reset on repeated start requeststabilize-8516.BMulin Chao2016-06-271-2/+5
| | | | | | | | | | | | | | | | | | Checking for bus busy (stop condition sent) should not apply if the caller is requesting a repeated start. BUG=None TEST=Manual on gru. Attach USB PD charger, verify i2c_unwedge is not called. BRANCH=None Change-Id: Idf13bdc530920c8da02c8d0d8064377513a5d144 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/356490 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* rk3399: kevin: Adding get_rtc_alarm functionality.Shelley Chen2016-06-211-2/+41
| | | | | | | | | | | | | | | | | | | | | | Adding ability to get # seconds before rtc alarm goes off. BUG=chrome-os-partner:52218 BRANCH=None TEST=ectool rtcgetalarm w/o setting returns Alarm not set. ectool rtcsetalarm 30; ectool rtcgetalarm to make sure counting down to 0. After alarm goes off, rtcgetalarm should return alarm not set again. rtcsetalarm 30; rtcgetalarm to check alarm is set. rtcsetalarm 0; should disable alarm. Use rtcgetalarm to ensure that alarm is disabled. Change-Id: I176b12fe2dda08eedd23ea33dc64785f09f1d9ae Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/353331 Reviewed-by: Shawn N <shawnn@chromium.org>
* npcx: vbnvcontext: Fix misaligned accessShawn Nematbakhsh2016-06-201-11/+18
| | | | | | | | | | | | | | | | | | | | We have no guarantee about the alignment of our input buffer so don't use 32-bit access. BUG=chrome-os-partner:54561 BRANCH=None TEST=Manual on gru. Enable CHROMEOS_VBNV_EC, verify exception isn't encountered on host command 0x17. Also verify call to system_set_vbnvcontext followed by system_get_vbnvcontext results in same data being read back. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I4df636b70c71a43a2dd6f584ee965135e90b4351 Reviewed-on: https://chromium-review.googlesource.com/354132 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* npcx: Fixed host access pending bit issue in INT11 ISR.Mulin Chao2016-06-141-10/+10
| | | | | | | | | | | | | | | | | | | | Since the pending bit of host access interrupt is set frequently if PCH accesses KBC/PM_Channel/Shared Memory through LPC after entering S0. It's better to add checking enable bit of MIWU of it in case huge latency between gpio interrupt and serving its own ISR in INT11's ISR. Modified sources: 1. gpio.c: Add checking enable bit of MIWU of host access in INT11 ISR. BRANCH=none BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers Change-Id: I1ae57173eb208fa78218bc01cfbc91f9a29c5c81 Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/352362 Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* npcx: i2c: Return slave ACK status on zero-byte read / writeShawn Nematbakhsh2016-06-081-38/+52
| | | | | | | | | | | | | | | | | | | | The `i2cdetect` tool will scan certain slave addresses with a zero byte read / write. Reply to such requests with the ACK status of the slave device. BUG=chrome-os-partner:53324 BRANCH=None TEST=Verify `i2cdetect -y -a 9` on kevin yields the ACK status of each slave address. Change-Id: If080cc9f1b7dfefb0025fef448c5b177a2a50137 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/350102 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Mulin Chao <mlchao@nuvoton.com> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
* npcx: gpio: Don't increase priority of SHI_CS for non-SHI boardsShawn Nematbakhsh2016-06-081-0/+4
| | | | | | | | | | | | | | | | Systems that don't use SHI don't need elevated SHI_CS interrupt priority. BUG=None TEST=`make buildall -j` BRANCH=None Change-Id: Ica6e82332bc7ef8f92c00d847cd3ff0df7ede429 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/350570 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* kevin: rk3399: ectool interface for EC RTC alarmShelley Chen2016-05-271-0/+11
| | | | | | | | | | | | | | | | | | Only way to set alarm previously was through rtcalarm command on EC console. Implemented interface through ectool so that the AP can set it as well. BUG=chrome-os-partner:52218 BRANCH=None TEST=from AP console, run ectool rtcalarm <sec> Should see [event set 0x02000000] from EC console in approximately <sec> seconds. Change-Id: I3202b826cb994dbca456b8b9c22bbca4dbe2766a Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/347493 Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
* servo_v4: Fix ADC console commandNick Sanders2016-05-261-19/+0
| | | | | | | | | | | | | | | | | | | | | | The console adc command prints adc values in the order they appear in hardware, however they are lableled in the order they are enumerated in board.h, which is not necessarily the same. This prints the correct name and value pairs, and removes the adc_read_all_channels function which is not otherwise used. BUG=chromium:571476 BRANCH=None TEST="adc" command associates correct values with names now. Change-Id: I688641953d20082224b4120eaefe0d634ad4c74c Signed-off-by: Nick Sanders <nsanders@google.com> Reviewed-on: https://chromium-review.googlesource.com/340892 Commit-Ready: Nick Sanders <nsanders@chromium.org> Tested-by: Nick Sanders <nsanders@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* kevin: rk3399: enabling RTC wakeupShelley Chen2016-05-231-1/+14
| | | | | | | | | | | | | | | | | | Enabled CONFIG_CMD_RTC_ALARM. EC_HOST_EVENT_RTC is enabled when the rtc_alarm goes off, alerting the AP to transition from S3->S0. BUG=chrome-os-partner:52218 BRANCH=None TEST=rtc_alarm <num> and see event set in ec console after <num> seconds. Also, check if new bit set through hostevent command in ec before/after rtc_alarm goes off. Change-Id: I53b1705ce0925000f35b9f80752035d198db3310 Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/345474 Reviewed-by: Shawn N <shawnn@chromium.org>
* npcx: Modify gpio's interrupt utilitiesMulin Chao2016-05-181-22/+14
| | | | | | | | | | | | | | | | | | | | | | Setting NVIC_EN register is not a suitable method if you want to turn on/off one GPIO's interrupt. Since there're eight sources belong to the same interrupt, using MIWU_EN register which bit belongs to one MIWU's source is a better way. Modified sources: 1. gpio.c: Replace accessing NVIC_EN register with MIWU_EN in gpio's interrupt utilities. BRANCH=none BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers Change-Id: I282a45f5a3ab7cb032b2282cf7e92cacc5e706b6 Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/342122 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Bill Richardson <wfrichar@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* shorten long console command namesVadim Bendebury2016-05-181-1/+1
| | | | | | | | | | | | | | | | | | | The EC code expects console commands to be no longer than 14 characters, otherwise the alignment of the help command output breaks. This patch replaces flash_spi_sel_lock with flash_spi_lock and fake_disconnect with fakedisconnect to make sure the command names fit. BRANCH=none BUG=none TEST=the 'help' command output is not misaligned any more Change-Id: Ia65f1535850a07adccbef0812c8a0922c0264cea Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/345570 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
* npcx: i2c: Fix spurious NACK after i2cscanMulin Chao2016-05-171-4/+28
| | | | | | | | | | | | | | | | | | | | | | | The NPCX_SMBCTL1_ACK bit (which tells the I2C master to produce a NACK rather than ACK) can be set but not cleared by SW -- it can only be cleared automatically after actually generating a NACK. During i2cscan, we want to NACK the first byte returned, but we won't actually produce a NACK unless the slave ACKs our scanned address. Therefore, we must wait until the slave ACKs its address before setting NPCX_SMBCTL1_ACK -- use the NPCX_SMBCTL1_STASTRE / stall interrupt to do so. BUG=chrome-os-partner:53323 BRANCH=None TEST=Manual on kevin. Verify faulty temperature sensor reads are not seen after `i2cscan` and verify i2c otherwise functions normally. Change-Id: I080d8804adb246129aaebbfbf5ad862e9513da3b Signed-off-by: Shawn Nematbakhsh <shawnn@chromioum.org> Reviewed-on: https://chromium-review.googlesource.com/344818 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* npcx: shi: Allow up to 10ms from CS assertion to first data byteShawn Nematbakhsh2016-05-121-1/+1
| | | | | | | | | | | | | | | | | | | Performance in our baseline 4.4 kernel is much worse than previous test kernels and CS-to-first-byte delay is frequently > 500us. Allow up to 10ms to receive a data byte after CS to reduce the possibility of failed host commands. BUG=chrome-os-partner:53181 TEST=Manual on kevin w/ chromeos-kernel-4_4. Verify that "ERR-GTH" rate is much reduced while spamming "ectool version". BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I92880ccf83a77ee9bdd3d85813e341105857ca4c Reviewed-on: https://chromium-review.googlesource.com/344410 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* npcx: Fixed bug that unexpected value of timer which source clock is 32KMulin Chao2016-05-113-5/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In rare case, FW read the unexpected counter value of timer which source clock is 32K (Watchdog timer and ITIM16/32 which use 32K source clock). The root cause is the clocks between reading registers and timer's are asynchronous. It has a chance to get invalid counter value when timer is under transaction edge. The solution is using two consecutive equal readings to make sure the counter value is valid. Beside different source clocks of timer, we also found there's chip's bug which causes unexpected value of timer. If an interrupt that occurs very shortly before entering deep idle with instant wakeup, it might result in disruptive execution (such as skipping some instructions or hard fault) after "wfi". The workaround is adding the same bypass for idle in deep idle section. Modified sources: 1. clock.c: Add bypass for instant wakeup from deep sleep. 2. hwtimer.c: Add consecutive reading function for event timer. 3. watchdog.c: Add consecutive reading function for watchdog timer. BUG=chrome-os-partner:34346 TEST=make buildall -j; test nuvoton IC specific drivers BRANCH=none Change-Id: I7c9f1fb9618a3c29826d8f4599864a8dac4203bf Signed-off-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-on: https://chromium-review.googlesource.com/327356 Reviewed-by: Shawn N <shawnn@chromium.org>
* npcx: shi: Fixes for REBOOT_EC host command handlingShawn Nematbakhsh2016-05-101-11/+11
| | | | | | | | | | | | | | | | | | | | | | | - For REBOOT_EC and several other host commands, send_response may be called multiple times (once for early success notification, one for actual notification, if the handler exits cleanly). Ignore calls after the first. - During reboot / sysjump, we're not equipped to handle host commands, so disable the SHI interface altogether. BUG=chrome-os-partner:52878 TEST=Manual on kevin. Verify "ectool reboot_ec RO" (RO to RO = NOP) succeeds without error messages on EC console. Verify "ectool reboot_ec RW" causes sysjump without AP going down. BRANCH=None Change-Id: Iae83084e4f8d5218600be2a9da7f71dd7872d569 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/342622 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* kevin: Move RAM from data section to codeShawn Nematbakhsh2016-05-102-3/+3
| | | | | | | | | | | | | | | | | | Kevin is code space constrained, so use RAM normally used for data instead for code. BUG=chrome-os-partner:52876 BRANCH=None TEST=Verify free code RAM becomes 5732 bytes (was 1636) and free data RAM becomes 3072 bytes (was 7168 bytes) (measured with pending changes to add sensor task). Also, verify kevin continues to boot + power sequence. Change-Id: Ia6470a76f95e87d6cda1bf7273deaab6344f8ee9 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/343191 Commit-Ready: Wonjoon Lee <woojoo.lee@samsung.com> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* npcx: shi: Improve reliability of SPI host command interfaceMulin Chao2016-05-062-126/+241
| | | | | | | | | | | | | | | | | | | | | - Fix output buffer filling races - Limit response size to 256 bytes to work-around forced low bit on 257th byte - Modify CS glitch to handle CS-to-clock delay - Make CS GPIO interrupt pri 0 to ensure SHI interrupts aren't serviced first TEST=`while true; do ectool version; done > /usr/local/log` on kevin, verify failure occurs about every ~72000 commands (~360000 host commands) BRANCH=None BUG=chrome-os-partner:52372 Change-Id: I5c3d90bf510ed782973b57c2b7497441434c1708 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/341492 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* npcx: spi: disable all port from board structWonjoon Lee2016-05-061-3/+5
| | | | | | | | | | | | | | We have two port(as is FALSH_, ACCEL_) on SPI defines Let's prevent build error so that We can use particular enable/disable port BUG=None TEST=Buildall is OK Change-Id: Ib6fe14c4edd91947bde0a2da1c889da31db291a4 Signed-off-by: Wonjoon Lee <woojoo.lee@samsung.com> Reviewed-on: https://chromium-review.googlesource.com/341576 Reviewed-by: Shawn N <shawnn@chromium.org>
* hooks: Add relative HOOK_INIT priority for peripheralsShawn Nematbakhsh2016-05-053-3/+3
| | | | | | | | | | | | | | | | | | | Using HOOK_PRIO_DEFAULT for peripheral initialization necessitates using HOOK_PRIO_DEFAULT+1 for board-level code. Instead, use a higher-than-default relative priority for peripheral initialization outside of board. BUG=None TEST=Verify PWM and ADC are functional on kevin. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Ia8e90a7a866bdb0a661099dd458e3dfcaaa3f6bb Reviewed-on: https://chromium-review.googlesource.com/342171 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* npcx: add device id for npcx586g/npcx576gKevin K Wong2016-05-041-0/+4
| | | | | | | | | | | | BUG=none BRANCH=none TEST=version command shows the correct chip device id Change-Id: I312b343f97a99b3ff5ae7d6ec3606cff291b2b55 Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-on: https://chromium-review.googlesource.com/342130 Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
* apollolake: ignore PLTRST# from SOC unless RSMRST# is deassertedKevin K Wong2016-05-031-4/+3
| | | | | | | | | | | | | add optional chipset specific function to check if PLTRST# is valid BUG=chrome-os-partner:52656 BRANCH=none TEST=make buildall, able to boot to OS on amenia Change-Id: I7a2747c4f77f50393c3250c2ab0e1625e64e5a41 Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-on: https://chromium-review.googlesource.com/341732 Reviewed-by: Shawn N <shawnn@chromium.org>
* npcx: Reduce system stack sizeShawn Nematbakhsh2016-05-021-1/+1
| | | | | | | | | | | | | | | | Reduce system stack size to 1K to match other recent chips. BUG=None TEST=Build + boot on kevin. BRANCH=None Change-Id: I0be6e865ca03f4eef2ee7a99856df8257d7269d9 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/341850 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
* pwm: Add PWM_CONFIG_DSLEEP config flagShawn Nematbakhsh2016-04-272-11/+7
| | | | | | | | | | | | | | | | | | | Add PWM_CONFIG_DSLEEP PWM config flag, which can be set to keep a channel active during low-power idle / deep sleep. Currently it's supported by npcx and mec1322. BUG=chrome-os-partner:52783 BRANCH=glados TEST=Manual on chell w/ subsequent commit + CONFIG_LOW_POWER_S0. Verify KB backlight does not flicker during idle. Change-Id: Ib9df5879aaa7dfa5764de1583496de84d40d2bb5 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/341002 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Todd Broch <tbroch@chromium.org>
* UART: Remove enable/disable interrupt functionsAnton Staaf2016-04-271-10/+0
| | | | | | | | | | | | | | | | These were not being used and complicate changes to the UART API. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Change-Id: I73e256f09f7ea72f0cc4831cc7ce391a7125e555 Reviewed-on: https://chromium-review.googlesource.com/340841 Commit-Ready: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* npcx: shi: Remove excessively verbose printsShawn Nematbakhsh2016-04-192-14/+18
| | | | | | | | | | | | | | | | | Remove verbose prints (most of which are printed in ISRs) by default to eliminate SHI console spam. BUG=chrome-os-partner:52372 BRANCH=None TEST=Verify console isn't spammy while SHI is in use on kevin. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I0dbd43e01f37980bc0e9d14fa6349a7ecb8c6f47 Reviewed-on: https://chromium-review.googlesource.com/339493 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
* npcx: shi: Remove support for V2 host protocolShawn Nematbakhsh2016-04-191-168/+4
| | | | | | | | | | | | | BUG=chrome-os-partner:52372 BRANCH=None TEST=Verify V3 host command interface is still functional. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: I75e684f3fbce764965ddac47b8314ed298086d74 Reviewed-on: https://chromium-review.googlesource.com/339472 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* npcx: shi: Don't enable GPIO_SHI_CS_L GPIO interrupt until S0Shawn Nematbakhsh2016-04-191-5/+26
| | | | | | | | | | | | | | | | | | Prior to going to S0, GPIO_SHI_CS_L may be low, which can cause glitches in the SHI HW unit. Enable the GPIO interrupt in S0, and disable it when leaving S0. BUG=chrome-os-partner:52222,chrome-os-partner:52217 BRANCH=None TEST=Manual on kevin. Verify 'ectool version' succeeds with subsequent kernel / ectool patches. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Ie3494122c2486429d3f648ab9220daf5dd34f812 Reviewed-on: https://chromium-review.googlesource.com/338857 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Mary Ruthven <mruthven@chromium.org>
* Deferred: Remove hard coded number of deferredsAnton Staaf2016-04-191-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | Previously the maximum number of deferred routines was specified by the the default maximum number of deferred routines you had to override this, and if you wanted fewer, you still payed the price of having the defer_until array statically allocated to be the maximum size. This change removes that define and instead creates the RAM state of the deferred routine (the time to wait until to call the deferred) when the deferred is declared. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j manually test on discovery-stm32f072 Change-Id: Id3db84ee1795226b7818c57f68c1f637567831dc Reviewed-on: https://chromium-review.googlesource.com/335597 Commit-Ready: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* Deferred: Use deferred_data instead of function pointerAnton Staaf2016-04-181-1/+1
| | | | | | | | | | | | | | | | | | | | | Previously calls to hook_call_deferred were passed the function to call, which was then looked up in the .rodata.deferred section with a linear search. This linear search can be replaced with a subtract by passing the pointer to the deferred_data object created when DECLARE_DEFERRED was invoked. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None CQ-DEPEND=CL:*255812 TEST=make buildall -j Change-Id: I951dd1541302875b102dd086154cf05591694440 Reviewed-on: https://chromium-review.googlesource.com/334315 Commit-Ready: Bill Richardson <wfrichar@chromium.org> Tested-by: Bill Richardson <wfrichar@chromium.org> Reviewed-by: Bill Richardson <wfrichar@chromium.org>
* amenia: enable BMM150 compassKevin K Wong2016-04-151-0/+1
| | | | | | | | | | | BUG=none BRANCH=none TEST=accelinfo return data from compass Change-Id: Ib64ca8a06071744294c0bc88bbb18f1445d71780 Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-on: https://chromium-review.googlesource.com/331656 Reviewed-by: Shawn N <shawnn@chromium.org>
* apollolake: ignore PLTRST# from SOC unless RSMRST# to soc is deassertedKevin K Wong2016-04-131-0/+8
| | | | | | | | | | | | | | | signals output from SOC should be considered invalid until EC has de-asserted RSMRST# to SOC. BUG=none BRANCH=none TEST=make buildall, able to boot to OS on amenia Change-Id: I15aee314263e3f1b41c45fb719249cd2579a6bc7 Signed-off-by: Kevin K Wong <kevin.k.wong@intel.com> Reviewed-on: https://chromium-review.googlesource.com/331654 Reviewed-by: Li1 Feng <li1.feng@intel.com> Reviewed-by: Shawn N <shawnn@chromium.org>
* npcx: gpio: Configure pin attributes before setting as outputShawn Nematbakhsh2016-03-291-8/+10
| | | | | | | | | | | | | | | | | | | | When a pin power-on default is input, it is necessary to configure output level, pull up, etc. before setting the pin to output. Otherwise, the pin may be set to an undesired logic level for a short time. BUG=chrome-os-partner:51722 TEST=Power-up kevin, verify that CR50_RESET_L (default input, configured as high + open drain output by default) does not go low for a short period at boot. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Ieaa08e14e6ea15a908f3ff4ee9188e14b17583cf Reviewed-on: https://chromium-review.googlesource.com/335344 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
* npcx: pwm: Fix PWM moduleShawn Nematbakhsh2016-03-282-5/+8
| | | | | | | | | | | | | | | | | - Fix incorrect use of pwm functions which take a channel number. - Set power-down register according to PWMs that are actually enabled. BUG=chrome-os-partner:51722 TEST=Run 'pwm 1 50` on kevin and verify that LED lights up. BRANCH=None Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: If7bcc812b55d3b72f215cf41c264d34827db7e29 Reviewed-on: https://chromium-review.googlesource.com/335372 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Mulin Chao <mlchao@nuvoton.com>
* GPIO: Rename and move board_set_gpio_hibernate_stateAnton Staaf2016-03-211-4/+7
| | | | | | | | | | | | | | | | | This function is no longer GPIO specific and fits better as part of the system API, so this moves it there and renames it board_hibernate_late. Signed-off-by: Anton Staaf <robotboy@chromium.org> BRANCH=None BUG=None TEST=make buildall -j Change-Id: I39d3ecedadaaa22142cc82c79f5d25c891f3f38c Reviewed-on: https://chromium-review.googlesource.com/330124 Commit-Ready: Anton Staaf <robotboy@chromium.org> Tested-by: Anton Staaf <robotboy@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
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