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* ish: Trim down the release branchstabilize-wristpin-14469.59.B-ishstabilize-voshyr-14637.B-ishstabilize-quickfix-14695.187.B-ishstabilize-quickfix-14695.124.B-ishstabilize-quickfix-14526.91.B-ishstabilize-14695.85.B-ishstabilize-14695.107.B-ishstabilize-14682.B-ishstabilize-14633.B-ishstabilize-14616.B-ishstabilize-14589.B-ishstabilize-14588.98.B-ishstabilize-14588.14.B-ishstabilize-14588.123.B-ishstabilize-14536.B-ishstabilize-14532.B-ishstabilize-14528.B-ishstabilize-14526.89.B-ishstabilize-14526.84.B-ishstabilize-14526.73.B-ishstabilize-14526.67.B-ishstabilize-14526.57.B-ishstabilize-14498.B-ishstabilize-14496.B-ishstabilize-14477.B-ishstabilize-14469.9.B-ishstabilize-14469.8.B-ishstabilize-14469.58.B-ishstabilize-14469.41.B-ishstabilize-14442.B-ishstabilize-14438.B-ishstabilize-14411.B-ishstabilize-14396.B-ishstabilize-14395.B-ishstabilize-14388.62.B-ishstabilize-14388.61.B-ishstabilize-14388.52.B-ishstabilize-14385.B-ishstabilize-14345.B-ishstabilize-14336.B-ishstabilize-14333.B-ishrelease-R99-14469.B-ishrelease-R98-14388.B-ishrelease-R102-14695.B-ishrelease-R101-14588.B-ishrelease-R100-14526.B-ishfirmware-cherry-14454.B-ishfirmware-brya-14505.B-ishfirmware-brya-14505.71.B-ishfactory-kukui-14374.B-ishfactory-guybrush-14600.B-ishfactory-cherry-14455.B-ishfactory-brya-14517.B-ishJack Rosenthal2021-11-051-503/+0
| | | | | | | | | | | | | | | | | | | | | | In the interest of making long-term branch maintenance incur as little technical debt on us as possible, we should not maintain any files on the branch we are not actually using. This has the added effect of making it extremely clear when merging CLs from the main branch when changes have the possibility to affect us. The follow-on CL adds a convenience script to actually pull updates from the main branch and generate a CL for the update. BUG=b:204206272 BRANCH=ish TEST=make BOARD=arcada_ish && make BOARD=drallion_ish Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Change-Id: I17e4694c38219b5a0823e0a3e55a28d1348f4b18 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3262038 Reviewed-by: Jett Rink <jettrink@chromium.org> Reviewed-by: Tom Hughes <tomhughes@chromium.org>
* chip/stm32: Factor family specific clock logic out of usb.cJes B. Klinke2021-09-081-0/+14
| | | | | | | | | | | | | | | | | | | | | | | The register for enabling USB register clock appears to have been identical across F0, F3, and G4 families, but for L5 it is different. Rather than having #ifdef in usb.c (as I recently committed), this CL will move the clock logic into clock_enable_module() where it arguably belonged all the time. Additionally: Some of the chip families make use of a clock_mask in their implementation of clock_enable_module(), but since the module_id enum has more than 32 value, until now, some values (among those MODULE_USB) would result in overflow, causing new_mask to be identical to clock_mask, and the USB case could have never been reached. BUG=b:192262089 TEST=Compile servo_v4 without linker errors BRANCH=none Signed-off-by: Jes Bodi Klinke <jbk@chromium.org> Change-Id: I7c29339f45eb513e3e78f662797a70543912c8c7 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3130733 Reviewed-by: Scott Collyer <scollyer@chromium.org>
* ec: change usage of dummySam Hurst2020-08-051-3/+3
| | | | | | | | | | | | | | | | | | Google is working to change its source code to use more inclusive language. To that end, replace the term "dummy" with inclusive alternatives. BUG=b:162781382 BRANCH=None TEST=make -j buildall `grep -ir dummy *` The only results are in "private/nordic_keyboard/sdk8.0.0" which is not our code. Signed-off-by: Sam Hurst <shurst@google.com> Change-Id: I6a42183d998e4db4bb61625f962867fda10722e2 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2335737 Reviewed-by: Tom Hughes <tomhughes@chromium.org>
* Make wait_for_ready available for allDaisuke Nojiri2020-07-281-21/+3
| | | | | | | | | | | | | | | | | | | wait_for_ready is a generic function which loops until bits in a register are set. This patch move it to util.c to make it available for all. There are more places where the function is applicable but this CL keeps the scope under chip/stm32/clock-stm32. There is no functionality change. BUG=none BRANCH=none TEST=buildall Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Change-Id: I796599344c1d86ab7144d1d6b434ec54cf1cc55d Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2317887 Reviewed-by: Scott Collyer <scollyer@chromium.org>
* printf: Convert %l to %llEvan Green2019-10-051-2/+2
| | | | | | | | | | | | | | | | | | | | | In order to make our printf more standard, utilize %ll for long long arguments, rather than %l. This does cost a little bit in flash space for that extra l in a couple of places, but enables us to turn on compile-time printf format checking. For this commit only, the semantics are such that both %l and %ll take 64-bit arguments. In the next commit, %l goes to its correct behavior of taking a sizeof(long) argument. BUG=chromium:984041 TEST=make -j buildall BRANCH=none Cq-Depend:chrome-internal:1863686,chrome-internal:1860161,chrome-internal:1914029 Change-Id: I18081b55a8dbf5ef8ec15fc499ca75e59d31da58 Signed-off-by: Evan Green <evgreen@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1819652 Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
* chip/stm32/clock: Remove warning message about clock modulesNicolas Boichat2019-07-021-3/+0
| | | | | | | | | | | | | | | | It is not super-useful to print a warning message on every single boot about the fact that some module is not supported, and that takes up a bit of flash space. Let's remove it. BRANCH=none BUG=none TEST=none Change-Id: I04728aa5971675d8e93dcd397ebb259bfdd15bac Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1660520 Reviewed-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* ec: Remove extraneous new line as the end of CPRINTS stringsNicolas Boichat2019-06-201-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | CPRINTS already prints a new line, no need to add another one. Spotted during boot on kukui, and then realized there are many more instances: "" [3.689239 Module 7 is not supported for clock disable ] "" BRANCH=none BUG=none TEST=make buildall -j TEST=`git grep CPRINTS | grep "\\\\n\""` shows nothing of interest. Change-Id: I4d2bbbc65a91fa56c6e6115aa5c353bfd2b384a1 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1660519 Tested-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* LICENSE: remove unnecessary (c) after CopyrightTom Hughes2019-06-191-1/+1
| | | | | | | | | | | | | | | | Ran the following command: git grep -l 'Copyright (c)' | \ xargs sed -i 's/Copyright (c)/Copyright/g' BRANCH=none BUG=none TEST=make buildall -j Change-Id: I6cc4a0f7e8b30d5b5f97d53c031c299f3e164ca7 Signed-off-by: Tom Hughes <tomhughes@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1663262 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* common: replace 1 << digits, with BIT(digits)Gwendal Grignou2019-03-261-6/+6
| | | | | | | | | | | | | | | | Requested for linux integration, use BIT instead of 1 << First step replace bit operation with operand containing only digits. Fix an error in motion_lid try to set bit 31 of a signed integer. BUG=None BRANCH=None TEST=compile Change-Id: Ie843611f2f68e241f0f40d4067f7ade726951d29 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1518659 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* ec: Refactor get_rtc_diff to return unsigned valuesJack Rosenthal2019-03-201-1/+2
| | | | | | | | | | | | | | | | | | | | | get_rtc_diff in stm32 previously returned a signed value, but the result could never be negative. This changes the function to return an unsigned value in a safe manner, and updates its corresponding usage. The original patch set for this CL included a test for the get_rtc_diff functionality. This was removed since there was no easy way to make a host-side test of board-specific functionality. If this is going to be solved, I will write a separate CL. BUG=chromium:769407 BRANCH=none TEST=make buildall -j TEST=made unit test for get_rtc_diff; test passed (see note above) Change-Id: Iec1b274294d8f78eaa0ee66d3bd63ce69536e747 Signed-off-by: Jack Rosenthal <jrosenth@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/1493035 Reviewed-by: Jett Rink <jettrink@chromium.org>
* chip/stm32/clock: Enable STOP mode when the host sets wake alarmPhilip Chen2019-01-111-14/+39
| | | | | | | | | | | | | | | | | BUG=chromium:769503 BRANCH=scarlet TEST=make buildall -j TEST=On scarlet: 1) 'powerd_dbus_suspend --wakeup_timeout=10' on AP console. 2) When AP is in S3, confirm ec enters STOP mode by 'idlestat'. 3) Confirm AP still wakes up at the right time. Change-Id: I0ce60cc6c33cb475b3311de83c35fe73ff92641b Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/706537 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* Refactor ADC clock enable for STM32F0/F3Moritz Fischer2018-09-271-0/+10
| | | | | | | | | | | | | | Refactor ADC clock enable code to use clock_module_enable() BUG=none BRANCH=master TEST=Build and run on discovery-stm32f072 Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com> Change-Id: Id3e8852fd5dd2fe47351dd9b9f84b0be9fb82dda Reviewed-on: https://chromium-review.googlesource.com/1217602 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Reviewed-by: Nick Sanders <nsanders@chromium.org>
* stm32: move UART wake-up to uart codeVincent Palatin2018-06-131-24/+3
| | | | | | | | | | | | | | | | | | | Move the low-power mode UART register settings out of the STM32F0 low power mode code into the UART driver as a preparation for adding STM32H7 low power mode code. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=poppy BUG=b:75105319 TEST=make buildall Change-Id: Iecac8c387edd80c15fc3a211cf7969bbc6b8a15e Reviewed-on: https://chromium-review.googlesource.com/1096766 Commit-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
* system: Enable/Disable low power idle in run timePhilip Chen2018-05-301-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | We have enable_sleep()/disable_sleep() to enable/disable EC deep sleep mode in runtime. Here we introduce similar interfaces to enable/disable EC idle (sleep) mode. BUG=b:78792296 BRANCH=scarlet TEST=Confirm idle mode is enabled/disabled when enable_idle() and disable_idle() are called. Change-Id: I2484f08a066523441064968da99c47de9342ecf0 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/1072370 Reviewed-by: Randall Spangler <rspangler@chromium.org> Reviewed-by: Philip Chen <philipchen@chromium.org> Commit-Queue: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> (cherry picked from commit c6b6626cdccef04b0ff203aaed0d84dbdcecf8b7) Reviewed-on: https://chromium-review.googlesource.com/1076708 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
* stm32f0 / stm32f3: rtc: Fix register <-> time conversionShawn Nematbakhsh2017-12-111-4/+14
| | | | | | | | | | | | | | | | | | | | | us_to_rtcss() could return an invalid value when us approached 1 sec due to precision loss in the divisor. Change the calculation order to divide last to eliminate precision loss. BUG=b:68185182 BRANCH=None TEST=On scarlet, Verify hw clock closely matches reality w/ low-power idle. Verify EC doesn't watchdog for 5 hours in S5 / G3 w/ low-power idle. Verify suspend-stress-test still succeeds to wake device on alarm. Change-Id: Id40797dd4291e94a54a09bbbdbc1a7f7a00a01b4 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/818332 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Brian Norris <briannorris@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* chip/stm32/clock: Optionally use LSE as RTCCLKPhilip Chen2017-10-111-13/+13
| | | | | | | | | | | | | | | | | | | | The default RTCCLK comes from LSI, which can vary from 30kHz to 60kHz. To use stm32 RTC for applications requiring accurate timing, let's setup LSE (a more accurate clock source) as RTCCLK. Also fix a typo in register.h as 'BCDR' should be 'BDCR' globally. BUG=b:63908519 BRANCH=none TEST=boot scarlet rev1 and wait for an hour, confirm rtc time == kernel system time. Change-Id: If4728bdd3b6384316e5337004a49c172eaec869d Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/679601 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* chip/stm32/clock: Wakeup AP when rtc alarm goes offPhilip Chen2017-09-281-0/+11
| | | | | | | | | | | | | | BUG=b:63908519 BRANCH=none TEST='powerd_dbus_suspend --wakeup_timeout=10' and see AP do S0->S3(10 secs)->S0 Change-Id: I35e248627e2f3b68b0ed3f27d6bae65eb73a745b Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/674054 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* chip/stm32/clock: Incorporate RTC date registerPhilip Chen2017-09-271-7/+13
| | | | | | | | | | | | | | | | | | | | | | | The current stm32 rtc driver only uses RTC_TR and RTC_SSR. So we son't be able to use rtc for applications which need time > 24 hours. To support such applications, this patch adds operations for RTC date register (RTC_DR). BUG=b:63908519 CQ-DEPEND=CL:666985 BRANCH=none TEST=manually with 'ectool rtcset/rtcset' and '/sys/class/rtc/rtc0', verify the conversion between calendar time and Unix epoch time works. Change-Id: Iacd5468502e4417a70880d7239ca5e03353d9469 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/659337 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Shawn N <shawnn@chromium.org>
* chip/stm32/clock: Support RTC console/host commandsPhilip Chen2017-08-231-0/+21
| | | | | | | | | | | | | | | | Add the driver for RTC console/host commands on stm32f0. BUG=b:63908519 BRANCH=none TEST=on scarlet, manually test 'rtc'/'rtc set' on ec console and 'ectool rtcget/rtcset/rtcgetalarm/rtcsetalarm' on ap console. Change-Id: I71035c91ed69fa5f65448618ff8bd1a37427eaad Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://chromium-review.googlesource.com/627637 Commit-Ready: Philip Chen <philipchen@chromium.org> Tested-by: Philip Chen <philipchen@chromium.org> Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
* usb: activate CRS on STM32F0Sam Hurst2017-01-261-0/+22
| | | | | | | | | | | | | | | | | | | | | Enable the Clock Recovery Subsystem to automatically adjust the internal HSI48 clock for proper USB operation on the STM32F0. BUG=chrome-os-partner:34160 TEST=Manual testing on STM32F072B-DISCOVERY Plugged in board and verified that device was detected with dmesg. [1400698.702999] usb 3-10: new full-speed USB device number 47 using xhci_hcd [1400698.720063] usb 3-10: New USB device found, idVendor=18d1, idProduct=500f [1400698.720069] usb 3-10: New USB device strings: Mfr=1, Product=2, SerialNumber=0 [1400698.720072] usb 3-10: Product: PDeval-stm32f072 [1400698.720075] usb 3-10: Manufacturer: Google Inc. BRANCH=none Change-Id: I496a9a121a4b1a0009fe04cfe24aaa693ada9236 Reviewed-on: https://chromium-review.googlesource.com/433059 Commit-Ready: Sam Hurst <shurst@google.com> Tested-by: Sam Hurst <shurst@google.com> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* cleanup: DECLARE_CONSOLE_COMMAND only needs 4 argsBill Richardson2016-08-241-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Since pretty much always, we've declared console commands to take a "longhelp" argument with detailed explanations of what the command does. But since almost as long, we've never actually used that argument for anything - we just silently throw it away in the macro. There's only one command (usbchargemode) that even thinks it defines that argument. We're never going to use this, let's just get rid of it. BUG=none BRANCH=none CQ-DEPEND=CL:*279060 CQ-DEPEND=CL:*279158 CQ-DEPEND=CL:*279037 TEST=make buildall; tested on Cr50 hardware Everything builds. Since we never used this arg anyway, there had better not be any difference in the result. Change-Id: Id3f71a53d02e3dc625cfcc12aa71ecb50e35eb9f Signed-off-by: Bill Richardson <wfrichar@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/374163 Reviewed-by: Myles Watson <mylesgw@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
* stm32f446e-eval: add support for stm32f446Nick Sanders2016-08-171-186/+6
| | | | | | | | | | | | | | | | | | This adds basic support for the stm32f446. This consists of: * New DMA model for stm32f4 * New clock domain support. * MCO oscillator gpio export support. * Flash support for irregular blocks. BUG=chromium:608039 TEST=boots w/ correct clock, stm32f0 also boots. BRANCH=None Change-Id: I1c5cf6ddca09009c9dac60da8a3d0c5ceedfcf4d Signed-off-by: Nick Sanders <nsanders@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/363992 Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
* stm32: Don't use HSI48 clock for chips which don't support itShawn Nematbakhsh2015-12-111-1/+4
| | | | | | | | | | | | | | | | | | stm32f03x and stm32f070 officially do not support an HSI48 clock, so configure our 48MHz clock using HSI8 and PLL. BUG=chromium:568717 BRANCH=None TEST=Verify snoball 1us timer is accurate and we can execute approximately 48 million NOPs in a second. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Ice74de98f18908e53e94f2d95a2ec3cae53e2347 Reviewed-on: https://chromium-review.googlesource.com/317459 Commit-Ready: Shawn N <shawnn@chromium.org> Tested-by: Shawn N <shawnn@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* oak_pd: add initial support for oak PDAlec Berg2015-05-271-0/+41
| | | | | | | | | | | | | | | Add initial support for Oak PD MCU on rev1 boards. This does not include USB PD communication. BUG=none BRANCH=none TEST=build and load on oak and get console. test we resond to host commands from EC using "pdcmd 0 0" on EC console. Change-Id: I92045cf0fd682279ada6c286f5399f0e258a6305 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/271828
* stm32f0: Fix RTC read glitchShawn Nematbakhsh2015-02-281-1/+7
| | | | | | | | | | | | | | | | Reads to RTC_SSR may be invalid if they occur close to the RTCCLK edge. As suggested by the datasheet, perform consecutive identical reads to ensure the read is valid. BUG=chrome-os-partner:37216 TEST=Manual on Samus. Repeatedly call rtc_read in test function, verify that RTC_SSR never incorrectly ticks up. BRANCH=Samus Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Ib26fbfab4a07263f638c580066e993675dd8c451 Reviewed-on: https://chromium-review.googlesource.com/254725 Reviewed-by: Alec Berg <alecaberg@chromium.org>
* stm32f0: fix handling of RTC alarm 24 hour rolloverAlec Berg2015-02-221-0/+6
| | | | | | | | | | | | | | | | | | | | Fix bug in RTC module for stm32f0 in which it doesn't handle the 24 hour rollover appropriately and can cause a watchdog reset if in deep sleep during rollover. BUG=chrome-os-partner:36920 BRANCH=samus TEST=add line to rtc_init() STM32_RTC_TR = 0x00235952 This initializes RTC clock to 8 seconds before rollover. Using samus make sure unit is allowed to go to deep sleep (S3/S5 and not charging) and see that without this CL we watchdog most of the time, and with this CL we don't watchdog ever. Change-Id: I3f4b4b1ab7b2be1d4e344477d5eaaa0dc916773a Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/251852 Reviewed-by: Alexandru Stan <amstan@chromium.org>
* make idlestats console command optionalVincent Palatin2015-02-181-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | To save flash space, disable "idlestats" console command on samus_pd. This saves 384 B of flash Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=samus BUG=chrome-os-partner:34489 TEST=make buildall and check firmware size. === build/samus_pd/ BASELINE === FLASH 57.8k / 60.0k [ text 48.0k rodat 9.7k data 0.1k ] RAM 11.8k / 16.0k [ data 0.1k bss 11.7k ] === #undef CONFIG_CMD_IDLE_STATS === FLASH 57.4k / 60.0k [ text 47.9k rodat 9.4k data 0.1k ] RAM 11.8k / 16.0k [ data 0.1k bss 11.7k ] Change-Id: Iba9654a88ec195026945881bc2687a1e67747706 Reviewed-on: https://chromium-review.googlesource.com/241452 Reviewed-by: Alec Berg <alecaberg@chromium.org> Commit-Queue: Alec Berg <alecaberg@chromium.org> Tested-by: Alec Berg <alecaberg@chromium.org>
* stm32f0: Change idle task warning printf to save stack spaceAlec Berg2015-02-161-1/+2
| | | | | | | | | | | | | | | | | | Change the idle task overslept warning printf to save stack space. The current warning uses CPRINTF which adds too much to the stack and overflows the idle stack. BUG=chrome-os-partner:33138, chrome-os-partner:36636 BRANCH=samus TEST=comment out the if (margin_us < 0) check and always print warning message. Without this CL stack overflows. With this CL, stack does not overflow and gets to 168/256, which is plenty of headroom considering the task doesn't do much. Change-Id: I19a8336b8584d2a1342e7b9290aad471d326a060 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/250300 Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
* stm32: Add delay after enabling peripheral clockVic Yang2015-02-101-0/+13
| | | | | | | | | | | | | | | | | We need a dummy read after enabling AHB peripheral clock before we can access the peripheral. For APB, we also need a dummy read for STM32F3. BRANCH=All affected BUG=chrome-os-partner:33007 TEST=make buildall Change-Id: I47f4a024dca294f555428c3f2053c1d32835ebe0 Signed-off-by: Vic Yang <victoryang@google.com> Reviewed-on: https://chromium-review.googlesource.com/246181 Reviewed-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org> Tested-by: Vic Yang <victoryang@chromium.org> Commit-Queue: Vic Yang <victoryang@chromium.org>
* stm32: remove useless moduloVincent Palatin2015-01-141-1/+1
| | | | | | | | | | | | | | | | | | | | | The RTC delay is always less than a day (see the assert at the beginning of set_rtc_alarm), so remove the useless module to save a few bytes of flash. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=samus BUG=none TEST=make buildall and see the zinger firmware is smaller by 16 bytes (more than the 8 bytes I need to submit the following CL) Change-Id: If0374ff5897f13e69574018d2123428075b2264e Reviewed-on: https://chromium-review.googlesource.com/240564 Reviewed-by: Alec Berg <alecaberg@chromium.org> Trybot-Ready: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
* Zinger: honor disable_sleep()Vincent Palatin2014-11-181-1/+1
| | | | | | | | | | | | | | | | | | | Extend the Zinger runtime to take into account the disable_sleep() issued by the USB protocol stack and avoid going into deep-sleep while connected. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=samus BUG=none TEST=connect Zinger to a PD power sink (Twinkie) and monitor the stop mode entry/exit on a GPIO. Change-Id: I04e35fdd65f3be3da7a4304dc1a92e6268930888 Reviewed-on: https://chromium-review.googlesource.com/230340 Reviewed-by: Alec Berg <alecaberg@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
* ryu: Enable low power idle for P2 boardsVic Yang2014-10-301-2/+5
| | | | | | | | | | | | | | | | | Now that the problem with UART in STOP mode is fixed, let's enable low power idle for Ryu P2 boards. BRANCH=None BUG=chrome-os-partner:33219 TEST=Shut down the AP and unplug AC power. Check the EC goes into deep-sleep by 'idlestat'. TEST=Power up the AP and check the EC stays awake. Change-Id: Ib8ad3763407315ec0f95551fa0fdd258a060e113 Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/226312 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org>
* stm32f0: stm32f3: Wake from STOP mode on UART start bitVic Yang2014-10-281-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | By default, UART wakes the chip up on RXNE interrupt. This means when the chip wakes up, RDR is full and only the shift register is empty, and this leaves us only the time of a single character to process the character in RDR. On some system, this is not enough and the first (or even the second) character is overrun, and thus any multi-character keys (e.g. arrow keys) break. To avoid this problem, let's change the wake source to wake on start bit detection. This gives us the time for one more character to wake up and process the console input. BRANCH=None BUG=chrome-os-partner:33219 TEST=Enable low power mode on Ryu P2. In STOP mode, hit up arrow key and see the last command show up. Change-Id: Idce4c0bdfcf3e04ad84152ba525f704a0909f115 Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/225771 Reviewed-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@google.com>
* stm32f3: Use the correct RTC ALARM IRQVic Yang2014-10-231-2/+2
| | | | | | | | | | | | | | | | | | | | On STM32F0, a single IRQ is used for all RTC events, including RTC_ALARM and RTC_WAKEUP, and this IRQ is named RTC_WAKEUP. We use RTC_WAKEUP IRQ in our code while we actually meant to capture RTC alarm event. On STM32F3, RTC_WAKEUP and RTC_ALARM are separate IRQs and thus we're having problem. Let's make it explicit which RTC IRQ we want to use and fix our code to use RTC_ALARM. BRANCH=None BUG=chrome-os-partner:33219 TEST=Run 'rtc_alarm' on Ryu and verify the EC gets interrupted after a second. Change-Id: Ib1a14a5da49d709a4d071d44fbfa46544cc5929b Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/224998 Reviewed-by: Alec Berg <alecaberg@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* Fix clock bug on STM32F0 that HSI48 isn't enabledVic Yang2014-10-221-2/+13
| | | | | | | | | | | | | | | | | | | When changing the clock init code for STM32F3, I accidentally disabled HSI48 for STM32F0, which is causing all problems on all STM32F0 platforms. Re-enable it. BRANCH=Samus BUG=chrome-os-partner:32660 TEST=Boot on Ryu P1 and see console. Change-Id: Ie343cdb039d839e41b36489388fc91970e2bb7d8 Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/225002 Reviewed-by: Anatol Pomazau <anatol@google.com> Tested-by: Anatol Pomazau <anatol@google.com> Reviewed-by: Todd Broch <tbroch@chromium.org> Tested-by: Todd Broch <tbroch@chromium.org> Reviewed-by: Alec Berg <alecaberg@chromium.org>
* Add new build target ryu_p2 for Ryu P2 boardsVic Yang2014-10-221-8/+31
| | | | | | | | | | | | | | | | | | | | | | | | | The new build target ryu_p2 is mostly based on ryu. On ryu_p2, we have a new EC chip with bigger flash, so make the corresponding changes: - Pinout changes - HW Timer: TIM5 - USB PD Tx Timer: TIM3_CH4 - USB PD Rx Timer: TIM2_CH4 - Use UART2 for EC console - Disable UART Tx DMA as it conflicts with USB PD Tx DMA - Use 24MHz HSE x2 = 48MHz for SYSCLK BRANCH=None BUG=chrome-os-partner:32660 TEST=Sanity check on a new board: - i2cscan - PD negotiation - UART console - gettime Change-Id: I4ef6b53a928a2777721e3874032aeb0e6b2b4c92 Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/221404 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* stm32f: stm32f0: guard hibernate function with CONFIG_HIBERNATEVic Yang2014-10-081-0/+2
| | | | | | | | | | | | | | If CONFIG_HIBERNATE is explicitly undefined for a platform, we shouldn't try to hibernate. BUG=chrome-os-partner:32727 TEST=None BRANCH=None Change-Id: Id0f93a3a694065478373e364d82589ff08e7d980 Signed-off-by: Vic Yang <victoryang@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/222013 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* zinger: add low power stop modeAlec Berg2014-09-291-17/+22
| | | | | | | | | | | | | | | | Add low power mode for zinger. This uses stop mode in task_wait_event(), the non-runtime equivalent of the idle task. BUG=chrome-os-partner:28335 BRANCH=samus TEST=load onto zinger and plug and unplug into samus a bunch of times to make sure it negotiates to 20V every time. also send custom vdm's from samus_pd and make sure those always succeed. Change-Id: I626365e7d22e030792d28dbf7eafaeb8f54f8a74 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/219933 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* stm32f0: enable flash prefetch bufferAlec Berg2014-09-251-2/+5
| | | | | | | | | | | | | | | | Enable flash prefetch buffer for stm32f0 chips to make for faster CPU execution. BUG=none BRANCH=none TEST=load onto samus_pd and zinger. let run for a while. connect/disconnect AC a few times. boot samus. Change-Id: I88c0ae67a3205987344552f5b44952f9890c8177 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/219921 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-by: Alexandru Stan <amstan@chromium.org>
* stm32f0: samus_pd: add hibernate and enable wake pins for samusAlec Berg2014-09-241-0/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add hibernate functionality for stm32f0, and enable wake pins for samus PD MCU. Samus wake pins are VBUS present on either port. BUG=chrome-os-partner:31226 BRANCH=none TEST=load onto samus PD. test hibernate console command: > hibernate 0 500000 Hibernating for 0.500000 s (5 seconds later) --- UART initialized after reboot --- [Reset cause: hibernate] ... > hibernate Hibernating until wake pin asserted. (plug in AC) --- UART initialized after reboot --- [Reset cause: hibernate] Change-Id: Ib86f2677721df29e7bf6975e239de79c25a38795 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/219105 Reviewed-by: Todd Broch <tbroch@chromium.org> Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* stm32f0: low power idle taskAlec Berg2014-09-221-22/+168
| | | | | | | | | | | | | | | | | | | Add low power idle task to stm32f0. This can be enabled by defining CONFIG_LOW_POWER_IDLE. This low power idle uses STOP mode to conserve power. BUG=chrome-os-partner:31226, chrome-os-partner:28335 BRANCH=none TEST=add #define CONFIG_LOW_POWER_IDLE to samus and use idlestats console command to verify using deep sleep. also #define CONFIG_FORCE_CONSOLE_RESUME and make sure serial console works without problems when going into deep sleep. Change-Id: I76b0ceb8587a139faa74353d3d8efb4f689fc669 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/218956 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* stm32f0: add RTC alarm functionalityAlec Berg2014-09-191-0/+206
| | | | | | | | | | | | | | | | Implement RTC alarm, with resolution 50us, for stm32f0. This is useful for using low power modes and waking up after set period of time. BUG=chrome-os-partner:31226, chrome-os-partner:28335 BRANCH=none TEST=tested on samus_pd with CONFIG_CMD_RTC_ALARM defined and used rtc_alarm console command to test various timeout periods. Change-Id: Ibabd8662cfbea654c7de387669f7be83af4fd79d Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/218322 Reviewed-by: Todd Broch <tbroch@chromium.org>
* stm32: pd: add config option to use SPI master for USB PD trasmitAlec Berg2014-04-291-8/+48
| | | | | | | | | | | | | | | | | | | | | | | Added config option CONFIG_USB_PD_TX_USES_SPI_MASTER which switches to use SPI master for PD transmit. The advantage of SPI master mode is at the end of the tranmission, we don't have to send any dummy 0 bits. When the option is set, the CPU_CLOCK must be set to 38.4MHz, so that the SPI master can generate the correct clock frequency. BUG=chrome-os-partner:28309 BRANCH=none TEST=Tested by connecting two fruitpies together across CC1. One fruitpie has been modified such that the MISO and MOSI lines are swapped and is running PD TX in SPI master mode with 38.4MHz clock, while the other is running PD TX in SPI slave mode. On EC console ran pd charger on one board and pd dev on other board. Verified that communication works with no errors. Ran for 10 minutes in each configuration. Change-Id: Ib24030d34d95d59f4ac6c2dae98bf7adda1ada01 Signed-off-by: Alec Berg <alecaberg@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/197215 Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
* stm32: add support for STM32F0xx familyVincent Palatin2014-03-111-0/+61
Add support for the STM32F0xx family of devices using a Cortex-M0 core and slightly newer peripherals than F1xx family. Signed-off-by: Vincent Palatin <vpalatin@chromium.org> BRANCH=none BUG=none TEST=run EC console on STM32F072B Discovery board. and pass all available unit-tests on target. Change-Id: Idaa3fcbf1c0da8a8f448c0e88e58bfd976b0a735 Reviewed-on: https://chromium-review.googlesource.com/188983 Reviewed-by: Vincent Palatin <vpalatin@chromium.org> Commit-Queue: Vincent Palatin <vpalatin@chromium.org> Tested-by: Vincent Palatin <vpalatin@chromium.org>
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