| Commit message (Collapse) | Author | Age | Files | Lines |
|---|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
In the interest of making long-term branch maintenance incur as little
technical debt on us as possible, we should not maintain any files on
the branch we are not actually using.
This has the added effect of making it extremely clear when merging CLs
from the main branch when changes have the possibility to affect us.
The follow-on CL adds a convenience script to actually pull updates from
the main branch and generate a CL for the update.
BUG=b:204206272
BRANCH=ish
TEST=make BOARD=arcada_ish && make BOARD=drallion_ish
Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I17e4694c38219b5a0823e0a3e55a28d1348f4b18
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3262038
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Tom Hughes <tomhughes@chromium.org>
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
As most of the peripherals were not implemented to support switching to
16-MHz HSI (e.g. high speed serial port requires a clock input > 24
Mhz), implement a simpler clock scheme than the dynamic between HSI and
PLL used other platforms:
- the PLL is disabled only when entering the low-power idle and the PLL
locking time is added to wake-up time.
- when the host is running (not suspended) we stay in a high power mode
(~20mW).
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=b:130561737
TEST=manual, on bloonchipper, check we can still capture fingerprint.
read the MCU power consumption: pp3300_dx_mcu_mw is 2.367 mW.
BRANCH=fpmcu-bloonchipper
Change-Id: Ic1fe015b2501bdea9779a2f63fab296f8812c315
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2555162
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Implement a low power idle mode using the STM32F4 STOP mode.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=b:130561737
TEST=manual, on bloonchipper, check we can still capture fingerprint.
read the MCU power consumption.
BRANCH=fpmcu-bloonchipper
Change-Id: I11249e9b68c989033263e34e1cde3f19ffe7c54c
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2537631
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
On STM32F4, when converting micro-seconds to the RTC sub-second counter
value, the current computation in the us_to_rtcss() routine has a large
rounding error which can even led to generate a negative value.
When such a negative value is output and then programmed in the
(unsigned) RTC_ALRMASSR register used to set the alarm precise
sub-second timestamp, it might put a wrong value in the past.
As a consequence when the RTC alarm is used a wake-up mechanism for the
low power idle, it might never fired and trigger a watchdog reboot.
An example of bad values on a STM32F412 with the RTC driven by the
32-kHz LSI:
- RTC_PREDIV_A = 1
- RTC_FREQ = (STM32F4_LSI_CLOCK / (RTC_PREDIV_A + 1) = 16000 /* Hz */
- RTC_PREDIV_S = (RTC_FREQ - 1) = 15999
- US_PER_RTC_TICK = 1000000 / RTC_FREQ = 62 /* rounded from 62.5 */
When converting 996000 us,
us_to_rtcss(996000) = RTC_PREDIV_S - (us / US_PER_RTC_TICK)
= 15999 - (996000 / 62)
= -65
returned as a uint32_t as 0xfffffffb.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=b:130561737
TEST=manual, with the STOP mode enabled, we no longer see watchdog
reboot due to the RTC alarm being set in the past and never firing.
TEST=manual, verify that the output of the 'gettime' console command is not
drifting compared to the wall clock when the low power idle using the
RTC time is used.
BRANCH=fpmcu-bloonchipper
Change-Id: I53869539828bed9a5900d29407b5feba140b8217
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2563684
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Allow to transition between the PLL to run at full speed
and the bare HSI (internal RC oscillator at 16Mhz) to save power.
On HSI, as our sysclk frequency is low, we run all peripheral clocks
undivided at the same frequency.
Keep the configuration for other platforms running from the HSE
(external crystal)
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BUG=b:130561737
TEST=manual, verify the timers are working by checking the output of the
'gettime' console command against the wall clock.
TEST=manual, verify the UART console works as expected.
TEST=measure MCU power on bloonchipper in various modes through the INA:
PLL 19.20 mW HSI 4.73 mW STOP 2.10 mW
BRANCH=fpmcu-bloonchipper
Change-Id: I1185e04c9a7819fec05dd643b7026116b146f3b8
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2527049
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Google is working to change its source code to use more inclusive
language. To that end, replace the term "dummy" with inclusive
alternatives.
BUG=b:162781382
BRANCH=None
TEST=make -j buildall
`grep -ir dummy *`
The only results are in "private/nordic_keyboard/sdk8.0.0"
which is not our code.
Signed-off-by: Sam Hurst <shurst@google.com>
Change-Id: I6a42183d998e4db4bb61625f962867fda10722e2
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2335737
Reviewed-by: Tom Hughes <tomhughes@chromium.org>
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
wait_for_ready is a generic function which loops until bits in a
register are set. This patch move it to util.c to make it available
for all.
There are more places where the function is applicable but this CL
keeps the scope under chip/stm32/clock-stm32. There is no
functionality change.
BUG=none
BRANCH=none
TEST=buildall
Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org>
Change-Id: I796599344c1d86ab7144d1d6b434ec54cf1cc55d
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2317887
Reviewed-by: Scott Collyer <scollyer@chromium.org>
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
For the STM32F4 chip family, this software reset of the backup domain
causes the RTC backup registers to be reset, which causes all backup
data to be lost.
The reset flag was not impacted because it's copied out before this
reset.
BRANCH=none
BUG=b:157059753
TEST=make -j BOARD=bloonchipper test-scratchpad
On console:
> runtest
=> PASS
> reboot
> runtest
=> FAIL, which is CORRECT
Signed-off-by: Yicheng Li <yichengli@chromium.org>
Change-Id: I85777b7d8a99561198d0b9dc1f795b8f8f6e26c7
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2226955
Reviewed-by: Tom Hughes <tomhughes@chromium.org>
Commit-Queue: Tom Hughes <tomhughes@chromium.org>
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
It is not super-useful to print a warning message on every single
boot about the fact that some module is not supported, and that
takes up a bit of flash space. Let's remove it.
BRANCH=none
BUG=none
TEST=none
Change-Id: I04728aa5971675d8e93dcd397ebb259bfdd15bac
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1660520
Reviewed-by: Yilun Lin <yllin@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
CPRINTS already prints a new line, no need to add another one.
Spotted during boot on kukui, and then realized there are many
more instances:
""
[3.689239 Module 7 is not supported for clock disable
]
""
BRANCH=none
BUG=none
TEST=make buildall -j
TEST=`git grep CPRINTS | grep "\\\\n\""` shows nothing of
interest.
Change-Id: I4d2bbbc65a91fa56c6e6115aa5c353bfd2b384a1
Signed-off-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1660519
Tested-by: Daisuke Nojiri <dnojiri@chromium.org>
Reviewed-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
|
| |
|
|
|
|
|
|
|
|
|
|
|
| |
Implement rtc_set() function for STM32F4 chip variant
BUG=none
BRANCH=none
TEST=Using eval-board, use rtc set 0, observe increments
Change-Id: I63abe0c388b7a0ba9ed881b393ffdbcc69e6d75a
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
Reviewed-on: https://chromium-review.googlesource.com/1401017
Reviewed-by: Philip Chen <philipchen@chromium.org>
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
Make ADCs on STM32F4 chips work by reusing most of the STM32F3 code
with the addition of SWSTART=1 bit in adc_read_channel.
The SWSTART=1 is most likely also required for the F3, but could
not be tested on actual hardware.
BUG=none
BRANCH=master
TEST=Build for nucleo-411RE and check measurements
Signed-off-by: Moritz Fischer <moritz.fischer@ettus.com>
Change-Id: Iea4f961b22119b5f2c1ee71295ec3ef1b7b7232c
Reviewed-on: https://chromium-review.googlesource.com/1217603
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Reviewed-by: Nick Sanders <nsanders@chromium.org>
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
The default RTCCLK comes from LSI, which can vary from 30kHz to 60kHz.
To use stm32 RTC for applications requiring accurate timing, let's setup
LSE (a more accurate clock source) as RTCCLK.
Also fix a typo in register.h as 'BCDR' should be 'BDCR' globally.
BUG=b:63908519
BRANCH=none
TEST=boot scarlet rev1 and wait for an hour,
confirm rtc time == kernel system time.
Change-Id: If4728bdd3b6384316e5337004a49c172eaec869d
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/679601
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
The current stm32 rtc driver only uses RTC_TR and RTC_SSR.
So we son't be able to use rtc for applications which need
time > 24 hours.
To support such applications, this patch adds operations
for RTC date register (RTC_DR).
BUG=b:63908519
CQ-DEPEND=CL:666985
BRANCH=none
TEST=manually with 'ectool rtcset/rtcset' and '/sys/class/rtc/rtc0',
verify the conversion between calendar time and Unix epoch time works.
Change-Id: Iacd5468502e4417a70880d7239ca5e03353d9469
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://chromium-review.googlesource.com/659337
Commit-Ready: Philip Chen <philipchen@chromium.org>
Tested-by: Philip Chen <philipchen@chromium.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
The STM32F76x is really close to the STM32F4 family, so the most concise
implementation is just using CHIP_FAMILY_STM32F4 and adding
CHIP_VARIANT_F76X.
Tune the clock settings to 180 Mhz CPU clock as the goal is performance.
(over-drive is not implemented yet to get to 216 Mhz)
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=none
BUG=none
TEST=ran on nucleo-f767zi board.
'make BOARD=nucleo-f767 flash', the red LED is on and the green LED
turns on/off when pressing the user button, UART console works properly.
Change-Id: I1f67df3aec874c965c81188df46c72de210728d9
Reviewed-on: https://chromium-review.googlesource.com/612750
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Shawn N <shawnn@chromium.org>
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
|
| |
On stm32f412, AHB prescaler must be 1 in order for stm32f412 to be
clocked at greater than 50MHz. APBX prescaler must be 2 so the clocks
can be in the right range. When APBX prescaler != 1, it results in 2x
timer clocks on both APB1 and APB2. We added a new
clock_get_timer_freq() function for stm32 to get timer specific clock
frequency so we can return 2x timer clocks when APBX != 1.
Flash latencies also need to be changed when we clock at 96MHz, the
FLASH_ACR_LATENCY defines are moved into the variant-specific switches
so each board can defined latency when setting CPU clocks.
BUG=b:38077127
TEST=`make BOARD=rose -j`, touch performance improved by 2x.
Change-Id: Ieb211ad80c168d3f57e72a8d16b954b703ee1444
Reviewed-on: https://chromium-review.googlesource.com/539375
Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org>
Tested-by: Wei-Ning Huang <wnhuang@chromium.org>
Reviewed-by: Rong Chang <rongchang@chromium.org>
|
| |
|
|
|
|
|
|
|
|
|
|
|
|
| |
Add clock definition for stmf412. New stm32f4 chip variant will have to
define their own clock definitions.
BUG=b:37187312
TEST=`make BOARD=rose- j`
Change-Id: Ie053298d2f1255d7bc152f6018a674281bda7004
Reviewed-on: https://chromium-review.googlesource.com/487848
Commit-Ready: Wei-Ning Huang <wnhuang@chromium.org>
Tested-by: Wei-Ning Huang <wnhuang@chromium.org>
Reviewed-by: Rong Chang <rongchang@chromium.org>
|
|
|
This adds basic support for the stm32f446.
This consists of:
* New DMA model for stm32f4
* New clock domain support.
* MCO oscillator gpio export support.
* Flash support for irregular blocks.
BUG=chromium:608039
TEST=boots w/ correct clock, stm32f0 also boots.
BRANCH=None
Change-Id: I1c5cf6ddca09009c9dac60da8a3d0c5ceedfcf4d
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/363992
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
|
